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  • HT24LC02图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • HT24LC02 现货库存
  • 数量6980 
  • 厂家ROHM 
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  • HT24LC02图
  • 集好芯城

     该会员已使用本站13年以上
  • HT24LC02
  • 数量13346 
  • 厂家HOLTEK/合泰 
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  • 北京首天国际有限公司

     该会员已使用本站16年以上
  • HT24LC02J
  • 数量8287 
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  • HT24LC02图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • HT24LC02
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  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • HT24LC02
  • 数量12300 
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  • 深圳市三得电子有限公司

     该会员已使用本站15年以上
  • HT24LC02
  • 数量82000 
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  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
  • HT24LC02
  • 数量32222 
  • 厂家HOLTEK/合泰 
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  • HT24LC02图
  • 深圳市湘达电子有限公司

     该会员已使用本站10年以上
  • HT24LC02
  • 数量6600 
  • 厂家HOLTEK/合泰 
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  • HT24LC02图
  • 上海熠富电子科技有限公司

     该会员已使用本站15年以上
  • HT24LC02
  • 数量15000 
  • 厂家HOLTEK 
  • 封装N/A 
  • 批号2024 
  • 上海原装现货库存,欢迎查询!
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  • HT24LC02  SMD图
  • 北京首天国际有限公司

     该会员已使用本站16年以上
  • HT24LC02 SMD
  • 数量9682 
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  • HT24LC02-8SOP--图
  • 北京中其伟业科技有限公司

     该会员已使用本站16年以上
  • HT24LC02-8SOP--
  • 数量9221 
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  • HT24LC02图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • HT24LC02
  • 数量34243 
  • 厂家HOTEK 
  • 封装SOP-8 
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • HT24LC02
  • 数量13050 
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  • HT24LC02图
  • 深圳市富科达科技有限公司

     该会员已使用本站13年以上
  • HT24LC02
  • 数量21688 
  • 厂家HOLTEK 
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  • HT24LC02图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • HT24LC02
  • 数量18300 
  • 厂家HOLTEK 
  • 封装SOP8 
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  • HT24LC02图
  • 绿盛电子(香港)有限公司

     该会员已使用本站12年以上
  • HT24LC02
  • 数量2015 
  • 厂家HOLTEK 
  • 封装8DIP 
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  • 深圳市惊羽科技有限公司

     该会员已使用本站11年以上
  • HT24LC02
  • 数量78800 
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  • 批号▉▉:2年内 
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  • HT24LC02图
  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • HT24LC02
  • 数量800 
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  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • HT24LC02
  • 数量5369 
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  • HT24LC02图
  • 深圳市创芯联科技有限公司

     该会员已使用本站9年以上
  • HT24LC02
  • 数量30000 
  • 厂家HOLTEK 
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  • HT24LC02图
  • 深圳市宇川湘科技有限公司

     该会员已使用本站6年以上
  • HT24LC02
  • 数量12660 
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  • HT24LC02图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • HT24LC02
  • 数量9689 
  • 厂家HOLTEK(合泰/盛群) 
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  • HT24LC02图
  • 上海磐岳电子有限公司

     该会员已使用本站11年以上
  • HT24LC02
  • 数量5800 
  • 厂家holtek(合泰 
  • 封装sopdip 
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  • HT24LC02图
  • 深圳市珩瑞科技有限公司

     该会员已使用本站2年以上
  • HT24LC02
  • 数量8000 
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  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • HT24LC02
  • 数量188971 
  • 厂家HOLTEK/合泰 
  • 封装SOP8 
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  • ★只做原装★正品现货★原盒原标★
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  • HT24LC02-8SOPLF图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • HT24LC02-8SOPLF
  • 数量3827 
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  • 深圳市恒佳微电子有限公司

     该会员已使用本站12年以上
  • HT24LC02
  • 数量
  • 厂家2644 
  • 封装SOP8 
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  • HT24LC02图
  • 北京元坤伟业科技有限公司

     该会员已使用本站17年以上
  • HT24LC02
  • 数量5000 
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  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • HT24LC02
  • 数量65000 
  • 厂家HOLTEK(台湾合泰/盛群) 
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  • HT24LC02/8NSOPT/R图
  • 深圳市凯睿晟科技有限公司

     该会员已使用本站10年以上
  • HT24LC02/8NSOPT/R
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  • HT24LC02  SMD图
  • 上海金庆电子技术有限公司

     该会员已使用本站15年以上
  • HT24LC02 SMD
  • 数量24184 
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  • 深圳市奥伟斯科技有限公司

     该会员已使用本站7年以上
  • HT24LC02
  • 数量20203 
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产品型号HT24LC02的概述

芯片HT24LC02的概述 HT24LC02是一款常用的I2C通信EEPROM (Electrically Erasable Programmable Read-Only Memory),由惠州华大半导体公司(Holtek Semiconductor)制造。作为一款高性能的存储器件,HT24LC02广泛应用于各种嵌入式系统中,尤其适合需要长时间存储数据的场合。该芯片以其低功耗、高可靠性和灵活性,成为许多电子项目中的首选存储解决方案。 HT24LC02具备256 × 8位的存储容量,支持I2C总线协议,可以实现多芯片连接。该芯片提供了一些重要的特性,例如可自行读写的存储空间、可靠的地址识别、数据擦写和再编程能力,以及一定的写保护功能。通过这些特性,HT24LC02能够在各种条件下稳定运行,并保障数据的安全性。 芯片HT24LC02的详细参数 - 存储容量:256 × 8 位(32字节) ...

产品型号HT24LC02的Datasheet PDF文件预览

HT24LC01/02  
1K/2K 2-Wire CMOS Serial EEPROM  
Features  
Operating voltage: 2.4V~5.5V  
Partial page write allowed  
Low power consumption  
8-byte Page write modes  
Write operation with built-in timer  
Hardware controlled write protection  
Operation: 5mA max.  
Standby: 5µA max.  
Internal organization  
40-year data retention  
1K (HT24LC01):128×8  
106 erase/write cycles per word  
2K (HT24LC02): 256×8  
8-pin DIP/SOP package  
2-wire serial interface  
Write cycle time: 5ms max.  
Automatic erase-before-write operation  
8-pin TSSOP (HT24LC02 only)  
Commerical temperature range  
(0°C to +70°C)  
General Description  
Th e H T24LC01/02 is a 1K/2K-bit ser ia l  
read/write non-volatile memory device using  
the CMOS floating gate process. Its 1024/2048  
bits of memory are organized into 128/256  
words and each word is 8 bits. The device is  
optimized for use in many industrial and com-  
mercial applications where low power and low  
voltage operation are essential. Up to eight  
HT24LC01/02 devices may be connected to the  
same two-wire bus. The HT24LC01/02 is guar-  
anteed for 1M erase/write cycles and 40-year  
data retention.  
Block Diagram  
Pin Assignment  
1
6th May 99  
HT24LC01/02  
Pin Description  
P in Na m e  
A0~A2  
SDA  
I/O  
Descr ip t ion  
I
I/O  
I
Address inputs  
Serial data inputs/output  
Serial clock data input  
Write protect  
SCL  
WP  
I
VSS  
I
Negative power supply  
Positive power supply  
VCC  
Absolute Maximum Ratings  
Operating Temperature (Commercial) .................................................................................. 0°C to 70°C  
Storage Temperature ........................................................................................................ –50°C to 125°C  
Applied VCC Voltage with Respect to VSS ....................................................................... –0.3V to 6.0V  
Applied Voltage on any Pin with Respect to VSS  
–0.3V to VCC+0.3V  
...................................................................  
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maxi-  
mum Ratings” may cause substantial damage to the device. Functional operation of this device  
at other conditions beyond those listed in the specification is not implied and prolonged  
exposure to extreme conditions may affect device reliability.  
D.C. Characteristics  
Ta=0°C to 70°C  
Test Con d ition s  
Sym bol  
P a r a m eter  
Min . Typ .  
Ma x. Un it  
VCC  
Con d ition s  
VCC  
ICC1  
ICC2  
VIL  
Operating Voltage  
2.4  
5.5  
V
mA  
mA  
V
Operating Current  
5V Read at 100kHz  
5V Write at 100kHz  
2
Operating Current  
5
Input Low Voltage  
–1  
0.3VCC  
VIH  
Input High Voltage  
0.7VCC  
VCC+0.5  
V
VOL  
ILI  
Output Low Voltage  
Input Leakage Current  
Output Leakage Current  
Standby Current  
2.4V IOL=2.1mA  
5V VIN=0 or VCC  
5V VOUT=0 or VCC  
5V VIN=0 or VCC  
2.4V VIN=0 or VCC  
0.4  
1
V
µA  
µA  
µA  
µA  
pF  
pF  
ILO  
1
ISTB1  
ISTB2  
CIN  
5
Standby Current  
4
Input Capacitance (See Note)  
Output Capacitance (See Note)  
f=1MHz 25°C  
f=1MHz 25°C  
6
COUT  
8
Note: These parameters are periodically sampled but not 100% tested  
2
6th May 99  
HT24LC01/02  
A.C. Characteristics  
Ta=0°C to 70°C  
Sta n d a r d Mod e* VCC=5V±10%  
Sym bol  
P a r a m eter  
Rem a r k  
Un it  
Min .  
Ma x.  
100  
Min . Ma x.  
fSK  
Clock Frequency  
600  
1200  
400 kHz  
tHIGH  
tLOW  
tR  
Clock High Time  
4000  
4700  
ns  
ns  
ns  
ns  
Clock Low Time  
SDA and SCL Rise Time Note  
1000  
300  
300  
300  
tF  
SDA and SCL Fall Time  
Note  
After this period  
the first clock pulse  
is generated  
START Condition Hold  
Time  
tHD:STA  
4000  
4000  
600  
600  
ns  
ns  
Only relevant for  
repeated START  
condition  
START Condition  
Setup Time  
tSU:STA  
tHD:DAT Data Input Hold Time  
tSU:DAT Data Input Setup Time  
0
0
ns  
ns  
200  
100  
STOP Condition Setup  
tSU:STO  
Time  
4000  
600  
ns  
ns  
Output Valid from  
Clock  
tAA  
3500  
900  
Time in which the  
bus must be free  
before a new  
transmission can  
start  
tBUF  
Bus Free Time  
4700  
1200  
ns  
Input Filter Time  
Constant (SDA and SCL  
Pins)  
Noise suppression  
time  
tSP  
100  
5
50  
5
ns  
tWR  
Write Cycle Time  
ms  
Notes: These parameters are periodically sampled but not 100% tested  
* The standard mode means VCC=2.4V to 5.5V  
For relative timing, refer to timing diagrams  
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6th May 99  
HT24LC01/02  
Functional Description  
Serial clock (SCL)  
bus is not busy. During data transfer, the data  
line must remain stable whenever the clock  
line is high. Changes in data line while the  
clock line is high will be interpreted as a  
START or STOP condition.  
The SCL input is used for positive edge clock  
data into each EEPROM device and negative  
edge clock data out of each device.  
Serial data (SDA)  
Start condition  
The SDA pin is bidirectional for serial data  
transfer. The pin is open-drain driven and  
may be wired-OR with any number of other  
open-drain or open collector devices.  
A high-to-low transition of SDAwith SCL high  
is a start condition which must precede any  
other command (refer to Start and Stop Defi-  
nition Timing diagram).  
A0, A1, A2  
Stop condition  
The A2, A1 and A0 pins are device address  
in p u t s t h a t a r e h a r d wir ed for t h e  
HT24LC01/02. As many as eight 1K/2K de-  
vices may be addressed on a single bus system  
(the device addressing is discussed in detail  
under the Device Addressing section).  
A low-to-high transition of SDAwith SCL high  
is a stop condition. After a read sequence, the  
stop command will place the EEPROM in a  
standby power mode (refer to Start and Stop  
Definition Timing Diagram).  
Acknowledge  
Write protect (WP)  
All addresses and data words are serially  
transmitted to and from the EEPROM in 8-bit  
words. The EEPROM sends a zero to acknow-  
ledge that it has received each word. This  
happens during the ninth clock cycle.  
The HT24LC01/02 has a write protect pin  
that provides hardware data protection. The  
write protect pin allows normal read/write  
operations when connected to the VSS. When  
the write protect pin is connected to Vcc, the  
write protection feature is enabled and oper-  
ates as shown in the following table.  
P r otect Ar r a y  
HT24LC01 HT24LC02  
WP P in  
Sta tu s  
At VCC  
At VSS  
Full Array (1K) Full Array (2K)  
Normal Read/Write Operations  
Memory organization  
Device addressing  
HT24LC01, 1K Serial EEPROM  
The 1K and 2K EEPROM devices all require an  
8-bit device address word following a start con-  
dition to enable the chip for a read or write  
operation. The device address word consist of a  
mandatory one, zero sequence for the first four  
most significant bits (refer to the diagram show-  
ing the Device Address). This is common to all  
the EEPROM device.  
Internally organized with 128 8-bit words, the  
1K requires a 7-bit data word address for  
random word addressing.  
HT24LC02, 2K Serial EEPROM  
Internally organized with 256 8-bit words, the  
2K requires an 8-bit data word address for  
random word addressing.  
The next three bits are the A2, A1 and A0 device  
address bits for the 1K/2K EEPROM. These  
three bits must compare to their corresponding  
hard-wired input pins.  
Device operations  
Clock and data transition  
Data transfer may be initiated only when the  
4
6th May 99  
HT24LC01/02  
The 8th bit of device address is the read/write  
operation select bit. A read operation is initi-  
ated if this bit is high and a write operation is  
initiated if this bit is low.  
Page write  
The 1K/2K EEPROM is capable of an 8-byte  
page write.  
A page write is initiated the same as byte  
write, but the microcontroller does not send a  
stop condition after the first data word is  
clocked in. Instead, after the EEPROM ac-  
knowledges the receipt of the first data word,  
the microcontroller can transmit up to seven  
more data words. The EEPROM will respond  
with a zero after each data word received. The  
m icrocontr oller m ust termina te the pa ge  
write sequence with a stop condition.  
If the comparison of the device address succeed the  
EEPROM will output a zero at ACK bit. If not, the  
chip will return to a standby state.  
Write operations  
Byte write  
The data word address lower three (1K/2K)  
bits are internally incremented following the  
receipt of each data word. The higher data  
word address bits are not incremented, re-  
taining the memory page row location (refer  
to Page write timing).  
A write operation requires an 8-bit data word  
address following the device address word  
and acknowledgment. Upon receipt of this ad-  
dress, the EEPROM will again respond with a  
zero and then clock in the first 8-bit data  
word. After receiving the 8-bit data word, the  
EEPROM will output a zero and the address-  
ing device, such as a microcontroller, must  
terminate the write sequence with a stop con-  
dition. At this time the EEPROM enters an  
internally-timed write cycle to the non-vola-  
tile memory. All inputs are disabled during  
this write cycle and EEPROM will not re-  
spond until the write is completed (refer to  
Byte write timing).  
Acknowledge polling  
Since the device will not acknowledge during  
a write cycle, this can be used to determine  
when the cycle is complete (this feature can be  
used to maximize bus throughput). Once the  
stop condition for a write command has been  
issued from the master, the device initiates  
the internally timed write cycle. ACK polling  
can be initiated immediately. This involves  
the master sending a start condition followed  
by the control byte for a write command  
(R/W=0). If the device is still busy with the  
5
6th May 99  
HT24LC01/02  
write cycle, then no ACK will be returned. If  
the cycle is completed, then the device will  
return the ACK and the master can then pro-  
ceed with the next read or write command.  
Write protect  
The HT24LC01/02 can be used as a serial  
ROM when the WP pin is connected to VCC.  
Programming will be inhibited and the entire  
memory will be write-protected.  
Read operations  
Read operations are initiated the same way as  
write operations with the exception that the  
read/write select bit in the device address  
word is set to one. There are three read opera-  
tions: current address read, random address  
read and sequential read.  
Acknowledge polling flow  
Random read  
Current address read  
The internal data word address counter main-  
tains the last address accessed during the last  
read or write operation, incremented by one.  
This address stays valid between operations  
as long as the chip power is maintained. The  
address roll over during read from the last  
byte of the last memory page to the first byte  
of the first page. The address roll over during  
write from the last byte of the current page to  
the first byte of the same page. Once the de-  
vice address with the read/write select bit set  
to one is clocked in and acknowledged by the  
EEPROM, the current address data word is  
serially clocked out. The microcontroller does  
not respond with an input zero but generates  
a following stop condition (refer to Current  
read timing).  
A random read requires a dummy byte write  
sequence to load in the data word address  
which is then clocked in and acknowledged by  
the EEPROM. The microcontroller must then  
generate another start condition. The micro-  
controller now initiates a current address  
read by sending a device address with the  
read/write select bit high. The EEPROM ac-  
knowledges the device address and serially  
clocks out the data word. The microcontroller  
does not respond with a zero but does gener-  
ates a following stop condition (refer to Ran-  
dom read timing).  
6
6th May 99  
HT24LC01/02  
Sequential read  
Sequential reads are initiated by either a cur-  
rent address read or a random address read.  
After the microcontroller receives a data word,  
it responds with an acknowledgment. As long as  
the EEPROM receives an acknowledgment, it  
will continue to increment the data word ad-  
dress and serially clock out sequential data  
words. When the memory address limit is  
reached, the data word address will roll over  
and the sequential read continues. The se-  
quential read operation is terminated when  
the microcontroller does not respond with a  
zero but generates a following stop condition.  
Timing Diagrams  
Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end  
of the valid start condition of sequential command.  
7
6th May 99  
HT24LC01/02  
Holtek Sem icon d u ctor In c. (Hea d qu a r ter s)  
No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.  
Tel: 886-3-563-1999  
Fax: 886-3-563-1189  
Holtek Sem icon d u ctor In c. (Ta ip ei Office)  
5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.  
Tel: 886-2-2782-9635  
Fax: 886-2-2782-9636  
Fax: 886-2-2782-7128 (International sales hotline)  
Holtek Micr oelectr on ics En ter p r ises Ltd .  
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong  
Tel: 852-2-745-8288  
Fax: 852-2-742-8657  
Copyright © 1999 by HOLTEK SEMICONDUCTOR INC.  
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek  
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are  
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications  
will be suitable without further modification, nor recommends the use of its products for application that may present  
a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior  
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.  
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6th May 99  
配单直通车
HT24LC02产品参数
型号:HT24LC02
生命周期:Active
Reach Compliance Code:unknown
风险等级:5.65
Base Number Matches:1
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