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HT27LC010

CMOS 128K´8-Bit OTP EPROM

Features

·

Operating voltage: +3.3V

128K´8-bit organization

·

Programming voltage

Fast read access time: 90ns

-

V_PP=12.5V±0.2V

·

Fast programming algorithm

-

V_CC=6.0V±0.2V

·

Programming time 75ms typ.

·

High-reliability CMOS technology

·

Two line controls (OE and CE)

·

Latch-up immunity to 100mA from -1.0V to

_CC+1.0V

·

Standard product identification code

V

Commercial temperature ranges (0°C to +70°C)

32-pin DIP/SOP/TSOP/PLCC Package

·

CMOS and TTL compatible I/O

Low power consumption

-

Active: 15mA max.

-

Standby: 1mA typ.

General Description

The HT27LC010 chip family is a low-power, 1024K

(1,048,576) bit, +3.3V electrically one-time programma-

ble (OTP) read-only memories (EPROM). Organized

into 128K words with 8 bits per word, it features a fast

single address location programming, typically at 75ms

per byte. Any byte can be accessed in less than 90ns

with respect to Spec. This eliminates the need for WAIT

states in high-performance microprocessor systems.

The HT27LC010 has separate Output Enable (OE) and

Chip Enable (CE) controls which eliminate bus conten-

tion issues.

Block Diagram

R

o

w

X

-

D

e

c

o

d

e

r

C

e

l

A

r

a

y

A

d

r

e

s

V

G

V

C

P

C

o

l

u

m

n

N

D

Y

-

D

e

c

o

d

e

r

Y

-

G

a

t

i

n

g

A

d

r

e

s

P

C

E

C

E

&

O

E

&

S

A

C

K

T

&

D

Q

0

~

D

Q

7

O

P

G

M

&

T

E

S

T

O

u

t

p

u

t

B

u

f

e

r

C

o

n

t

r

o

l

L

o

g

i

c

P

G

M

Rev. 1.30

1

December 8, 2003

HT27LC010

Pin Assignment

V

P

1

2

3

2

1

V

P

C

G

C

A

1

6

M

A

1

5

2

7

6

3

4

5

6

3

2

0

9

8

7

N

A

C

1

8

4

3

2

1

2

1

0

9

8

7

6

5

4

3

2

1

0

9

8

7

A

1

O

A

C

D

G

D

A

E

1

0

A

9

8

2

3

4

5

6

A

2

9

A

7

6

5

4

3

2

1

0

5

E

Q

A

1

4

3

A

1

3

4

7

6

5

4

3

D

2

1

0

2

8

6

7

8

9

A

5

4

7

8

2

6

5

A

9

1

2

7

6

5

4

3

2

1

A

8

N

C

P

G

M

7

8

1

0

A

9

H

T

2

7

L

C

0

1

0

H

T

2

7

L

C

0

1

0

V

C

A

1

0

A

3

2

1

0

9

1

2

4

3

2

1

O

A

C

D

E

V

P

N

9

3

2

P

L

C

-

A

3

2

T

S

O

P

-

A

1

0

1

2

3

O

A

E

A

1

6

5

Q

1

0

1

2

1

A

1

2

1

2

E

Q

C

D

E

A

7

6

5

4

0

1

2

3

1

3

7

D

Q

0

Q

7

1

4

1

5

D

Q

0

1

3

4

2

1

0

9

D

Q

6

5

4

3

1

6

D

Q

2

1

5

6

1

8

7

G

N

D

H

T

2

7

L

C

0

1

0

3

2

D

I

P

-

A

/

S

O

P

-

A

Pin Description

Pin Name

VPP

I/O/C/P

Description

P

I

Program voltage supply

Address inputs

A0~A16

DQ0~DQ7

CE

I/O

C

Data inputs/outputs

Chip enable

OE

C

Output enable

PGM

C

Program strobe

No connection

NC

¾

VCC

Positive power supply

Absolute Maximum Rating

Operation Temperature Commercial..........................................................................................................0°C to +70°C

Storage Temperature.............................................................................................................................-65°C to 125 °C

Applied VCC Voltage with Respect to GND............................................................................................... -0.6V to 7.0V

Applied Voltage on Input Pin with Respect to GND.................................................................................... -0.6V to 7.0V

Applied Voltage on Output Pin with Respect to GND......................................................................... -0.6V to V_CC+0.5V

Applied Voltage on A9 Pin with Respect to GND ..................................................................................... -0.6V to 13.5V

Applied VPP Voltage with Respect to GND..............................................................................................-0.6V to 13.5V

Applied READ Voltage (Functionality is guaranteed between these limits) ..............................................+3.0V to +3.6V

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those

listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-

ity.

Rev. 1.30

2

December 8, 2003

HT27LC010

D.C. Characteristics

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_CC

Read Operation

V_OH

V_OL

V_IH

V_IL

I_LI

Output High Level

Output Low Level

Input High Level

3.3V

2.4

¾

V

I_OH=-0.4mA

¾

0.45

V_CC+0.5

0.8

I_OL=2.0mA

2.0

-0.3

-5

V

¾

Input Low Level

V

V_IN=0 to 3.6V

V_OUT=0 to 3.6V

CE=V_IL, f=5MHz,

Input Leakage Current

Output Leakage Current

5

mA

I_LO

10

-10

I_CC

VCC Active Current

3.3V

15

mA

¾

I

_OUT=0mA

I_SB1

I_SB2

I_PP

Standby Current (CMOS)

Standby Current (TTL)

3.3V

1.0

¾

10

0.6

100

CE=V_CC±0.3V

CE=V_IH

¾

mA

VPP Read/Standby Current

CE=OE=V_IL, V_PP=V_CC

¾

Programming Operation

V_OH

V_OL

V_IH

V_IL

I_LI

Output High Level

Output Low Level

Input High Level

6V

2.4

V

I_OH=-0.4mA

¾

I_OL=2.0mA

0.45

¾

0.7V_CC

V

_CC+0.5

0.8

V

¾

Input Low Level

V

-0.5

¾

V_IN=V_IL, V_IH

Input Load Current

A9 Product ID Voltage

VCC Supply Current

VPP Supply Current

5.0

mA

V

V_H

11.5

¾

12.5

40

¾

I_CC

I_PP

Capacitance

mA

CE=V_IL

10

¾

C_IN

V_IN=0V

Input Capacitance

Output Capacitance

VPP Capacitance

3.3V

8

12

25

pF

¾

C_OUT

C_VPP

V_OUT=0V

V_PP=0V

18

A.C. Characteristics

Ta=+25°C±5°C

Test Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_CC

Conditions

Read Operation

t_ACC

t_CE

CE=OE=V_IL

OE=V_IL

Address to Output Delay

3.3V

90

45

ns

¾

Chip Enable to Output Delay

Output Enable to Output Delay

t_OE

CE=V_IL

CE or OE High to Output Float, Whichever

Occurred First

t_DF

3.3V

40

ns

¾

Output Hold from Address, CE or OE,

Whichever Occurred First

t_OH

0

¾

Rev. 1.30

3

December 8, 2003

HT27LC010

Test Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_CC

Conditions

Programming Operation

t_AS

Address Setup Time

6V

2

¾

75

¾

ms

ns

ms

ns

ms

t_OES

t_DS

OE Setup Time

Data Setup Time

2

¾

t_AH

Address Hold Time

Data Hold Time

0

¾

t_DH

2

¾

t_DFP

t_VPS

t_PW

t_VCS

t_CES

t_OE

Output Enable to Output Float Delay

VPP Setup Time

0

130

¾

2

PGM Program Pulse Width

VCC Setup Time

30

2

105

¾

CE Setup Time

2

¾

Data Valid from OE

150

¾

2

t_PRT

VPP Pulse Rise Time During Programming 6V

Test Waveforms and Measurements

2

.

4

V

2

.

0

V

A

M

L

C

A

C

D

r

i

v

i

n

g

e

a

s

u

r

e

m

e

n

t

L

e

v

e

l

s

e

v

e

l

0

.

8

V

0

.

4

5

V

t_R, t_F< 20ns (10% to 90%)

Output Test Load

V

D

1

.

3

V

(

1

N

9

1

4

)

3

.

3

k

O

u

t

p

u

t

P

i

n

C

L

Note: C_L=100pF including jig capacitance.

Product Identification Code

Pins

Hex

Data

Code

A0

0

A1

1

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

Manufacturer

Device Type

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1C

01

7F

1

0

Continuation

1

0

Rev. 1.30

4

December 8, 2003

HT27LC010

Functional Description

Operation Mode

All the operation modes are shown in the table following.

Mode

CE

V_IL

OE

V_IL

V_IH

X

PGM

X (2)

X

A0

X

A1

X

A9

VPP

Output

Dout

Read

X

V_CC

V_PP

V_CC

Output Disable

Standby (TTL)

Standby (CMOS)

Program

V_IL

X

High Z

D_IN

V_IH

X

V

_CC± 0.3V

V_IL

V_IH

V_IL

X

V_IL

V_IH

X

Program Verify

Product Inhibit

Manufacturer Code (3)

Device Code (3)

V_IL

X

D_OUT

High Z

1C

V_IH

X

V_IL

X

V_IL

V_IH

V_H(1)

V_IL

X

01

Notes:

(1) ²V_H² 12.0V ± 0.5V

(2) ²X² Either V_IHor V_IL

(3) For Manufacturer Code and Device Code, A1=V_IH, When A1=V_IL, both codes will read 7F

Programming of the HT27LC010

program pulse applied to an HT27LC010 CE input with

Vpp=12.5±0.2V, PGM LOW, and OE HIGH will program

that HT27LC010. A high-level CE input inhibits the

HT27LC010 from being programmed.

When the HT27LC010 is delivered, the chip has all

1024K bits in the ²ONE², or HIGH state. ²ZEROs² are

loaded into the HT27LC010 through programming.

The programming mode is entered when 12.5±0.2V is

applied to the VPP pin, OE is at V_IH, and CE and PGM are

V_IL. For programming, the data to be programmed is ap-

plied with 8 bits in parallel to the data pins.

Program Verify Mode

Verification should be performed on the programmed

bits to determine whether they were correctly pro-

grammed. The verification should be performed with OE

and CE at V_IL, PGM at V_IH, and VPP at its programming

voltage.

The programming flowchart in Figure 3 shows the fast

interactive programming algorithm. The interactive al-

gorithm reduces programming time by using 30ms to

105ms programming pulses and giving each address

only as many pulses as is necessary in order to reliably

program the data. After each pulse is applied to a given

address, the data in that address is verified. If the data is

not verified, additional pulses are given until it is verified

or until the maximum number of pulses is reached while

sequencing through each address of the HT27LC010.

This process is repeated while sequencing through

each address of the HT27LC010. This part of the pro-

gramming algorithm is done at V_CC=6.0V to assure that

each EPROM bit is programmed to a sufficiently high

threshold voltage. This ensures that all bits have suffi-

cient margin. After the final address is completed, the

entire EPROM memory is read at V_CC=V_PP=3.3±0.3V to

verify the entire memory.

Auto Product Identification

The Auto Product Identification mode allows the reading

out of a binary code from an EPROM that will identify its

manufacturer and the type. This mode is intended for

programming to automatically match the device to be

programmed with its corresponding programming algo-

rithm. This mode is functional in the 25°C±5°C ambient

temperature range that is required when programming

the HT27LC010.

To activate this mode, the programming equipment must

force 12.0±0.5V on the address line A9 of the

HT27LC010. Two identifier bytes may then be se-

quenced from the device outputs by toggling address

line A0 from V_ILto V_IH, when A1=V_IH. All other address

lines must be held at V_IHduring Auto Product Identifica-

tion mode.

Program Inhibit Mode

Byte 0 (A0=V_IL) represents the manufacturer code, and

byte 1 (A0=V_IH), the device code. For HT27LC010,

these two identifier bytes are given in the Mode Select

Table. All identifiers for the manufacturer and device

Programming of multiple HT27LC010 in parallel with dif-

ferent data is also easily accomplished by using the Pro-

gram Inhibit Mode. Except for CE, all like inputs of the

parallel HT27LC010 may be common. A TTL low-level

Rev. 1.30

5

December 8, 2003

HT27LC010

codes will possess odd parity, with the MSB (DQ7) de-

fined as the parity bit. When A1=V_IL, the HT27LC010 will

read out the binary code of 7F, continuation code, to sig-

nify the unavailability of manufacturer ID codes.

Two-line Output Control Function

To accommodate multiple memory connections, a

two-linecontrolfunctionisprovidedtoallowfor:

·

Low memory power dissipation

Assurance that output bus contention will not occur

Read Mode

It is recommended that CE be decoded and used as the

primary device-selection function, while OE be made a

common connection to the READ line from the system

control bus. This assures that all deselected memory

devices are in their low-power standby mode and that

the output pins are only active when data is desired from

a particular memory device.

The HT27LC010 has two control functions, both of which

must be logically satisfied in order to obtain data at out-

puts.ChipEnable(CE)isthepowercontrolandshouldbe

used for device selection. Output Enable (OE) is the out-

put control and should be used to gate data to the output

pins, independent of device selection. Assuming that ad-

dressesarestable, addressaccesstime(t_ACC)isequalto

the delay from CE to output (t_CE). Data is available at the

outputs(t_OE)afterthefallingedgeofOE,assumingtheCE

has been LOW and addresses have been stable for at

System Considerations

During the switch between active and standby condi-

tions, transient current peaks are produced on the rising

and falling edges of Chip Enable. The magnitude of

these transient current peaks is dependent on the out-

put capacitance loading of the device. At a minimum, a

0.1mF ceramic capacitor (high frequency, low inherent

inductance) should be used on each device between

VCC and VPP to minimize transient effects. In addition,

to overcome the voltage drop caused by the inductive

effects of the printed circuit board traces on EPROM ar-

rays, a 4.7mF bulk electrolytic capacitor should be used

between VCC and VPP for each eight devices. The lo-

cation of the capacitor should be close to where the

power supply is connected to the array.

leastt_ACC-t_OE

.

Standby Mode

The HT27LC010 has CMOS standby mode which re-

duces the maximum VCC current to 10mA. It is placed in

CMOS standby when CE is at V_CC±0.3V. The

HT27LC010 also has a TTL-standby mode which re-

duces the maximum VCC current to 0.6mA. It is placed

in TTL-standby when CE is at V_IH. When in standby

mode, the outputs are in a high-impedance state, inde-

pendent of the OE input.

A

d

r

e

s

A

d

r

e

s

V

a

l

i

d

t

C E

C

E

t

D F

t

O

E

O

E

t

A C C

t

O H

O

u

t

p

u

t

V

a

l

i

d

O

u

t

p

u

t

H

I

G

H

Z

Figure 1. A.C. Waveforms for Read Operation

Rev. 1.30

6

December 8, 2003

HT27LC010

R

e

a

d

P

r

o

g

r

a

m

(

V

e

r

i

f

y

)

V

I

H

A

d

r

e

s

A

d

r

e

s

S

t

a

b

l

e

V

I

L

t

A

S

t

O

E

t

A H

V

I

H

D

a

t

a

O

u

t

D

a

t

a

I

n

D

a

t

a

V

a

l

i

d

V

I

L

t

D

S

t

D H

6

5

.

0

V

C

t

D F P

t

V C S

1

2

5

.

5

0

V

t

V P S

V

P

V

t

P R T

V

I

H

C

E

V

I

L

t

C E S

V

I

H

P

G

M

V

I

L

t

O E S

t

P W

V

I

H

O

E

V

I

L

Figure 2. Programming Waveforms

S

T

A

R

T

A

d

r

e

s

=

F

i

r

s

t

L

o

c

a

t

i

o

n

V

C

V

P

=

1

2

.

5

V

X

=

0

P

r

o

g

r

a

m

o n e 7 5 s P u l s e

I

n

t

e

r

a

c

t

i

v

e

S

e

c

t

i

o

n

I

n

c

r

e

m

e

n

t

X

Y

e

s

X

=

2

5

?

N

o

F

a

i

l

V

e

r

i

f

y

B

y

t

e

?

P

a

s

N

o

L

a

s

t

F

a

i

l

I

n

c

r

e

m

e

n

t

A

d

r

e

s

A

d

r

e

s

Y

e

s

V

C

=

V

P

= 3 . 3 V

V

e

r

i

f

y

S

e

c

t

i

o

n

F

a

i

l

V

e

r

i

f

y

a

l

D

e

v

i

c

e

F

a

i

l

e

d

B

y

t

e

s

?

P

a

s

D

e

v

i

c

e

P

a

s

e

d

N

m

Figure 3. Fast Programming Flowchart

Rev. 1.30

7

December 8, 2003

HT27LC010

Package Information

32-pin DIP (600mil) Outline Dimensions

A

3

2

1

7

B

1

6

H

C

D

I

a

E

F

G

Dimensions in mil

Nom.

Symbol

Min.

1635

535

145

125

16

Max.

1665

555

155

145

20

A

B

C

D

E

F

G

H

I

¾

50

70

¾

100

¾

595

635

0°

615

670

15°

¾

a

¾

Rev. 1.30

8

December 8, 2003

HT27LC010

32-pin SOP (450mil) Outline Dimensions

3

2

1

7

A

B

1

6

C

'

G

H

D

a

E

F

Dimensions in mil

Nom.

Symbol

Min.

543

440

14

¾

Max.

557

450

20

A

B

C

C¢

D

E

F

¾

50

¾

817

112

¾

100

¾

4

¾

G

H

a

32

4

38

12

0°

10°

Rev. 1.30

9

December 8, 2003

HT27LC010

32-pin PLCC Outline Dimensions

A

B

4

1

3

2

3

0

5

2

9

D

C

1

3

2

1

4

2

0

K

E

F

J

G

H

I

Dimensions in mil

Nom.

Symbol

Min.

485

445

585

545

105

¾

Max.

495

455

595

555

115

140

¾

A

B

C

D

E

F

G

H

I

¾

50

¾

15

¾

16

22

J

24

32

K

a

8

12

0°

10°

Rev. 1.30

10

December 8, 2003

HT27LC010

32-pin TSOP (8´20) Outline Dimensions

H

D

1

3

2

q

E

0

.

0

1

0

L

D

e

t

a

i

l

F

1

6

1

7

D

A

2

A

1

S

e

D

e

t

a

i

l

F

b

e

L

1

S

y

S

e

a

t

i

n

g

P

l

a

n

e

Dimensions in mm

Nom.

Symbol

Min.

¾

Max.

1.20

0.15

1.05

¾

A

A1

A2

b

¾

0.05

0.95

¾

0.22

¾

D

18.30

19.80

7.90

¾

18.50

20.20

8.10

¾

H_D

E

¾

e

0.50

0.60

0.80

¾

L

¾

L1

q

¾

0°

5°

Rev. 1.30

11

December 8, 2003

HT27LC010

Product Tape and Reel Specifications

Reel Dimensions

D

T

2

C

A

B

T

1

SOP 32W

Symbol

Description

Dimensions in mm

A

B

Reel Outer Diameter

Reel Inner Diameter

330±1.0

100±0.1

13.0+0.5

-0.2

C

D

Spindle Hole Diameter

Key Slit Width

2.0±0.5

32.8+0.3

-0.2

T1

T2

Space Between Flange

Reel Thickness

38.2+0.2

PLCC 32

Symbol

Description

Dimensions in mm

330±1.0

A

B

Reel Outer Diameter

Reel Inner Diameter

62±1.5

13.0+0.5

-0.2

C

D

Spindle Hole Diameter

Key Slit Width

2.0±0.5

24.8+0.3

-0.2

T1

T2

Space Between Flange

Reel Thickness

30.2±0.2

Rev. 1.30

12

December 8, 2003

HT27LC010

Carrier Tape Dimensions

P

0

P

1

t

D

E

F

B

0

W

C

K

1

D

1

P

K

2

A

0

SOP 32W

Symbol

Description

Dimensions in mm

32.0+0.3

-0.1

W

Carrier Tape Width

P

E

Cavity Pitch

16.0±0.1

1.75±0.1

14.2±0.1

1.55+0.1

2.0+0.25

4.0±0.1

2.0±0.1

14.7±0.1

20.9±0.1

3.0±0.1

3.4±0.1

0.35±0.05

25.5

Perforation Position

F

Cavity to Perforation (Width Direction)

Perforation Diameter

Cavity Hole Diameter

Perforation Pitch

D

D1

P0

P1

A0

B0

K1

K2

t

Cavity to Perforation (Length Direction)

Cavity Length

Cavity Width

Cavity Depth

Carrier Tape Thickness

Cover Tape Width

C

Rev. 1.30

13

December 8, 2003

HT27LC010

P

0

P

1

t

D

E

F

W

B

0

C

D

1

P

K

0

A

0

PLCC 32

Symbol

Description

Dimensions in mm

24.0±0.3

W

P

E

F

Carrier Tape Width

Cavity Pitch

18.0±0.1

Perforation Position

1.75±0.1

Cavity to Perforation (Width Direction)

Perforation Diameter

11.5±0.1

D

1.5+0.1

1.55+1.0

D1

Cavity Hole Diameter

-0.05

P0

P1

A0

B0

K0

t

Perforation Pitch

4.0±0.1

2.0±0.1

13.1±0.1

15.5±0.1

3.9±0.1

0.30±0.05

21.3

Cavity to Perforation (Length Direction)

Cavity Length

Cavity Width

Cavity Depth

Carrier Tape Thickness

Cover Tape Width

C

Rev. 1.30

14

December 8, 2003

HT27LC010

Holtek Semiconductor Inc. (Headquarters)

No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan

Tel: 886-3-563-1999

Fax: 886-3-563-1189

http://www.holtek.com.tw

Holtek Semiconductor Inc. (Taipei Sales Office)

4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan

Tel: 886-2-2655-7070

Fax: 886-2-2655-7373

Fax: 886-2-2655-7383 (International sales hotline)

Holtek Semiconductor Inc. (Shanghai Sales Office)

7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233

Tel: 021-6485-5560

Fax: 021-6485-0313

http://www.holtek.com.cn

Holtek Semiconductor Inc. (Shenzhen Sales Office)

43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031

Tel: 0755-8346-5589

Fax: 0755-8346-5590

ISDN: 0755-8346-5591

Holtek Semiconductor Inc. (Beijing Sales Office)

Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031

Tel: 010-6641-0030, 6641-7751, 6641-7752

Fax: 010-6641-0125

Holmate Semiconductor, Inc. (North America Sales Office)

46712 Fremont Blvd., Fremont, CA 94538

Tel: 510-252-9880

Fax: 510-252-9885

http://www.holmate.com

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-

sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used

solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable

without further modification, nor recommends the use of its products for application that may present a risk to human life

due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices

or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,

please visit our web site at http://www.holtek.com.tw.

Rev. 1.30

15

December 8, 2003

型号:	HT27LC010(32DIP)
生命周期：	Obsolete
IHS 制造商：	HOLTEK SEMICONDUCTOR INC
Reach Compliance Code：	unknown
风险等级：	5.84

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