HT9170B现货热卖使用介绍供应商报价哪里找芯片批发报价-中国IC网-芯三七

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产品型号HT9170B的概述

芯片HT9170B的概述 HT9170B是一款高性能的解码器/控制器芯片，广泛应用于遥控器、电子玩具与家用电器等领域。该芯片能够执行多种控制指令，通过对遥控信号的解码，实现对设备的控制功能。HT9170B芯片设计精密，具有低功耗、高抗干扰性和多种功能，成为了电子行业中常用的解决方案之一。 HT9170B的解码能力使其适用于多种编码方案，支持多种工作模式，能够在复杂环境中稳定运行。同时，HT9170B能够与多种其他外部组件协同工作，满足不同应用的需求，这种灵活性使其在市场上颇受欢迎。芯片HT9170B的详细参数 HT9170B的技术参数如下： - 电源电压（VDD）：2.5V 至 6.0V - 工作电流（Icc）：最大10mA（在5V时） - 工作频率： 32.768 kHz（外部振荡器） - 输入信号电平：TTL兼容，逻辑高电平范围通常为2.0V以上，逻辑低电平范围通常为0.8V以下...

产品型号HT9170B的Datasheet PDF文件预览

HT9170

DTMF Receiver

Features

Operating voltage: 2.5V~5.5V

Tristate data output for mC interface

3.58MHz crystal or ceramic resonator

1633Hz can be inhibited by the INH pin

HT9170B: 18-pin DIP package

Minimal external components

No external filter is required

Low standby current (on power down mode)

Excellent performance

HT9170D: 18-pin SOP package

General Description

The HT9170 series are Dual Tone Multi Fre-

quency (DTMF) receivers integrated with digi-

tal decoder and bandsplit filter functions. The

HT9170B and HT9170D types supply

power-down mode and inhibit mode operations.

All types of the HT9170 series use digital count-

ing techniques to detect and decode all the 16

DTMF tone pairs into a 4-bit code output.

Highly accurate switched capacitor filters are

employed to divide tone (DTMF) signals into

low and high group signals. A built-in dial tone

rejection circuit is provided to eliminate the

need for pre-filtering.

Selection Table

Function

Operating

OSC

Tristate

Voltage Frequency Data Output Down Inhibit

Power 1633Hz

DV DVB Package

Part No.

HT9170B 2.5V~5.5V

HT9170D 2.5V~5.5V

3.58MHz

18 DIP

18 SOP

December 20, 1999

HT9170

Block Diagram

d e

Pin Assignment

December 20, 1999

HT9170

Pin Description

Internal

Connection

Pin Name I/O

Description

OPERATIONAL

AMPLIFIER

Operational amplifier non-inverting input

Operational amplifier inverting input

Operational amplifier output terminal

Reference voltage output, normally V_DD/2

VREF

The system oscillator consists of an inverter, a bias resistor

and the necessary load capacitor on chip.

OSCILLATOR

A standard 3.579545MHz crystal connected to X1 and X2 ter-

minals implements the oscillator function.

Active high. This enables the device to go into power down

mode and inhibits the oscillator. This pin input is internally

pulled down.

CMOS IN

Pull-low

PWDN

Logic high. This inhibits the detection of tones representing

characters A, B, C and D. This pin input is internally pulled

down.

CMOS IN

Pull-low

INH

VSS

Negative power supply

CMOS IN

Pull-high

D0~D3 output enable, high active

Receiving data output terminals

OE=²H²: Output enable

OE=²L²: High impedance

CMOS OUT

Tristate

D0~D3

Data valid output

When the chip receives a valid tone (DTMF) signal, the DV

goes high; otherwise it remains low.

CMOS OUT

EST

Early steering output (see Functional Description)

Tone acquisition time and release time can be set through

connection with external resistor and capacitor.

RT/GT

VDD

I/O CMOS IN/OUT

Positive power supply, 2.5V~5.5V for normal operation

One-shot type data valid output, normal high, when the chip

receives a valid time (DTMF) signal, the DVB goes low for

10ms.

DVB

CMOS OUT

December 20, 1999

HT9170

Approximate internal connection circuits

M O

Absolute Maximum Ratings

Supply Voltage.................................-0.3V to 6V

Input Voltage.................V_SS-0.3V to V_DD+0.3V

Storage Temperature.................-50°C to 125°C

Operating Temperature ..............-20°C to 75°C

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi-

mum Ratings² may cause substantial damage to the device. Functional operation of this device

at other conditions beyond those listed in the specification is not implied and prolonged expo-

sure to extreme conditions may affect device reliability.

D.C. Characteristics

Ta=25°C

Test Conditions

Symbol

Parameter

Min. Typ. Max. Unit

V_DD

Conditions

V_DD

I_DD

I_STB

V_IL

V_IH

I_IL

Operating Voltage

Operating Current

Standby Current

2.5

4.0

3.0

5.5

5V PWDN=5V

1.0

²Low² Input Voltage

²High² Input Voltage

²Low² Input Current

²High² Input Current

_VP=V_VN=0V

_VP=V_VN=5V

_OE=0V

0.1

150

I_IH

R_OE

R_IN

Pull-high Resistance (OE) 5V

Input Impedance (VN, VP) 5V

100

December 20, 1999

HT9170

Test Conditions

Conditions

Symbol

Parameter

Source Current

(D0~D3, EST, DV)

Min. Typ. Max. Unit

V_DD

I_OH

V_OUT=4.5V

V_OUT=0.5V

-0.4

-0.8

Sink Current

(D0~D3, EST, DV)

I_OL

1.0

2.5

f_OSC

System Frequency

5V Crystal=3.5795MHz 3.5759 3.5795 3.5831 MHz

A.C. Characteristics

f_OSC=3.5795MHz, Ta=25°C

Test Conditions

Symbol

Parameter

Min. Typ. Max. Unit

V_DD

Conditions

DTMF Signal

-36

-29

-6

Input Signal Level

dBm

Twist Accept Limit (Positive)

Twist Accept Limit (Negative) 5V

Dial Tone Tolerance

Noise Tolerance

-12

-16

Third Tone Tolerance

Frequency Deviation

Acceptance

±3.5

±1.5

Frequency Deviation Rejection 5V

Power Up Time (t_PU

(See Figure 4.)

)

Gain Setting Amplifier

R_IN

Input Resistance

0.1

±25

I_IN

_SS<(V_VP,V_VN)<V_DD

Input Leakage Current

Offset Voltage

V_OS

P_SRR

C_MRR

A_VO

f_T

Power Supply Rejection

Common Mode Rejection

Open Loop Gain

100 Hz

-3V<V_IN<3V

Gain Band Width

1.5

4.5

MHz

V_PP

V_OUT

Output Voltage Swing

R_L>100kW

December 20, 1999

HT9170

Test Conditions

Symbol

Parameter

Min. Typ. Max. Unit

V_DD

Conditions

R_L

Load Resistance (GS)

Load Capacitance (GS)

Common Mode Range

100

3.0

C_L

V_CM

V_PP

5V No load

Steering Control

t_DP

t_DA

t_ACC

t_REJ

t_IA

Tone Present Detection Time

8.5

Tone Absent Detection Time

Acceptable Tone Duration

Rejected Tone Duration

Acceptable Inter-digit Pause

Rejected Inter-digit Pause

t_IR

Propagation Delay

(RT/GT to DO)

t_PDO

Propagation Delay

(RT/GT to DV)

t_PDV

t_DOV

t_DDO

t_EDO

Output Data Set Up (DO to DV)

Disable Delay (OE to DO)

Enable Delay (OE to DO)

4.5

300

Note: DO=D0~D3

. F 1

(

. F 1

)

Figure 1. Test circuit

December 20, 1999

HT9170

Functional Description

Overview

Steering control circuit

The HT9170 series tone decoders consist of

three band pass filters and two digital decode

circuits to convert a tone (DTMF) signal into

digital code output.

The steering control circuit is used for measur-

ing the effective signal duration and for protect-

ing against drop out of valid signals. It employs

the analog delay by external RC time-constant

controlled by EST.

An operational amplifier is built-in to adjust

the input signal (refer to Figure 2).

The timing is shown in Figure 3. The EST pin is

normally low and draws the RT/GT pin to keep

low through discharge of external RC. When a

valid tone input is detected, EST goes high to

charge RT/GT through RC.

When the voltage of RT/GT changes from 0 to

V_TRT(2.35V for 5V supply), the input signal is

effective, and the correct code will be created by

the code detector. After D0~D3 are completely

latched, DV output becomes high. When the

(

)

voltage of RT/GT falls down from VDD to V_TRT

(i.e.., when there is no input tone), DV output

becomes low, and D0~D3 keeps data until a

next valid tone input is produced.

By selecting adequate external RC value, the min-

imum acceptable input tone duration (t_ACC) and

the minimum acceptable inter-tone rejection (t_IR

)

can be set. External components (R, C) are chosen

by the formula (refer to Figure 5.):

_ACC=t_DP+t_GTP;

(

)

_IR=t_DA+t_GTA

;

Figure 2. Input operation for amplifier applica-

tion circuits

where t_ACC: Tone duration acceptable time

t_DP: EST output delay time (²L²®²H²)

The pre-filter is a band rejection filter which re-

duces the dialing tone from 350Hz to 400Hz.

_GTP: Tone present time

_IR: Inter-digit pause rejection time

The low group filter filters low group frequency

signal output whereas the high group filter fil-

ters high group frequency signal output.

t_DA: EST output delay time (²H²®²L²)

_GTA: Tone absent time

Each filter output is followed by a zero-crossing

detector with hysteresis. When each signal am-

plitude at the output exceeds the specified

level, it is transferred to full swing logic signal.

When input signals are recognized to be effec-

tive, DV becomes high, and the correct tone

code (DTMF) digit is transferred.

December 20, 1999

HT9170

Timing Diagrams

Figure 3. Steering timing

Figure 4. Power up timing

December 20, 1999

HT9170

(a) Fundamental circuit:

t_GTP= R ´ C ´ Ln (V_DD/ (V_{DD -}V_TRT))

t_GTA= R ´ C ´ Ln (V_DD/ V_TRT

t_GTP= R1 ´ C ´ Ln (V_DD/ (V_DD- V_TRT))

)

t_GTA= (R1 // R2) ´ C ´ Ln (V_DD/ V_TRT

)

(b) t_GTP< t_GTA

t_GTP= (R1 // R2) ´ C ´ Ln (V_{DD -}V_TRT))

t_GTA= R1 ´ C ´ Ln (V_DD/ V_TRT

)

Figure 5. Steering time adjustment circuits

DTMF dialing matrix

December 20, 1999

HT9170

DTMF data output table

Low Group (Hz) High Group (Hz) Digit

697

770

852

941

697

770

852

941

1209

1336

1477

1209

1336

1477

1209

1336

1477

1336

1209

1477

1633

ANY

Z: High impedance

Data output

The data outputs (D0~D3) are tristate outputs. When OE input becomes low, the data outputs

(D0~D3) are high impedance.

December 20, 1999

HT9170

Application Circuits

. F 1

(

)

(

)

December 20, 1999

HT9170

Holtek Semiconductor Inc. (Headquarters)

No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.

Tel: 886-3-563-1999

Fax: 886-3-563-1189

Holtek Semiconductor Inc. (Taipei Office)

5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.

Tel: 886-2-2782-9635

Fax: 886-2-2782-9636

Fax: 886-2-2782-7128 (International sales hotline)

Holtek Semiconductor (Hong Kong) Ltd.

RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong

Tel: 852-2-745-8288

Fax: 852-2-742-8657

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek

assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are

used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications

will be suitable without further modification, nor recommends the use of its products for application that may pres-

ent a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior

notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

December 20, 1999

HT9170B相关文章

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HT9170B产品参数

型号:	HT9170B
生命周期：	Active
Reach Compliance Code：	unknown
风险等级：	5.73
JESD-30 代码：	R-PDIP-T18
端子数量：	18
最高工作温度：	70 °C
最低工作温度：	-20 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装等效代码：	DIP18,.3
封装形状：	RECTANGULAR
封装形式：	IN-LINE
电源：	3/5 V
认证状态：	Not Qualified
子类别：	Telecom Signaling Circuits
最大压摆率：	7 mA
表面贴装：	NO
技术：	CMOS
电信集成电路类型：	DTMF SIGNALING CIRCUIT
温度等级：	COMMERCIAL
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
Base Number Matches：	1

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产品型号HT9170B的概述

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