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产品型号HUF76131SK8的Datasheet PDF文件预览

HUF76131SK8  
TM  
Data Sheet  
June 2000  
File Number 4396.5  
10A, 30V, 0.013 Ohm, N-Channel, Logic  
Level UltraFET Power MOSFET  
Features  
• Logic Level Gate Drive  
• 10A, 30V  
This N-Channel power MOSFET is  
®
manufactured using the innovative  
• Ultra Low On-Resistance, r  
= 0.013Ω  
UltraFET process. This advanced  
process technology achieves the  
DS(ON)  
®
Temperature Compensating PSPICE Model  
• Thermal Impedance SPICE Model  
• Peak Current vs Pulse Width Curve  
• UIS Rating Curve  
lowest possible on-resistance per silicon area, resulting in  
outstanding performance. This device is capable of  
withstanding high energy in the avalanche mode and the  
diode exhibits very low reverse recovery time and stored  
charge. It was designed for use in applications where power  
efficiency is important, such as switching regulators,  
switching converters, motor drivers, relay drivers, low-  
voltage bus switches, and power management in portable  
and battery-operated products.  
• Related Literature  
- TB334, “Guidelines for Soldering Surface Mount  
Components to PC Boards”  
Symbol  
Formerly developmental type TA76131.  
Ordering Information  
SOURCE(1)  
SOURCE(2)  
DRAIN(8)  
DRAIN(7)  
PART NUMBER  
PACKAGE  
BRAND  
76131SK8  
HUF76131SK8  
MS-012AA  
NOTE: When ordering, use the entire part number. Add the suffix T  
to obtain the variant in tape and reel, e.g., HUF76131SK8T.  
SOURCE(3)  
GATE(4)  
DRAIN(6)  
DRAIN(5)  
Packaging  
JEDEC MS-012AA  
BRANDING DASH  
5
1
2
3
4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.  
UltraFET® is a registered trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2000.  
1
HUF76131SK8  
o
Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified  
A
HUF76131SK8  
UNITS  
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V  
30  
30  
±16  
V
V
V
DSS  
DGR  
GS  
Drain to Gate Voltage (R  
= 20k) (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V  
GS  
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V  
Drain Current  
Continuous (Figure 2) (Notes 2, 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I  
10  
Figure 5  
Figure 6  
2.5  
0.02  
-55 to 150  
A
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I  
DM  
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E  
AS  
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P  
W
D
o
o
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
W/ C  
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T  
Maximum Temperature for Soldering  
C
J
STG  
o
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T  
300  
260  
C
L
o
Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
C
pkg  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
o
o
1. T = 25 C to 150 C.  
J
o
Electrical Specifications T = 25 C, Unless Otherwise Specified  
A
PARAMETER  
SYMBOL  
TEST CONDITIONS  
= 250µA, V = 0V (Figure 11)  
MIN  
TYP  
MAX UNITS  
Drain to Source Breakdown Voltage  
Gate to Source Threshold Voltage  
Zero Gate Voltage Drain Current  
BV  
I
30  
1
-
-
-
-
V
DSS  
D
GS  
= V , I = 250µA (Figure 10)  
V
V
V
V
V
-
V
GS(TH)  
GS  
DS  
DS  
GS  
DS D  
I
= 25V, V  
= 25V, V  
= ±16V  
= 0V  
-
1
µA  
µA  
nA  
DSS  
GS  
o
= 0V, T = 150 C  
-
-
250  
GS  
A
Gate to Source Leakage Current  
Drain to Source On Resistance  
I
-
-
±100  
GSS  
r
I
I
I
= 10A, V  
= 4.5V (Figures 9,14)  
-
0.017  
0.015  
0.011  
-
0.018  
DS(ON)  
D
GS  
GS  
GS  
= 10A, V  
= 10A, V  
= 5V  
-
0.017  
D
D
= 10V  
-
0.013  
Turn-On Time  
t
V
= 15V, I  
10A, R = 1.5, V  
GS  
= 5V,  
-
115  
ns  
ON  
DD  
D
L
R
= 6.8Ω  
GS  
Turn-On Delay Time  
Rise Time  
t
-
15  
61  
33  
36  
-
-
ns  
d(ON)  
(Figure 15)  
t
-
-
ns  
r
Turn-Off Delay Time  
Fall Time  
t
-
-
ns  
d(OFF)  
t
-
-
ns  
f
Turn-Off Time  
t
-
105  
ns  
OFF  
Total Gate Charge  
Q
V
V
V
= 0V to 10V V  
= 15V, I  
10A,  
= 1.0mA  
g(REF)  
-
39  
22  
1.53  
4.00  
9.50  
1605  
685  
115  
-
47  
nC  
nC  
nC  
nC  
nC  
pF  
pF  
pF  
C/W  
C/W  
C/W  
g(TOT)  
GS  
GS  
GS  
DD  
D
R = 1.5Ω, I  
(Figure 13)  
L
Gate Charge at 5V  
Q
= 0V to 5V  
= 0V to 1V  
-
26  
g(5)  
Threshold Gate Charge  
Gate to Source Gate Charge  
Gate to Drain “Miller” Charge  
Input Capacitance  
Q
-
1.85  
g(TH)  
Q
Q
-
-
gs  
gd  
-
-
C
V
= 25V, V  
GS  
= 0V, f = 1MHz  
-
-
ISS  
DS  
(Figure 12)  
Output Capacitance  
Reverse Transfer Capacitance  
Thermal Resistance Junction to Ambient  
C
C
-
-
OSS  
RSS  
-
-
2
o
o
o
R
Pad Area = 0.76 in (Note 2)  
-
50  
θJA  
2
Pad Area = 0.054 in (See TB377)  
-
-
143.4  
177.3  
2
Pad Area = 0.0115 in (See TB377)  
-
-
Source to Drain Diode Specifications  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
1.25  
1.1  
UNITS  
V
Source to Drain Diode Voltage  
V
I
I
I
I
= 10A  
-
-
-
-
-
-
-
-
SD  
SD  
SD  
SD  
SD  
= 2.3A  
V
Reverse Recovery Time  
t
= 2.3A, dI /dt = 100A/µs  
SD  
57  
ns  
rr  
Reverse Recovered Charge  
Q
= 2.3A, dI /dt = 100A/µs  
SD  
81  
nC  
RR  
NOTES:  
o
2
2. 50 C/W measured using FR-4 board with 0.76 in footprint at 10 seconds.  
o
2
3. 177.3 C/W measured using FR-4 board with 0.0115 in footprint at 1000 seconds.  
2
HUF76131SK8  
Typical Performance Curves  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
12  
10  
8
6
4
2
0
0
25  
50  
75  
100  
125  
150  
25  
50  
75  
100  
125  
150  
o
o
T , AMBIENT TEMPERATURE ( C)  
T , AMBIENT TEMPERATURE ( C)  
A
A
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT  
TEMPERATURE  
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs  
AMBIENT TEMPERATURE  
10  
DUTY CYCLE - DESCENDING ORDER  
0.5  
0.2  
0.1  
0.05  
1
0.02  
0.01  
P
DM  
0.1  
t
1
t
2
0.01  
NOTES:  
DUTY FACTOR: D = t /t  
1
2
PEAK T = P  
J
x Z  
x R  
+ T  
JA A  
SINGLE PULSE  
-3  
DM  
JA  
θ
θ
0.001  
10  
-5  
-4  
10  
-2  
-1  
10  
0
1
2
3
10  
10  
10  
10  
10  
10  
t, RECTANGULAR PULSE DURATION (s)  
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE  
1000  
500  
100  
T
T
= MAX RATED  
TRANSCONDUCTANCE  
MAY LIMIT CURRENT  
IN THIS REGION  
J
o
= 25 C  
A
V
= 5V  
100  
GS  
100µs  
1ms  
FOR TEMPERATURES  
OPERATION IN THIS  
AREA MAY BE  
o
10  
ABOVE 25 C DERATE PEAK  
10  
1
CURRENT AS FOLLOWS:  
LIMITED BY r  
DS(ON)  
10ms  
150 - T  
A
I = I  
25  
125  
o
T
= 25 C  
V
= 30V  
A
DSS(MAX)  
10  
, DRAIN TO SOURCE VOLTAGE (V)  
1
-5  
10  
-4  
10  
-3  
10  
-2  
-1  
0
1
1
100  
10  
10  
10  
10  
V
t, PULSE WIDTH (s)  
DS  
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA  
FIGURE 5. PEAK CURRENT CAPABILITY  
3
HUF76131SK8  
Typical Performance Curves (Continued)  
100  
50  
40  
30  
20  
10  
0
If R = 0  
t
= (L)(I )/(1.3*RATED BV  
- V )  
DD  
AV  
If R 0  
= (L/R)ln[(I *R)/(1.3*RATED BV  
AS  
DSS  
V
= 10V  
= 5V  
= 4.5V  
= 4V  
GS  
V
t
AV  
- V ) +1]  
DD  
GS  
AS DSS  
V
GS  
V
GS  
V
= 3.5V  
GS  
o
STARTING T = 25 C  
J
10  
o
V
= 3V  
STARTING T = 150 C  
J
GS  
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
o
T
= 25 C  
A
1
0.1  
1
10  
100  
0
0.5  
1.0  
1.5  
2.0  
2.5  
t
, TIME IN AVALANCHE (ms)  
AV  
V
, DRAIN TO SOURCE VOLTAGE (V)  
DS  
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.  
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING  
CAPABILITY  
FIGURE 7. SATURATION CHARACTERISTICS  
50  
1.75  
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
V
= 10V, I = 10A  
GS  
D
40  
30  
20  
1.5  
1.25  
1.0  
o
10  
0
150 C  
o
25 C  
o
V
= 15V  
DD  
-55 C  
0.75  
-80  
-40  
0
40  
80  
120  
160  
0
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
o
V
, GATE TO SOURCE VOLTAGE (V)  
T , JUNCTION TEMPERATURE ( C)  
GS  
J
FIGURE 8. TRANSFER CHARACTERISTICS  
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON  
RESISTANCE vs JUNCTION TEMPERATURE  
1.2  
1.0  
0.8  
0.6  
0.4  
1.2  
V
= V , I = 250µA  
I
= 250µA  
GS  
DS  
D
D
1.1  
1.0  
0.9  
0.8  
-80  
-40  
0
40  
80  
120  
160  
-80  
-40  
0
40  
80  
120  
160  
o
o
T , JUNCTION TEMPERATURE ( C)  
T , JUNCTION TEMPERATURE ( C)  
J
J
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs  
JUNCTION TEMPERATURE  
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN  
VOLTAGE vs JUNCTION TEMPERATURE  
4
HUF76131SK8  
Typical Performance Curves (Continued)  
10  
2500  
V
= 0V, f = 1MHz  
GS  
ISS  
C
C
C
= C  
+ C  
GS  
= C  
GD  
RSS  
OSS  
GD  
= C  
8
2000  
1500  
1000  
500  
0
+ C  
GD  
DS  
C
ISS  
6
4
2
0
WAVEFORMS IN  
DESCENDING ORDER:  
C
C
OSS  
I
I
I
I
= 20A  
= 10A  
= 5A  
D
D
D
D
RSS  
V
= 15V  
DD  
= 2.5A  
0
10  
20  
30  
40  
50  
0
5
10  
15  
20  
25  
30  
Q , GATE CHARGE (nC)  
g
V
, DRAIN TO SOURCE VOLTAGE (V)  
DS  
NOTE: Refer to Intersil Application Notes 7254 and 7260.  
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT  
GATE CURRENT  
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE  
80  
200  
V
= 15V, I = 10A, R = 1.5Ω  
D L  
DD  
I
= 10A  
= 20A  
D
60  
40  
20  
0
150  
100  
50  
I
= 5A  
t
t
t
D
r
I
D
d(OFF)  
f
I
= 2.5A  
D
t
d(ON)  
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
0
0
2
4
6
8
10  
0
10  
20  
30  
40  
50  
V
, GATE TO SOURCE VOLTAGE (V)  
R , GATE TO SOURCE RESISTANCE ()  
GS  
GS  
FIGURE 14. DRAIN TO SOURCE ON RESISTANCE vs GATE  
VOLTAGE AND DRAIN CURRENT  
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE  
Test Circuits and Waveforms  
V
DS  
BV  
DSS  
L
t
P
V
DS  
I
VARY t TO OBTAIN  
P
AS  
+
-
V
DD  
R
REQUIRED PEAK I  
G
AS  
V
DD  
V
GS  
DUT  
t
P
I
AS  
0V  
0
0.01Ω  
t
AV  
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT  
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS  
5
HUF76131SK8  
Test Circuits and Waveforms (Continued)  
V
t
t
DS  
ON  
OFF  
t
d(OFF)  
t
d(ON)  
t
t
f
R
L
r
V
DS  
90%  
90%  
+
V
GS  
V
DD  
10%  
10%  
0
-
DUT  
90%  
50%  
R
GS  
V
GS  
50%  
PULSE WIDTH  
10%  
V
GS  
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT  
FIGURE 19. SWITCHING TIME WAVEFORM  
V
DS  
V
Q
DD  
R
g(TOT)  
L
V
DS  
V
= 10V  
GS  
V
Q
GS  
g(5)  
+
-
V
DD  
V
= 5V  
V
GS  
GS  
DUT  
V
= 1V  
GS  
I
0
g(REF)  
Q
g(TH)  
I
g(REF)  
0
FIGURE 20. GATE CHARGE TEST CIRCUIT  
FIGURE 21. GATE CHARGE WAVEFORMS  
6
HUF76131SK8  
Thermal resistance values corresponding to other  
Thermal Resistance vs Mounting Pad Area  
component side copper areas can be obtained from Figure  
22 or by calculation using Equation 2. Area in Equation 2 is  
the top copper area including the gate and source pads.  
The maximum rated junction temperature T  
constrains  
JMAX  
the maximum allowable device power dissipation P  
in  
o
Dmax  
an application. The application ambient temperature T ( C)  
A
o
and thermal impedance Z  
o
( C/W) must be reviewed to  
R
= 79.3 21.8 × ln(Area)  
(EQ. 2)  
θJA  
θJA  
ensure that T  
( C) is never exceeded. Equation 1  
JMAX  
mathematically represents the relationship.  
250  
(T  
T )  
JMAX  
Z
A
(EQ. 1)  
P
= ---------------------------------------  
R
= 79.3 - 21.8*ln(AREA)  
DMAX  
θJA  
θJA  
200  
150  
100  
50  
Intersil provides thermal information to assist the designer’s  
preliminary application evaluation. Precise determination of  
o
2
177.3 C/W - 0.0115in  
o
2
P
is complex and influenced by many factors:  
143.4 C/W - 0.054in  
DMAX  
1. PC heat sink area and location (top and bottom), copper  
leads and mounting pad area.  
2. Air Flow, board orientation and type.  
3. Power pulse width and duty factor.  
Figure 22 addresses these points by depicting R  
θJA  
values  
vs. top copper (component side) heat sink area. The  
0.001  
0.01  
0.1  
2
1.0  
AREA, TOP COPPER AREA (in )  
measurements were performed in still air using a horizontally  
positioned FR-4 board with 1oz copper after 1000 seconds  
of steady state power.  
IGURE 22. THERMAL RESISTANCE vs MOUNTING PAD AREA  
Figure 22 also displays the two R  
θJA  
values listed in the  
Figure 22 provides the necessary information for steady  
state junction temperature or power dissipation calculations.  
Transient pulse applications are best studied using the  
Intersil device SPICE thermal model.  
Electrical Specifications table. The two points were chosen  
to graphically depict the compromise between copper board  
area, thermal resistance and ultimately power dissipation.  
7
HUF76131SK8  
PSPICE Electrical Model  
SUBCKT HUF76131 2 1 3 ;  
rev 12/31/97  
CA 12 8 2.22-9  
CB 15 14 2.13e-9  
CIN 6 8 1.52e-9  
LDRAIN  
DPLCAP  
10  
DRAIN  
2
5
RLDRAIN  
DBODY 7 5 DBODYMOD  
DBREAK 5 11 DBREAKMOD  
DPLCAP 10 5 DPLCAPMOD  
RSLC1  
51  
DBREAK  
+
RSLC2  
5
ESLC  
11  
51  
-
50  
EBREAK 11 7 17 18 37.4  
EDS 14 8 5 8 1  
EGS 13 8 6 8 1  
ESG 6 10 6 8 1  
EVTHRES 6 21 19 8 1  
EVTEMP 20 6 18 22 1  
+
-
17  
18  
-
DBODY  
RDRAIN  
6
ESG  
8
EBREAK  
EVTHRES  
+
16  
21  
+
-
19  
MWEAK  
LGATE  
EVTEMP  
+
8
RGATE  
GATE  
1
6
-
18  
22  
MMED  
IT 8 17 1  
9
20  
MSTRO  
8
RLGATE  
LDRAIN 2 5 1e-9  
LGATE 1 9 1.04e-9  
LSOURCE 3 7 1.29e-10  
LSOURCE  
CIN  
SOURCE  
3
7
RSOURCE  
MMED 16 6 8 8 MMEDMOD  
MSTRO 16 6 8 8 MSTROMOD  
MWEAK 16 21 8 8 MWEAKMOD  
RLSOURCE  
S1A  
S2A  
RBREAK  
12  
15  
13  
14  
13  
17  
18  
8
RBREAK 17 18 RBREAKMOD 1  
RDRAIN 50 16 RDRAINMOD 1.94e-3  
RGATE 9 20 2.20  
RLDRAIN 2 5 10  
RLGATE 1 9 10.4  
RLSOURCE 3 7 1.29  
RSLC1 5 51 RSLCMOD 1e-6  
RSLC2 5 50 1e3  
RSOURCE 8 7 RSOURCEMOD 8.75e-3  
RVTHRES 22 8 RVTHRESMOD 1  
RVTEMP 18 19 RVTEMPMOD 1  
RVTEMP  
19  
S1B  
S2B  
13  
CB  
CA  
IT  
14  
-
+
+
VBAT  
6
8
5
8
EGS  
EDS  
+
-
-
8
22  
RVTHRES  
S1A 6 12 13 8 S1AMOD  
S1B 13 12 13 8 S1BMOD  
S2A 6 15 14 13 S2AMOD  
S2B 13 15 14 13 S2BMOD  
VBAT 22 19 DC 1  
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*275),3))}  
.MODEL DBODYMOD D (IS = 2.25e-12 RS = 6.05e-3 IKF=16.00 TRS1 = 1.14e-4 TRS2 = 1.23e-6 CJO = 2.35e-9 TT = 2.71e-8 M = 0.44)  
.MODEL DBREAKMOD D (RS = 1.05e-1 TRS1 = 1.01e-4 TRS2 = 1.11e-7)  
.MODEL DPLCAPMOD D (CJO = 1.08e-9 IS = 1e-30 N = 10 M = 0.69)  
.MODEL MMEDMOD NMOS (VTO = 1.89 KP = 5.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.20)  
.MODEL MSTROMOD NMOS (VTO = 2.22 KP = 125.00 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)  
.MODEL MWEAKMOD NMOS (VTO = 1.62 KP = 0.10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 22.0 RS = 0.1)  
.MODEL RBREAKMOD RES (TC1 = 9.54e-4 TC2 = 1.07e-7)  
.MODEL RDRAINMOD RES (TC1 = 1.61e-2 TC2 = 5.17e-5)  
.MODEL RSLCMOD RES (TC1 = 1.03e-5 TC2 = 7.67e-7)  
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)  
.MODEL RVTHRESMOD RES (TC = -2.81e-3 TC2 = -8.75e-6)  
.MODEL RVTEMPMOD RES (TC1 = -6.68e-4 TC2 = 8.80e-7)  
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.80 VOFF= -1.50)  
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.50 VOFF= -5.80)  
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.50 VOFF= -0.00)  
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.00 VOFF= -0.50)  
.ENDS  
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global  
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.  
8
HUF76131SK8  
SPICE Thermal Model  
JUNCTION  
7
REV 20 Feb 98  
HUF76131  
RTHERM1  
CTHERM1  
CTHERM1 7 6 3.75e-4  
CTHERM2 6 5 3.05e-3  
CTHERM3 5 4 3.70e-2  
CTHERM4 4 3 2.52e-2  
CTHERM5 3 2 8.50e-2  
CTHERM6 2 1 7.95e-1  
6
RTHERM2  
RTHERM3  
RTHERM4  
RTHERM5  
RTHERM6  
CTHERM2  
CTHERM3  
CTHERM4  
CTHERM5  
CTHERM6  
RTHERM1 7 6 3.95e-2  
RTHERM2 6 5 2.50e-1  
RTHERM3 5 4 4.00e-1  
RTHERM4 4 3 6.35  
RTHERM5 3 2 2.02e1  
RTHERM6 2 1 4.80e1  
5
4
3
2
1
CASE  
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.  
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-  
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see web site www.intersil.com  
9
HUF76131SK8  
MS-012AA  
8 LEAD JEDEC MS-012AA SMALL OUTLINE PLASTIC PACKAGE  
E
E
A
INCHES  
MILLIMETERS  
A
1
1
SYMBOL  
MIN  
MAX  
MIN  
1.35  
0.10  
0.33  
0.19  
4.80  
5.80  
3.80  
MAX  
1.75  
0.25  
0.51  
0.25  
5.00  
6.20  
4.00  
NOTES  
A
0.0532  
0.004  
0.0688  
0.0098  
0.020  
-
-
e
A
1
b
0.013  
-
D
c
D
E
0.0075  
0.189  
0.0098  
0.1968  
0.244  
-
2
-
b
0.2284  
0.1497  
E
0.1574  
3
-
1
e
0.050 BSC  
1.27 BSC  
o
h x 45  
H
L
0.0099  
0.016  
0.0196  
0.050  
0.25  
0.40  
0.50  
1.27  
-
4
c
NOTES:  
1. All dimensions are within allowable dimensions of Rev. C of  
JEDEC MS-012AA outline dated 5-90.  
0.004 IN  
0.10 mm  
L
2. Dimension “D” does not include mold flash, protrusions or gate  
burrs. Mold flash, protrusions or gate burrs shall not exceed  
0.006 inches (0.15mm) per side.  
o
o
0 -8  
0.060  
1.52  
3. Dimension “E ” does not include inter-lead flash or protrusions.  
1
Inter-lead flash and protrusions shall not exceed 0.010 inches  
(0.25mm) per side.  
4. “L is the length of terminal for soldering.  
0.050  
1.27  
5. The chamfer on the body is optional. If it is not present, a visual index  
feature must be located within the crosshatched area.  
6. Controlling dimension: Millimeter.  
7. Revision 8 dated 5-99.  
0.024  
0.6  
0.155  
4.0  
0.275  
7.0  
4.0mm  
USER DIRECTION OF FEED  
1.5mm  
DIA. HOLE  
MINIMUM RECOMMENDED FOOTPRINT FOR  
SURFACE-MOUNTED APPLICATIONS  
2.0mm  
1.75mm  
C
L
MS-012AA  
12mm TAPE AND REEL  
12mm  
8.0mm  
40mm MIN.  
ACCESS HOLE  
18.4mm  
13mm  
COVER TAPE  
330mm  
50mm  
GENERAL INFORMATION  
1. 2500 PIECES PER REEL.  
12.4mm  
2. ORDER IN MULTIPLES OF FULL REELS ONLY.  
3. MEETS EIA-481 REVISION “A” SPECIFICATIONS.  
10  
配单直通车
HUF76131SK8产品参数
型号:HUF76131SK8
是否Rohs认证: 不符合
生命周期:Obsolete
包装说明:SMALL OUTLINE, R-PDSO-G8
Reach Compliance Code:unknown
ECCN代码:EAR99
HTS代码:8541.29.00.95
风险等级:5.21
其他特性:LOGIC LEVEL COMPATIBLE
配置:SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压:30 V
最大漏极电流 (Abs) (ID):10 A
最大漏极电流 (ID):10 A
最大漏源导通电阻:0.017 Ω
FET 技术:METAL-OXIDE SEMICONDUCTOR
JEDEC-95代码:MS-012AA
JESD-30 代码:R-PDSO-G8
JESD-609代码:e0
元件数量:1
端子数量:8
工作模式:ENHANCEMENT MODE
最高工作温度:150 °C
封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED
极性/信道类型:N-CHANNEL
最大功率耗散 (Abs):2.5 W
认证状态:Not Qualified
子类别:FET General Purpose Power
表面贴装:YES
端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
晶体管应用:SWITCHING
晶体管元件材料:SILICON
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