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产品型号HY57V561620CT的Datasheet PDF文件预览

HY57V561620C(L)T

4 Banks x 4M x 16Bit Synchronous DRAM

DESCRIPTION

The HY57V561620C is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require

large memory density and high bandwidth. HY57V561620C is organized as 4banks of 4,194,304x16.

HY57V561620C is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-

nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by

a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or

write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or

write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3±0.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

8192 refresh cycles / 64ms

JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin

pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

•

All inputs and outputs referenced to positive edge of sys-

tem clock

•

Data mask function by UDQM, LDQM

Internal four banks operation

•

Programmable CAS Latency ; 2, 3 Clocks

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY57V561620CT-6

HY57V561620CT-K

HY57V561620CT-H

HY57V561620CT-8

HY57V561620CT-P

HY57V561620CT-S

HY57V561620CLT-6

HY57V561620CLT-K

HY57V561620CLT-H

HY57V561620CLT-8

HY57V561620CLT-P

HY57V561620CLT-S

166MHz

133MHz

125MHz

100MHz

166MHz

133MHz

125MHz

100MHz

Normal

4Banks x 4Mbits x16

LVTTL

400mil 54pin TSOP II

Low power

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev. 0.3/Dec. 01

HY57V561620C(L)T

PIN CONFIGURATION

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

VSS

DQ5 10

DQ6 11

VSSQ 12

DQ7 13

VDD 14

LDQM 15

/WE 16

/CAS 17

/RAS 18

/CS 19

BA0 20

BA1 21

A10/AP 22

A0 23

54pin TSOP II

400mil x 875mil

0.8mm pin pitch

UDQM

CLK

CKE

A12

A11

A1 24

A2 25

A3 26

VDD 27

VSS

PIN DESCRIPTION

PIN NAME

DESCRIPTION

The system clock input. All other inputs are registered to the SDRAM on the

rising edge of CLK

CLK

Clock

Controls internal clock signal and when deactivated, the SDRAM will be one

of the states among power down, suspend or self refresh

CKE

Clock Enable

Chip Select

Enables or disables all inputs except CLK, CKE, UDQM and LDQM

Selects bank to be activated during RAS activity

Selects bank to be read/written during CAS activity

BA0, BA1

A0 ~ A12

Bank Address

Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8

Auto-precharge flag : A10

Address

Row Address Strobe,

Column Address Strobe,

Write Enable

RAS, CAS and WE define the operation

Refer function truth table for details

RAS, CAS, WE

UDQM, LDQM

DQ0 ~ DQ15

VDD/VSS

Data Input/Output Mask

Data Input/Output

Controls output buffers in read mode and masks input data in write mode

Multiplexed data input / output pin

Power Supply/Ground

Data Output Power/Ground

No Connection

Power supply for internal circuits and input buffers

Power supply for output buffers

VDDQ/VSSQ

No connection

Rev. 0.3/Dec. 01

HY57V561620C(L)T

FUNCTIONAL BLOCK DIAGRAM

4Mbit x 4banks x 16 I/O Synchronous DRAM

Self Refresh Logic

& Timer

Internal Row

Counter

4Mx16 Bank 3

4Mx16 Bank 2

CLK

Row

Pre

Row Active

CKE

Decoders

4Mx16 Bank 1

4Mx16 Bank 0

DQ0

DQ1

RAS

CAS

Memory

Cell

Array

Column

Active

Column

Pre

UDQM

LDQM

Decoders

DQ14

DQ15

Y decoders

Column Add

Counter

Bank Select

Address

Burst

Counter

A12

BA0

BA1

CAS Latency

Pipe Line Control

Mode Registers

Data Out Control

Rev. 0.3/Dec. 01

HY57V561620C(L)T

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Rating

Unit

Ambient Temperature

0 ~ 70

-55 ~ 125

-1.0 ~ 4.6

°C

Storage Temperature

TSTG

°C

Voltage on Any Pin relative to VSS

Voltage on VDD relative to VSS

Short Circuit Output Current

Power Dissipation

VIN, VOUT

VDD, VDDQ

IOS

Soldering Temperature Time

TSOLDER

260 10

°C Sec

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITION ^{(TA=0 to 70°C)}

Parameter

Symbol

Min

Typ.

Max

Unit

Note

Power Supply Voltage

Input High Voltage

Input Low Voltage

VDD, VDDQ

VIH

3.0

2.0

3.3

3.0

3.6

VDDQ + 0.3

0.8

1,2

1,3

VIL

- 0.3

Note :

1.All voltages are referenced to VSS = 0V

2.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration

3.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration

AC OPERATING CONDITION ^{(TA=0 to 70°C, V}DD=3.3 ± 0.3V, VSS=0V)

Parameter

Symbol

Value

Unit

Note

AC Input High / Low Level Voltage

VIH / VIL

Vtrip

2.4/0.4

1.4

Input Timing Measurement Reference Level Voltage

Input Rise / Fall Time

tR / tF

Voutref

Output Timing Measurement Reference Level

Output Load Capacitance for Access Time Measurement

1.4

Note :

1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)

For details, refer to AC/DC output circuit

Rev. 0.3/Dec. 01

HY57V561620C(L)T

CAPACITANCE ^{(TA=25°C, f=1MHz)}

-6/K/H

Max

-8/P/S

Unit

Parameter

Symbol

Min

Max

Input capacitance

CLK

CI1

CI2

2.5

3.5

3.8

2.5

4.0

5.0

A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS,

WE, UDQM, LDQM

Data input / output capacitance

DQ0 ~ DQ15

CI/O

4.0

6.5

4.0

6.5

OUTPUT LOAD CIRCUIT

Vtt=1.4V

RT=250 Ω

Output

50pF

DC Output Load Circuit

AC Output Load Circuit

DC CHARACTERISTICS I ^{(TA=0 to 70°C, V}DD=3.3±0.3V)

Parameter

Symbol

Min.

Max

Unit

Note

Input Leakage Current

Output Leakage Current

Output High Voltage

Output Low Voltage

ILI

-1

2.4

ILO

VOH

VOL

IOH = -4mA

IOL = +4mA

0.4

Note :

1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V

2.DOUT is disabled, VOUT=0 to 3.6V

Rev. 0.3/Dec. 01

HY57V561620C(L)T

DC CHARACTERISTICS II ^{(TA=0 to 70°C, V}DD=3.3±0.3V, VSS=0V)

Speed

Parameter

Symbol

Test Condition

Unit Note

-6

-K

-H

-8

-P

-S

Burst length=1, One bank active

Operating Current

IDD1

130

110

100

tRC ≥ tRC(min), IOL=0mA

IDD2P

CKE ≤ VIL(max), tCK = 15ns

CKE ≤ VIL(max), tCK = ∞

Precharge Standby Current

in Power Down Mode

IDD2PS

CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns

Input signals are changed one time during

30ns. All other pins ≥ VDD-0.2V or ≤ 0.2V

IDD2N

Precharge Standby Current

in Non Power Down Mode

CKE ≥ VIH(min), tCK = ∞

Input signals are stable.

IDD2NS

IDD3P

CKE ≤ VIL(max), tCK = 15ns

Active Standby Current

in Power Down Mode

IDD3PS CKE ≤ VIL(max), tCK = ∞

CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns

IDD3N

Input signals are changed one time during

Active Standby Current

30ns. All other pins ≥ VDD-0.2V or ≤ 0.2V

in Non Power Down Mode

CKE ≥ VIH(min), tCK = ∞

Input signals are stable.

IDD3NS

Burst Mode Operating

Current

tCK ≥ tCK(min), IOL=0mA

IDD4

IDD5

150

220

130

220

130

220

130

200

110

200

110

200

All banks active

Auto Refresh Current

tRRC ≥ tRRC(min), All banks active

Self Refresh Current

IDD6

CKE ≤ 0.2V

1.5

Note :

1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open

2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II

3.HY57V561620CT-6/K/H/8/P/S

4.HY57V561620CLT-6/K/H/8/P/S

Rev. 0.3/Dec. 01

HY57V561620C(L)T

AC CHARACTERISTICS I ^{(AC operating conditions unless otherwise noted)}

-6

-K

-H

-8

-P

-S

Parameter

Symbol

Unit Note

Min

Max

Min

7.5

2.5

Max

Min

7.5

2.5

Max

Min

Max

Min

Max

Min

Max

CAS Latency = 3 tCK3

CAS Latency = 2 tCK2

System Clock

Cycle Time

1000

7.5

2.5

Clock High Pulse Width

Clock Low Pulse Width

tCHW

tCLW

CAS Latency = 3 tAC3

CAS Latency = 2 tAC2

tOH

5.4

Access Time

From Clock

5.4

Data-Out Hold Time

2.7

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

2.7

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

2.7

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

Data-Input Setup Time

Data-Input Hold Time

Address Setup Time

Address Hold Time

tDS

tDH

tAS

tAH

CKE Setup Time

tCKS

tCKH

tCS

CKE Hold Time

Command Setup Time

Command Hold Time

CLK to Data Output in Low-Z Time

tCH

tOLZ

CAS Latency = 3 tOHZ3

CAS Latency = 2 tOHZ2

2.7

5.4

2.7

5.4

2.7

5.4

CLK to Data

Output in High-Z

Time

Note :

1.Assume tR / tF (input rise and fall time ) is 1ns

2.Access times to be measured with input signals of 1v/ns edge rate

Rev. 0.3/Dec. 01

HY57V561620C(L)T

AC CHARACTERISTICS II

-6

-K

-H

-8

-P

-S

Parameter

Symbol

Unit Note

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Operation

Auto Refresh

tRC

RAS Cycle Time

tRRC

tRCD

tRAS

tRP

RAS to CAS Delay

RAS Active Time

100K

RAS Precharge Time

RAS to RAS Bank Active Delay

CAS to CAS Delay

tRRD

tCCD

tWTL

tWR

CLK

Write Command to Data-In Delay

Write Recovery Time

Data-In to Active Command

DQM to Data-Out Hi-Z

DQM to Data-In Mask

tDAL

tDQZ

tDQM

tMRD

MRS to New Command

CAS Latency = 3 tPROZ3

CAS Latency = 2 tPROZ2

Precharge to Data

Output Hi-Z

Power Down Exit Time

Self Refresh Exit Time

Refresh Time

tPDE

tSRE

tREF

Note :

1. A new command can be given tRRC after self refresh exit

Rev. 0.3/Dec. 01

HY57V561620C(L)T

IBIS SPECIFICATION

IOH Characteristics (Pull-up)

66MHz and 100MHz Pull-up

100MHz

(Min)

100MHz

(Max)

66MHz

(Min)

Voltage

0.5

1.5

2.5

3.5

(V)

3.45

3.3

3.0

2.6

2.4

2.0

1.8

1.65

1.5

1.4

1.0

I(mA)

-2.4

I(mA)

-100

-200

-300

-400

-500

-600

-27.3

-74.1

-0.7

-7.5

-21.1

-34.1

-58.7

-67.3

-73

-129.2

-153.3

-197

-13.3

-27.5

-35.5

-41.1

-47.9

-52.4

-72.5

-93

-226.2

-248

Voltage (V)

-77.9

-80.8

-88.6

-93

-269.7

-284.3

-344.5

-502.4

^OHMin (100MHz)

^OHMin (66MHz)

^OHMax (66 /100MHz)

IOL Characteristics (Pull-down)

66MHz and 100MHz Pull-down

100MHz

(Min)

100MHz

(Max)

66MHz

(Min)

Voltage

250

200

150

100

(V)

I(mA)

0.4

27.5

41.8

51.6

58.0

70.7

72.9

75.4

77.0

77.6

80.3

81.4

70.2

17.7

26.9

33.3

37.6

46.6

48.0

49.5

50.7

51.5

54.2

54.9

0.65

0.85

1.0

107.5

133.8

151.2

187.7

194.4

202.5

208.6

212.0

219.6

222.6

1.4

1.5

1.65

1.8

0.5

1.5

Voltage (V)

^OLMin (100MHz)

^OLMin (66MHz)

^OLMax (100MHz)

2.5

3.5

1.95

3.0

3.45

Rev. 0.3/Dec. 01

HY57V561620C(L)T

DEVICE OPERATING OPTION TABLE

HY57V561620C(L)T-6

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

166MHz(6ns)

143MHz(7ns)

133MHz(7.5ns)

3CLKs

2CLKs

3CLKs

7CLKs

6CLKs

10CLKs

9CLKs

3CLKs

5.4ns

2.7ns

HY57V561620C(L)T-K

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

133MHz(7.5ns)

125MHz(8ns)

100MHz(10ns)

2CLKs

3CLKs

2CLKs

3CLKs

2CLKs

6CLKs

5CLKs

8CLKs

9CLKs

7CLKs

2CLKs

3CLKs

2CLKs

5.4ns

6ns

2.7ns

3ns

HY57V561620C(L)T-H

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

133MHz(7.5ns)

125MHz(8ns)

100MHz(10ns)

3CLKs

2CLKs

3CLKs

2CLKs

6CLKs

5CLKs

9CLKs

7CLKs

3CLKs

2CLKs

5.4ns

6ns

2.7ns

3ns

HY57V561620C(L)T-8

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

125MHz(8ns)

100MHz(10ns)

83MHz(12ns)

3CLKs

2CLKs

3CLKs

2CLKs

6CLKs

5CLKs

4CLKs

9CLKs

7CLKs

6CLKs

3CLKs

2CLKs

6ns

3ns

HY57V561620C(L)T-P

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

100MHz(10ns)

83MHz(12ns)

66MHz(15ns)

2CLKs

5CLKs

4CLKs

7CLKs

6CLKs

2CLKs

6ns

3ns

HY57V561620C(L)T-S

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

100MHz(10ns)

83MHz(12ns)

66MHz(15ns)

3CLKs

2CLKs

5CLKs

4CLKs

7CLKs

6CLKs

2CLKs

6ns

3ns

Rev. 0.3/Dec. 01

HY57V561620C(L)T

COMMAND TRUTH TABLE

A10/

Command

CKEn-1

CKEn

RAS

CAS

DQM

ADDR

Note

Mode Register Set

OP code

No Operation

Bank Active

Read

Read with Autoprecharge

Write

Write with Autoprecharge

Precharge All Banks

Precharge selected Bank

Burst Stop

DQM

Auto Refresh

Burst-Read-Single-

WRITE

A9 Pin High

(Other Pins OP code)

Entry

Self Refresh

Exit

Entry

Precharge

power down

Exit

Entry

Clock

Suspend

Exit

Note :

1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high

2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,

Opcode = Operand Code, NOP = No Operation

Rev. 0.3/Dec. 01

HY57V561620C(L)T

PACKAGE INFORMATION

400mil 54pin Thin Small Outline Package

UNIT : mm(inch)

11.938(0.4700)

11.735(0.4620)

22.327(0.8790)

22.149(0.8720)

10.262(0.4040)

10.058(0.3960)

0.150(0.0059)

0.050(0.0020)

1.194(0.0470)

0.991(0.0390)

5deg

0deg

0.210(0.0083)

0.120(0.0047)

0.597(0.0235)

0.406(0.0160)

0.400(0.016)

0.80(0.0315)BSC

0.300(0.012)

Rev. 0.3/Dec. 01

HY57V561620CT相关文章

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HY57V561620CT-6产品参数

型号:	HY57V561620CT-6
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	TSOP2
包装说明：	TSOP2, TSOP54,.46,32
针数：	54
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.32.00.24
风险等级：	5.79
访问模式：	FOUR BANK PAGE BURST
最长访问时间：	5.4 ns
其他特性：	AUTO/SELF REFRESH
最大时钟频率 (fCLK)：	166 MHz
I/O 类型：	COMMON
交错的突发长度：	1,2,4,8
JESD-30 代码：	R-PDSO-G54
JESD-609代码：	e0
长度：	22.238 mm
内存密度：	268435456 bit
内存集成电路类型：	SYNCHRONOUS DRAM
内存宽度：	16
功能数量：	1
端口数量：	1
端子数量：	54
字数：	16777216 words
字数代码：	16000000
工作模式：	SYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	16MX16
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP2
封装等效代码：	TSOP54,.46,32
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V
认证状态：	Not Qualified
刷新周期：	8192
座面最大高度：	1.194 mm
自我刷新：	YES
连续突发长度：	1,2,4,8,FP
最大待机电流：	0.001 A
子类别：	DRAMs
最大压摆率：	0.22 mA
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.8 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10.16 mm
Base Number Matches：	1

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