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    产品型号HY57V641620ELT-5的Datasheet PDF文件预览

    64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O  
    Document Title  
    4Bank x 1M x 16bits Synchronous DRAM  
    Revision History  
    Revision No.  
    History  
    Draft Date  
    Remark  
    First Version Release  
    1.0  
    Nov. 2004  
    1. Changed tOH: 2.0 --> 2.5  
    [tCK = 7 & 7.5 (CL3) Product]  
    1. Changed Input High/Low Voltage (Page 08)  
    2. Changed DC characteristics (Page 09)  
    - IDD2NS: 18mA -> 15mA  
    - IDD5:210 / 195 / 180mA -> 170 / 160 / 150mA  
    [Speed 200 / 166 / 143 / 133MHz]  
    3. Changed Clock High / Low pulse width Time (Page 11)  
    4. Changed tAC Time (Page11)  
    1.1  
    1.2  
    Dec. 2004  
    Dec. 2004  
    5. Changed tRRD Time (Page12)  
    1. Corrected Revision No.: 2.0 -> 1.1  
    2. Deleted Remark at Revision History  
    3. Corrected AC OPERATING CONDITION  
    - CL 50pF -> 30pF  
    4. Changed DC OPERATING CONDITION  
    - VIH MAX VDDQ+2.0 -> VDDQ+0.3 and Typ 3.3 -> 3.0  
    - VIL MIN VSSQ-2.0 -> -0.3  
    1.3  
    1.4  
    1.5  
    1. Modified note for Super Low Power in ORDERING INFORMATION  
    1. Corrected PIN ASSIGNMENT A12 to NC  
    Jan. 2005  
    Jan. 2005  
    Feb. 2005  
    1. Corrected comments for overshoot and undershoot  
    This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for  
    use of circuits described. No patent licenses are implied.  
    Rev. 1.5 / Feb. 2005  
    1
    Synchronous DRAM Memory 64Mbit (4Mx16bit)  
    HY57V641620E(L/S)T(P) Series  
    DESCRIPTION  
    The Hynix HY57V641620E(L/S)T(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory  
    applications which require wide data I/O and high bandwidth. HY57V641620E(L/S)T(P) is organized as 4banks of  
    1,048,576x16.  
    HY57V641620E(L/S)T(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs  
    and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve  
    very high bandwidth. All input and output voltage levels are compatible with LVTTL.  
    Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write  
    cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-  
    quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or  
    can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-  
    stricted by a '2N' rule)  
    FEATURES  
    •
    •
    •
    •
    Voltage: VDD, VDDQ 3.3V supply voltage  
    All device pins are compatible with LVTTL interface  
    54 Pin TSOPII (Lead or Lead Free Package)  
    •
    •
    •
    Auto refresh and self refresh  
    4096 Refresh cycles / 64ms  
    Programmable Burst Length and Burst Type  
    - 1, 2, 4, 8 or full page for Sequential Burst  
    - 1, 2, 4 or 8 for Interleave Burst  
    Programmable CAS Latency; 2, 3 Clocks  
    Burst Read Single Write operation  
    All inputs and outputs referenced to positive edge of  
    system clock  
    •
    •
    Data mask function by UDQM, LDQM  
    Internal four banks operation  
    •
    •
    ORDERING INFORMATION  
    Part No.  
    Clock Frequency  
    Organization  
    Interface  
    Package  
    HY57V641620E(L/S)T(P)-5  
    HY57V641620E(L/S)T(P)-6  
    HY57V641620E(L/S)T(P)-7  
    HY57V641620E(L/S)T(P)-H  
    200MHz  
    166MHz  
    143MHz  
    133MHz  
    4Banks x 1Mbits x16  
    LVTTL  
    54 Pin TSOPII  
    Note: 1. HY57V641620ET Series: Normal power, Leaded.  
    2. HY57V641620ELT Series: Low power, Leaded.  
    3. HY57V641620EST Series: Super Low power, Leaded.  
    4. HY57V641620ETP Series: Normal power, Lead Free.  
    5. HY57V641620ELTP Series: Low power, Lead Free.  
    6. HY57V641620ESTP Series: Super Low Power, Lead Free  
    Rev. 1.5 / Feb. 2005  
    2
    Synchronous DRAM Memory 64Mbit (4Mx16bit)  
    HY57V641620E(L/S)T(P) Series  
    PIN ASSIGNMENTS  
    1
    54  
    53  
    52  
    51  
    50  
    49  
    48  
    47  
    46  
    45  
    44  
    43  
    42  
    41  
    40  
    39  
    38  
    37  
    36  
    35  
    34  
    33  
    32  
    31  
    30  
    29  
    28  
    VDD  
    DQ0  
    VDDQ  
    DQ1  
    DQ2  
    VSSQ  
    DQ3  
    DQ4  
    VDDQ  
    DQ5  
    DQ6  
    VSSQ  
    DQ7  
    VDD  
    LDQM  
    /WE  
    /CAS  
    /RAS  
    /CS  
    VSS  
    2
    DQ15  
    VSSQ  
    DQ14  
    DQ13  
    VDDQ  
    DQ12  
    DQ11  
    VSSQ  
    DQ10  
    DQ9  
    VDDQ  
    DQ8  
    VSS  
    3
    4
    5
    6
    7
    8
    9
    10  
    11  
    12  
    13  
    14  
    15  
    16  
    17  
    18  
    19  
    20  
    21  
    22  
    23  
    24  
    25  
    26  
    27  
    54 Pin TSOPII  
    400mil x 875mil  
    0.8mm pin pitch  
    NC  
    UDQM  
    CLK  
    CKE  
    NC  
    BA0  
    A11  
    BA1  
    A9  
    A10/AP  
    A0  
    A8  
    A7  
    A1  
    A6  
    A2  
    A5  
    A3  
    A4  
    VDD  
    VSS  
    Rev. 1.5 / Feb. 2005  
    3
    Synchronous DRAM Memory 64Mbit (4Mx16bit)  
    HY57V641620E(L/S)T(P) Series  
    PIN DESCRIPTION  
    SYMBOL  
    TYPE  
    DESCRIPTION  
    The system clock input. All other inputs are registered to the  
    SDRAM on the rising edge of CLK  
    CLK  
    Clock  
    Controls internal clock signal and when deactivated, the SDRAM will  
    be one of the states among power down, suspend or self refresh  
    CKE  
    CS  
    Clock Enable  
    Chip Select  
    Enables or disables all inputs except CLK, CKE, UDQM and LDQM  
    Selects bank to be activated during RAS activity  
    Selects bank to be read/written during CAS activity  
    BA0, BA1  
    Bank Address  
    Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA7  
    Auto-precharge flag: A10  
    A0 ~ A11  
    Address  
    Row Address Strobe,  
    Column Address Strobe,  
    Write Enable  
    RAS, CAS and WE define the operation  
    Refer function truth table for details  
    RAS, CAS, WE  
    UDQM, LDQM  
    Controls output buffers in read mode and masks input data in write  
    mode  
    Data Input/Output Mask  
    DQ0 ~ DQ15  
    VDD / VSS  
    Data Input / Output  
    Multiplexed data input / output pin  
    Power Supply / Ground  
    Power supply for internal circuits and input buffers  
    Data Output Power /  
    Ground  
    VDDQ / VSSQ  
    NC  
    Power supply for output buffers  
    No connection  
    No Connection  
    Rev. 1.5 / Feb. 2005  
    4
    Synchronous DRAM Memory 64Mbit (4Mx16bit)  
    HY57V641620E(L/S)T(P) Series  
    FUNCTIONAL BLOCK DIAGRAM  
    1Mbit x 4banks x 16 I/O Synchronous DRAM  
    Internal Row  
    Counter  
    Self refresh  
    logic & timer  
    1Mx16 BANK 3  
    1Mx16 BANK 2  
    1Mx16 BANK 1  
    1Mx16 BANK 0  
    CLK  
    Row  
    Pre  
    Decoder  
    Row Active  
    CKE  
    CS  
    DQ0  
    RAS  
    CAS  
    Refresh  
    Memory  
    Cell  
    Array  
    Column Active  
    Column  
    Pre  
    WE  
    Decoder  
    DQ15  
    U/LDQM  
    Y-Decoder  
    Column Add  
    Counter  
    Bank Select  
    Address  
    Register  
    A0  
    A1  
    Burst  
    Counter  
    Pipe Line  
    Control  
    A11  
    BA1  
    BA0  
    CAS Latency  
    Mode Register  
    Data Out Control  
    Rev. 1.5 / Feb. 2005  
    5
    Synchronous DRAM Memory 64Mbit (4Mx16bit)  
    HY57V641620E(L/S)T(P) Series  
    BASIC FUNCTIONAL DESCRIPTION  
    Mode Register  
    BA1  
    0
    BA0  
    0
    A11  
    0
    A10  
    0
    A9  
    A8  
    0
    A7  
    0
    A6  
    A5  
    A4  
    A3  
    BT  
    A2  
    A1  
    A0  
    OP Code  
    CAS Latency  
    Burst Length  
    OP Code  
    A9  
    0
    Write Mode  
    Burst Read and Burst Write  
    Burst Read and Single Write  
    Burst Type  
    1
    A3  
    0
    Burst Type  
    Sequential  
    Interleave  
    1
    CAS Latency  
    Burst Length  
    A6  
    0
    A5  
    0
    A4  
    CAS Latency  
    Reserved  
    1
    Burst Length  
    A2  
    A1  
    A0  
    0
    1
    0
    1
    0
    1
    0
    1
    A3 = 0  
    A3=1  
    0
    0
    0
    0
    0
    0
    1
    1
    1
    1
    0
    0
    1
    1
    0
    0
    1
    1
    0
    1
    0
    1
    0
    1
    0
    1
    1
    2
    1
    2
    4
    8
    0
    1
    2
    0
    1
    3
    4
    1
    0
    R e s e r v e d  
    Reserved  
    Reserved  
    R e s e r v e d  
    8
    1
    0
    Reserved  
    Reserved  
    Reserved  
    Full Page  
    Reserved  
    Reserved  
    Reserved  
    Reserved  
    1
    1
    1
    1
    Rev. 1.5 / Feb. 2005  
    6
    Synchronous DRAM Memory 64Mbit (4Mx16bit)  
    HY57V641620E(L/S)T(P) Series  
    ABSOLUTE MAXIMUM RATING  
    Parameter  
    Symbol  
    Rating  
    Unit  
    oC  
    Ambient Temperature  
    TA  
    0 ~ 70  
    oC  
    V
    Storage Temperature  
    TSTG  
    VIN, VOUT  
    VDD, VDDQ  
    IOS  
    -55 ~ 125  
    -1.0 ~ 4.6  
    -1.0 ~ 4.6  
    50  
    Voltage on Any Pin relative to VSS  
    Voltage on VDD relative to VSS  
    Short Circuit Output Current  
    Power Dissipation  
    V
    mA  
    W
    PD  
    1
    oC / Sec  
    TSOLDER  
    Soldering Temperature / Time  
    260 / 10  
    o
    DC OPERATING CONDITION (TA= 0 to 70 C)  
    Parameter  
    Power Supply Voltage  
    Input High Voltage  
    Input Low Voltage  
    Symbol  
    VDD, VDDQ  
    VIH  
    Min  
    3.0  
    Typ  
    3.3  
    3.0  
    -
    Max  
    Unit  
    Note  
    1
    3.6  
    V
    V
    V
    2.0  
    VDDQ + 0.3  
    0.8  
    1, 2  
    1, 3  
    VIL  
    -0.3  
    Note: 1. All voltages are referenced to VSS = 0V  
    2. VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.  
    3. VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration.  
    o
    AC OPERATING TEST CONDITION (TA= 0 to 70 C, VDD=3.3±0.3V, VSS=0V)  
    Parameter  
    AC Input High/Low Level Voltage  
    Symbol  
    VIH / VIL  
    Vtrip  
    Value  
    2.4 / 0.4  
    1.4  
    Unit  
    V
    Note  
    Input Timing Measurement Reference Level Voltage  
    Input Rise/Fall Time  
    V
    tR / tF  
    Voutref  
    CL  
    1
    ns  
    V
    Output Timing Measurement Reference Level Voltage  
    Output Load Capacitance for Access Time Measurement  
    1.4  
    30  
    pF  
    1
    Note: 1.  
    Vtt=1.4V  
    Vtt=1.4V  
    RT=500 Ω  
    RT=50 Ω  
    Output  
    Z0 = 50Ω  
    Output  
    30pF  
    30pF  
    DC Output Load Circuit  
    AC Output Load Circuit  
    Rev. 1.5 / Feb. 2005  
    7
    Synchronous DRAM Memory 64Mbit (4Mx16bit)  
    HY57V641620E(L/S)T(P) Series  
    o
    CAPACITANCE (TA= 0 to 70 C, f=1MHz, VDD=3.3V)  
    Parameter  
    Pin  
    Symbol  
    Min  
    Max  
    Unit  
    CLK  
    CI1  
    2.0  
    4.0  
    pF  
    Input capacitance  
    A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE,  
    LDQM, UDQM  
    CI2  
    2.5  
    3.0  
    5.0  
    5.5  
    pF  
    pF  
    Data input / output capacitance  
    DQ0 ~ DQ15  
    CI/O  
    o
    DC CHARACTERRISTICS I (TA= 0 to 70 C)  
    Parameter  
    Symbol  
    Min  
    Max  
    Unit  
    Note  
    Input Leakage Current  
    Output Leakage Current  
    Output High Voltage  
    Output Low Voltage  
    ILI  
    ILO  
    -1  
    -1  
    2.4  
    -
    1
    1
    uA  
    uA  
    V
    1
    2
    VOH  
    VOL  
    -
    IOH = -4mA  
    IOL = +4mA  
    0.4  
    V
    Note: 1. VIN = 0 to 3.3V, All other balls are not tested under VIN =0V  
    2. DOUT is disabled, VOUT=0 to 3.6  
    Rev. 1.5 / Feb. 2005  
    8
    Synchronous DRAM Memory 64Mbit (4Mx16bit)  
    HY57V641620E(L/S)T(P) Series  
    o
    DC CHARACTERISTICS II (TA= 0 to 70 C)  
    Speed  
    Parameter  
    Symbol  
    Test Condition  
    Unit Note  
    5
    6
    7
    H
    Burst length=1, One bank active  
    tRC ≥ tRC(min), IOL=0mA  
    Operating Current  
    IDD1  
    120 110 100 100 mA  
    1
    Precharge Standby Cur- IDD2P  
    rent  
    CKE ≤ VIL(max), tCK = 15ns  
    2
    2
    mA  
    mA  
    IDD2PS CKE ≤ VIL(max), tCK = ∞  
    in Power Down Mode  
    CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns  
    Input signals are changed one time during  
    2clks.  
    All other pins ≥ VDD-0.2V or ≤ 0.2V  
    Precharge Standby Cur-  
    rent  
    in Non Power Down  
    Mode  
    IDD2N  
    18  
    mA  
    mA  
    mA  
    CKE ≥ VIH(min), tCK = ∞  
    Input signals are stable.  
    IDD2NS  
    IDD3P  
    15  
    CKE ≤ VIL(max), tCK = 15ns  
    3
    3
    Active Standby Current  
    in Power Down Mode  
    IDD3PS CKE ≤ VIL(max), tCK = ∞  
    CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns  
    Input signals are changed one time during  
    2clks.  
    All other pins ≥ VDD-0.2V or ≤ 0.2V  
    IDD3N  
    40  
    35  
    Active Standby Current  
    in Non Power Down  
    Mode  
    CKE ≥ VIH(min), tCK = ∞  
    Input signals are stable.  
    IDD3NS  
    Burst Mode Operating  
    Current  
    tCK ≥ tCK(min), IOL=0mA  
    All banks active  
    IDD4  
    IDD5  
    120 110 100 100 mA  
    170 160 150 150 mA  
    1
    2
    Auto Refresh Current  
    tRC ≥ tRC(min), All banks active  
    Normal  
    1
    mA  
    uA  
    3
    Low power  
    400  
    Self Refresh Current  
    IDD6  
    CKE ≤ 0.2V  
    Super Low  
    power  
    300  
    uA  
    3, 4  
    Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open  
    2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II  
    3. HY57V641620ET(P) Series: Normal Power  
    HY57V641620ELT(P) Series: Low Power  
    HY57V641620EST(P) Series: Super Low Power  
    Rev. 1.5 / Feb. 2005  
    9
    Synchronous DRAM Memory 64Mbit (4Mx16bit)  
    HY57V641620E(L/S)T(P) Series  
    AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)  
    5
    6
    7
    H
    Parameter  
    Symbol  
    Unit Note  
    Min Max Min Max Min Max Min Max  
    CL = 3  
    CL = 2  
    tCK3  
    tCK2  
    tCHW  
    tCLW  
    tAC3  
    tAC2  
    tOH  
    5.0  
    10  
    6.0  
    10  
    2.0  
    2.0  
    -
    7.0  
    10  
    2.0  
    2.0  
    -
    7.5  
    10  
    2.5  
    2.5  
    -
    ns  
    ns  
    System Clock  
    Cycle Time  
    1000  
    1000  
    1000  
    1000  
    Clock High Pulse Width  
    Clock Low Pulse Width  
    1.75  
    1.75  
    -
    -
    -
    -
    -
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    1
    1
    -
    -
    -
    -
    CL = 3  
    CL = 2  
    4.5  
    5.4  
    5.4  
    5.4  
    Access Time From Clock  
    2
    -
    6.0  
    -
    6.0  
    -
    6.0  
    -
    6.0  
    Data-out Hold Time  
    Data-Input Setup Time  
    Data-Input Hold Time  
    Address Setup Time  
    Address Hold Time  
    CKE Setup Time  
    2.0  
    1.5  
    0.8  
    1.5  
    0.8  
    1.5  
    0.8  
    1.5  
    0.8  
    1.0  
    -
    -
    2.0  
    1.5  
    0.8  
    1.5  
    0.8  
    1.5  
    0.8  
    1.5  
    0.8  
    1.0  
    -
    -
    2.5  
    1.5  
    0.8  
    1.5  
    0.8  
    1.5  
    0.8  
    1.5  
    0.8  
    1.5  
    -
    -
    2.5  
    1.5  
    0.8  
    1.5  
    0.8  
    1.5  
    0.8  
    1.5  
    0.8  
    1.5  
    -
    -
    tDS  
    -
    -
    -
    -
    1
    1
    1
    1
    1
    1
    1
    1
    tDH  
    -
    -
    -
    -
    tAS  
    -
    -
    -
    -
    tAH  
    -
    -
    -
    -
    -
    -
    -
    -
    tCKS  
    tCKH  
    tCS  
    CKE Hold Time  
    -
    -
    -
    -
    Command Setup Time  
    Command Hold Time  
    -
    -
    -
    -
    tCH  
    -
    -
    -
    -
    CLK to Data Output in Low-Z Time tOLZ  
    -
    -
    -
    -
    CL = 3  
    CL = 2  
    tOHZ3  
    tOHZ2  
    4.5  
    6.0  
    5.4  
    6.0  
    5.4  
    6.0  
    5.4  
    6.0  
    CLK to Data Output  
    in High-Z Time  
    -
    -
    -
    -
    Note: 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.  
    2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns,  
    then (tR/2-0.5)ns should be added to the parameter.  
    Rev. 1.5 / Feb. 2005  
    10  
    Synchronous DRAM Memory 64Mbit (4Mx16bit)  
    HY57V641620E(L/S)T(P) Series  
    AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)  
    5
    6
    7
    H
    Parameter  
    Symbol  
    Unit Note  
    Min Max Min Max Min Max Min Max  
    RAS Cycle Time  
    Operation  
    tRC  
    55  
    55  
    15  
    -
    -
    -
    60  
    60  
    18  
    42  
    18  
    12  
    1
    -
    63  
    63  
    20  
    42  
    20  
    14  
    1
    -
    -
    -
    63  
    63  
    20  
    -
    -
    -
    ns  
    ns  
    ns  
    RAS Cycle Time  
    RAS to CAS Delay  
    RAS Active Time  
    Auto Refresh tRRC  
    -
    tRCD  
    tRAS  
    -
    38.7 100K  
    100K  
    100K 42 120K ns  
    RAS Precharge Time  
    tRP  
    15  
    10  
    1
    -
    -
    -
    -
    -
    -
    -
    -
    -
    20  
    15  
    1
    -
    -
    -
    ns  
    ns  
    RAS to RAS Bank Active Delay  
    CAS to CAS Delay  
    tRRD  
    tCCD  
    CLK  
    Write Command to Data-In De-  
    lay  
    tWTL  
    0
    2
    -
    -
    0
    2
    -
    -
    0
    2
    -
    -
    0
    2
    -
    -
    CLK  
    CLK  
    Data-in to Precharge Command tDPL  
    Data-In to Active Command  
    DQM to Data-Out Hi-Z  
    DQM to Data-In Mask  
    MRS to New Command  
    tDAL  
    tDPL + tRP  
    tDQZ  
    tDQM  
    tMRD  
    tPROZ3  
    tPROZ2  
    tDPE  
    2
    0
    2
    3
    2
    1
    1
    -
    -
    -
    2
    0
    2
    3
    2
    1
    1
    -
    -
    -
    -
    -
    -
    -
    -
    2
    0
    2
    3
    2
    1
    1
    -
    -
    2
    0
    2
    3
    2
    1
    1
    -
    -
    -
    CLK  
    CLK  
    CLK  
    CLK  
    CLK  
    CLK  
    CLK  
    ms  
    -
    -
    -
    Prechargeto Data CL = 3  
    Output High-Z  
    CL = 2  
    -
    -
    -
    -
    -
    -
    Power Down Exit Time  
    Self Refresh Exit Time  
    Refresh Time  
    -
    -
    -
    tSRE  
    -
    -
    -
    1
    tREF  
    64  
    64  
    -
    64  
    64  
    Note: 1. A new command can be given tRRC after self refresh exit.  
    Rev. 1.5 / Feb. 2005  
    11  
    Synchronous DRAM Memory 64Mbit (4Mx16bit)  
    HY57V641620E(L/S)T(P) Series  
    COMMAND TRUTH TABLE  
    Command  
    CKEn-1 CKEn  
    CS  
    L
    RAS CAS WE DQM ADDR A10/AP  
    BA  
    Note  
    Mode Register Set  
    H
    H
    H
    X
    X
    X
    L
    X
    H
    L
    L
    X
    H
    H
    L
    X
    H
    H
    X
    X
    X
    OP code  
    H
    L
    No Operation  
    X
    Bank Active  
    Read  
    L
    RA  
    V
    V
    L
    H
    L
    H
    H
    H
    X
    X
    L
    L
    H
    H
    L
    L
    H
    L
    X
    X
    X
    CA  
    CA  
    X
    Read with Autopre-  
    charge  
    Write  
    V
    Write with Autopre-  
    charge  
    H
    H
    L
    Precharge All Banks  
    X
    V
    X
    X
    L
    L
    L
    H
    H
    L
    L
    Precharge  
    Bank  
    selected  
    Burst Stop  
    DQM  
    H
    H
    H
    H
    X
    V
    X
    X
    X
    X
    Auto Refresh  
    H
    X
    L
    L
    L
    L
    L
    L
    L
    H
    L
    X
    Burst-Read-Single-  
    WRITE  
    A9 ball High  
    (Other balls OP code)  
    MRS  
    Mode  
    H
    H
    X
    X
    Entry  
    L
    H
    L
    L
    X
    H
    X
    H
    X
    H
    X
    V
    L
    X
    H
    X
    H
    X
    H
    X
    V
    H
    X
    H
    X
    H
    X
    H
    X
    V
    Self Refresh1  
    X
    Exit  
    L
    H
    L
    H
    L
    X
    X
    X
    H
    L
    Entry  
    Exit  
    Precharge  
    power down  
    X
    X
    H
    L
    H
    H
    L
    Entry  
    Exit  
    H
    L
    L
    X
    X
    Clock  
    Suspend  
    H
    X
    Rev. 1.5 / Feb. 2005  
    12  
    Synchronous DRAM Memory 64Mbit (4Mx16bit)  
    HY57V641620E(L/S)T(P) Series  
    PACKAGE INFORMATION  
    400mil 54pin Thin Small Outline Package  
    UNIT : mm(inch)  
    11.938(0.4700)  
    11.735(0.4620)  
    22.327(0.8790)  
    22.149(0.8720)  
    10.262(0.4040)  
    10.058(0.3960)  
    0.150(0.0059)  
    0.050(0.0020)  
    1.194(0.0470)  
    0.991(0.0390)  
    5deg  
    0deg  
    0.210(0.0083)  
    0.120(0.0047)  
    0.597(0.0235)  
    0.406(0.0160)  
    0.400(0.016)  
    0.80(0.0315)BSC  
    0.300(0.012)  
    Rev. 1.5 / Feb. 2005  
    13  
    配单直通车
    HY57V641620ELT-5产品参数
    型号:HY57V641620ELT-5
    是否Rohs认证： 不符合
    生命周期：Obsolete
    零件包装代码：TSOP2
    包装说明：TSOP2, TSOP54,.46,32
    针数：54
    Reach Compliance Code：compliant
    ECCN代码：EAR99
    HTS代码：8542.32.00.02
    风险等级：5.88
    访问模式：FOUR BANK PAGE BURST
    最长访问时间：4.5 ns
    其他特性：AUTO/SELF REFRESH
    最大时钟频率 (fCLK)：200 MHz
    I/O 类型：COMMON
    交错的突发长度：1,2,4,8
    JESD-30 代码：R-PDSO-G54
    JESD-609代码：e0
    长度：22.238 mm
    内存密度：67108864 bit
    内存集成电路类型：SYNCHRONOUS DRAM
    内存宽度：16
    功能数量：1
    端口数量：1
    端子数量：54
    字数：4194304 words
    字数代码：4000000
    工作模式：SYNCHRONOUS
    最高工作温度：70 °C
    最低工作温度：
    组织：4MX16
    输出特性：3-STATE
    封装主体材料：PLASTIC/EPOXY
    封装代码：TSOP2
    封装等效代码：TSOP54,.46,32
    封装形状：RECTANGULAR
    封装形式：SMALL OUTLINE, THIN PROFILE
    峰值回流温度（摄氏度）：NOT SPECIFIED
    电源：3.3 V
    认证状态：Not Qualified
    刷新周期：4096
    座面最大高度：1.194 mm
    自我刷新：YES
    连续突发长度：1,2,4,8,FP
    最大待机电流：0.002 A
    子类别：DRAMs
    最大压摆率：0.21 mA
    最大供电电压 (Vsup)：3.6 V
    最小供电电压 (Vsup)：3 V
    标称供电电压 (Vsup)：3.3 V
    表面贴装：YES
    技术：CMOS
    温度等级：COMMERCIAL
    端子面层：Tin/Lead (Sn/Pb)
    端子形式：GULL WING
    端子节距：0.8 mm
    端子位置：DUAL
    处于峰值回流温度下的最长时间：NOT SPECIFIED
    宽度：10.16 mm
    Base Number Matches：1
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