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产品型号HY57V641620HG的概述

芯片HY57V641620HG的概述 HY57V641620HG是一款由韩华电子（Hynix）生产的高性能动态随机存取存储器（DRAM）芯片，广泛应用于各种电子设备中。它是一种高容量的64M x 16位DRAM，具有较高的读写速度和稳定性，适用于数据存储、缓冲以及作为系统内存使用。该芯片以其低功耗和高密度的特性，吸引了众多电子产品设计师的关注，使得其在现代电子市场上的应用日益广泛。该芯片的设计基于先进的CMOS工艺，支持多种操作模式，包括随机存取和顺序存取，能够满足不同客户的需求。HY57V641620HG具有559个引脚，采用TSOP-II封装，兼顾了物理尺寸和性能的平衡。这使得它能够在构建小型化设备时具有灵活性。芯片HY57V641620HG的详细参数 HY57V641620HG具有以下详细参数： - 存储容量：64M x 16位 - 工作电压：通常为3.3V - 内存类型：D...

产品型号HY57V641620HG的Datasheet PDF文件预览

HY57V641620HG

4 Banks x 1M x 16Bit Synchronous DRAM

DESCRIPTION

The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which

require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16.

HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-

nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated

by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of

read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst

read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

•

Auto refresh and self refresh

•

Single 3.3±0 . 3 V p o w e r s u p p l y ^{N o t e )}

4096 refresh cycles / 64ms

•

All device pins are compatible with LVTTL interface

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

•

J E D E C s t a n d a r d 4 0 0 m i l 5 4 p i n T S O P - I I w i t h 0 . 8 m m

of pin pitch

•

All inputs and outputs referenced to positive edge of

system clock

•

P r o g r a m m a b l e C A S Latency ; 2, 3 Clocks

•

D a t a m a s k f u n c t i o n b y U D Q M o r L D Q M

Internal four banks operation

OR D E R IN G INF ORMAT ION

Par t No.

C l ock Fr equency

Po we r

Or gani zat i on

I nt erf ace

Package

H Y 5 7 V 6 4 1 6 2 0 H G T - 5 / 5 5 / 6 / 7

H Y 5 7 V 6 4 1 6 2 0 H G T - K

H Y 5 7 V 6 4 1 6 2 0 H G T - H

H Y 5 7 V 6 4 1 6 2 0 H G T - 8

2 0 0 / 1 8 3 / 1 6 6 / 1 4 3 M H z

1 3 3 M H z

N o r m a l

1 2 5 M H z

H Y 5 7 V 6 4 1 6 2 0 H G T - P

H Y 5 7 V 6 4 1 6 2 0 H G T - S

H Y 5 7 V 6 4 1 6 2 0 H G L T - 5 / 5 5 / 6 / 7

H Y 5 7 V 6 4 1 6 2 0 H G L T - K

H Y 5 7 V 6 4 1 6 2 0 H G L T - H

H Y 5 7 V 6 4 1 6 2 0 H G L T - 8

H Y 5 7 V 6 4 1 6 2 0 H G L T - P

H Y 5 7 V 6 4 1 6 2 0 H G L T - S

1 0 0 M H z

4 B a n k s x 1 M b i t s

x 1 6

L V T T L

400mil 54pin TSOP II

2 0 0 / 1 8 3 / 1 6 6 / 1 4 3 M H z

1 3 3 M H z

L o w p o w e r

1 2 5 M H z

1 0 0 M H z

Not e : VDD( M in) of HY5 7 V6 4 1 6 2 0 HG( L) T- 5 /55/ 6 i s 3. 135V

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of

circuits described. No patent licenses are implied.

Rev. 0. 5/ Jun. 01

HY57V641620HG

P IN CONF IGURAT ION

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

VDD

LDQM

/WE

/CAS

/RAS

/CS

5 4

5 3

5 2

5 1

5 0

4 9

4 8

4 7

4 6

4 5

4 4

4 3

4 2

4 1

4 0

3 9

3 8

3 7

3 6

3 5

3 4

3 3

3 2

3 1

3 0

2 9

2 8

V SS

DQ15

V SSQ

DQ14

DQ13

V DDQ

DQ12

DQ11

V SSQ

DQ10

DQ9

V DDQ

DQ8

V SS

1 0

1 1

1 2

1 3

1 4

1 5

1 6

1 7

1 8

1 9

2 0

2 1

2 2

2 3

2 4

2 5

2 6

2 7

54pin TSOP II

400mil x 875mil

0.8mm pin pitch

UDQM

CLK

CKE

BA0

A11

BA1

A 9

A10/AP

A 0

A 8

A 7

A 1

A 6

A 2

A 5

A 3

A 4

VDD

V SS

P IN DE S CRIPTION

PI N

P I N N A ME

D E S C R I PTI ON

The system clock input. All other inputs are registered to the SDRAM on the

rising edge of CLK

C L K

C l o c k

Controls internal clock signal and when deactivated, the SDRAM will be one

of the states among power down, suspend or self refresh

C K E

C S

Clock Enable

Chip Select

E n a b l e s o r d i s a b l e s a l l i n p u t s e x c e p t C L K , C K E a n d D Q M

Selects bank to be activated during R A S activity

Selects bank to be read/written during C A S activity

B A 0 , B A 1

B a n k A d d r e s s

R o w A d d r e s s : R A 0 ~ R A 1 1 , C o l u m n A d d r e s s : C A 0 ~ C A 7

Auto-precharge flag : A10

A 0

A 1 1

A d d r e s s

R o w A d d r e s s S t r o b e ,

R A S , C A S a n d W E define the operation

Refer function truth table for details

R A S , C A S, W E

C o l u m n A d d r e s s S t r o b e ,

W r i t e E n a b l e

L D Q M , U D Q M

D Q 0 ~ D Q 1 5

V DD /V S S

D a t a I n p u t / O u t p u t M a s k

D a t a I n p u t / O u t p u t

Controls output buffers in read mode and masks input data in write mode

Multiplexed data input / output pin

P o w e r S u p p l y / G r o u n d

D a t a O u t p u t P o w e r / G r o u n d

N o C o n n e c t i o n

Power supply for internal circuits and input buffers

Power supply for output buffers

V D D Q /V S S Q

N C

N o c o n n e c t i o n

Rev. 0. 5/ Jun. 01

HY57V641620HG

F UNCT IONAL BL OCK DIA GR A M

1 M b i t x 4 b a n k s x 1 6 I / O S y n c h r o n o u s D R A M

Self refresh logic

& timer

Internal Row

counter

1 Mx 1 6 Ba nk 3

1 Mx 1 6 Ba nk 2

CLK

R o w

Pre

R o w a c t i v e

C K E

C S

D e c o d e r s

1 Mx 1 6 Ba nk 1

1 Mx 1 6 Ba nk 0

D Q0

D Q1

R A S

C A S

W E

M e m o r y

Cell

refresh

Array

C o l u m n

A c t i v e

C o l u m n

Pre

U D QM

L D QM

D e c o d e r s

DQ1 4

DQ1 5

Y d e c o d e r s

C o l u m n A d d

C o u n t e r

B a n k S e l e c t

A 0

A 1

A d d r e s s

Registers

B u r s t

C o u n t e r

A1 1

B A 0

B A 1

C A S L a t e n c y

P i p e L i n e C o n t r o l

Mode Regist ers

D a t a O u t C o n t r o l

Rev. 0. 5/ Jun. 01

HY57V641620HG

ABS OL UT E MAX IMU M R A T IN G S

Par ame t er

S y mb o l

Rat i ng

Uni t

A m b i e n t T e m p e r a t u r e

7 0

°C

S t o r a g e T e m p e r a t u r e

TS T G

- 5 5 ~ 1 2 5

-1.0 ~ 4.6

5 0

Voltage on Any Pin relative to V S S

Voltage on V D D relative to V S S

Short Circuit Output Current

Power Dissipation

V IN, V O U T

V D D , V D D Q

IO S

m A

P D

S o l d e r i n g T e m p e r a t u r e × T i m e

TS O L D E R

2 6 0 × 1 0

°C × S e c

N o t e : Operation at above absolute maximum rating can adversely affect device reliability

DC OP E RAT IN G C ON D ITION ( T A = 0 t o 7 0 °C )

Par ame t er

S y mb o l

M in

Ty p.

Ma x

U n it

N o te

P o w e r S u p p l y V o l t a g e

Input High Voltage

I n p u t L o w V o l t a g e

V D D , V D D Q

3.0

2.0

3.3

3.0

3.6

V DDQ + 2. 0

0.8

1,2

1,3

1,4

V IH

V IL

V S S Q - 2.0

N o t e :

1.All voltages are referenced to VS S

2 . V D D ( m i n ) o f H Y 5 7 V 6 4 1 6 2 0 H G ( L ) T - 5 / 5 5 / 6 i s 3 . 1 3 5 V

0 V

3.V IH (max) is acceptable 5. 6V AC pulse width with £ 3ns of duration

4.V IL (min) is acceptable -2. 0V AC pulse width with £ 3ns of duration

Note2

AC OP E RAT IN G C ON D ITION ( T A = 0 t o 7 0 °C , V D D=3. 3 ± 0 . 3 V

, V S S = 0 V )

Par ame t er

S y mb o l

Val ue

U n it

Not e

A C I n p u t H i g h / L o w L e v e l V o l t a g e

V IH / V IL

Vtrip

2.4/0.4

1.4

I n p u t T i m i n g M e a s u r e m e n t R e f e r e n c e L e v e l V o l t a g e

I n p u t R i s e / F a l l T i m e

tR / tF

Voutref

C L

n s

O u t p u t T i m i n g M e a s u r e m e n t R e f e r e n c e L e v e l

O u t p u t L o a d C a p a c i t a n c e f o r A c c e s s T i m e M e a s u r e m e n t

1.4

5 0

N o t e :

1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)

For details, refer to AC/DC output circuit

2 . V D D ( m i n ) o f H Y 5 7 V 6 4 1 6 2 0 H G ( L ) T - 5 / 5 5 / 6 i s 3 . 1 3 5 V

Rev. 0. 5/ Jun. 01

HY57V641620HG

CAP ACIT ANCE ( T A = 2 5°C , f = 1 M H z )

Pa r a me t e r

P in

S y mb o l

M in

Ma x

Uni t

Input capacitance

C L K

C I1

CI 2

A 0 ~ A 1 1 , B A 0 , B A 1 , C K E , C S , R A S ,

C A S , W E , U D Q M , L D Q M

2.5

Data input / output capacitance

D Q 0

D Q 1 5

C I/O

6.5

OUT P UT L OAD CIR C U IT

Vtt=1.4V

RT=250 W

Output

50pF

50 pF

DC Output Load Circuit

A C O u t p u t L o a d C i r c u i t

Note3

DC CHARACT E RISTICS I ( T A = 0 t o 7 0 ° C , V DD =3.3 ± 0 . 3 V

)

Par ame t er

S y mb o l

M i n.

Ma x

Uni t

Not e

I n p u t L e a k a g e C u r r e n t

O u t p u t L e a k a g e C u r r e n t

O u t p u t H i g h V o l t a g e

O u t p u t L o w V o l t a g e

ILI

-1

u A

IL O

V O H

V O L

2.4

IO H = - 4 m A

IO L = + 4 m A

0.4

N o t e :

1.V IN = 0 to 3.6V, All other pins are not tested under V IN = 0 V

2.DO U T is disabled, V O U T =0 to 3.6

Rev. 0. 5/ Jun. 01

HY57V641620HG

Note5

DC CHARACT E RISTICS II ( T A = 0 t o 7 0 °C , V D D =3.3 ± 0 . 3 V

, V S S = 0 V )

Spe e d

-K

Pa r a me t e r

S y mb o l

Test Condi t i on

Uni t

N o te

-5

- 55

- 6

- 7

-H

- 8

-P

- S

Burst length=1, One bank active

Operating Current

ID D 1

100

9 0

8 5

8 0

m A

tRC

³ tRC (min), IO L = 0 m A

P r e c h a r g e S t a n d b y

Current

ID D 2 P

C K E £ V IL(max), tC K = min

C K E £ V IL(max), tC K = ¥

m A

ID D 2 P S

i n P o w e r D o w n M o d e

C K E

³ V IH (min), C S ³ V IH(min), tC K

= min

ID D 2 N

Input signals are changed one time

during 2clks. All other pins ³ V DD -

0. 2V or £ 0 . 2 V

1 5

m A

P r e c h a r g e S t a n d b y

Current

i n N o n P o w e r D o w n M o d e

C K E

³ V IH (min), t C K = ¥

ID D 2 N S

1 2

m A

Input signals are stable.

C K E £ V IL(max), tC K = min

C K E £ V IL(max), tC K = ¥

ID D 3 P

m A

Active Standby Current

i n P o w e r D o w n M o d e

ID D 3 P S

C K E

³ V IH (min), C S ³ V IH(min), tC K

= min

ID D 3 N

Input signals are changed one time

during 2clks. All other pins ³ V DD -

0. 2V or £ 0 . 2 V

3 0

m A

Active Standby Current

i n N o n P o w e r D o w n M o d e

C K E

³ V IH (min), t C K = ¥

ID D 3 N S

2 0

m A

Input signals are stable.

C L = 3

C L = 2

170

N A

160

N A

150

N A

1 5 0

N A

150

120

m A

u A

B u r s t M o d e O p e r a t i n g

Current

tCK

³ tCK (min), IO L = 0 m A

ID D 4

ID D 5

ID D 6

All banks active

A u t o R e f r e s h C u r r e n t

Self Refresh Current

tR R C

tR R C (min), All banks active

160

C K E £ 0 . 2 V

400

N o t e :

1.ID D 1 a n d I D D 4 depend on output loading and cycle rates. Specified values are measured with the output open

2. Min. of tRRC (Refresh R A S c y c l e t i m e ) i s s h o w n a t A C C H A R A C T E R I S T I C S I I

3 . H Y 5 7 V 6 4 1 6 2 0 H G T - 6 / 7 / K / H / P / S

4 . H Y 5 7 V 6 4 1 6 2 0 H G L T - 6 / 7 / K / H / P / S

Rev. 0. 5/ Jun. 01

HY57V641620HG

AC CHARACT E RIST ICS I (AC operating conditions unless otherwise noted)

-5

- 55

-6

-7

-K

-H

-8

-P

-S

Pa r a me t e r

S y mb o l

Uni t

Not e

M in

Ma x

Mi n

Ma x M in

Ma x

Mi n

Ma x

M in

Ma x

M in

Ma x

M in Ma x

M in

Ma x

Mi n

Ma x

C A S L a t e n c y

tCK3

tCK2

5 5

7. 5

7.5

n s

S y s t e m c l o c k

cycle time

1 0 0

1 0 0 0

1000

1 0 0 0

1000

1 0 0 0

1000

C A S L a t e n c y

1 0

7. 5

Clock high pulse width

Clock low pulse width

t C H W

tCLW

2. 5

2.75

2.5

2. 5

2.5

n s

C A S L a t e n c y

t A C 3

t A C 2

5. 4

5.4

5. 4

n s

A c c e s s t i m e

from clock

C A S L a t e n c y

D a t a - o u t h o l d t i m e

Data-Input setup time

Data-Input hold time

A d d r e s s s e t u p t i m e

A d d r e s s h o l d t i m e

C K E s e t u p t i m e

t O H

t D S

t D H

tAS

2. 5

1. 5

0. 8

1. 5

0. 8

1. 5

0. 8

1. 5

0. 8

2. 5

1. 5

0. 8

1. 5

0. 8

1. 5

0. 8

1. 5

0. 8

2.7

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

2. 7

1. 5

0. 8

1. 5

0. 8

1. 5

0. 8

1. 5

0. 8

1. 5

2. 7

1. 5

0. 8

1. 5

0. 8

1. 5

0. 8

1. 5

0. 8

1. 5

2.7

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

1.5

n s

tAH

tCKS

tCKH

t C S

t C H

C K E h o l d t i m e

C o m m a n d s e t u p t i m e

C o m m a n d h o l d t i m e

C L K t o d a t a o u t p u t i n l o w Z - t i m e t O L Z

C A S L a t e n c y

t O H Z 3

t O H Z 2

n s

C L K t o d a t a

output in high

Z - t i m e

5. 4

5.4

5. 4

C A S L a t e n c y

Not e :

1. Assume tR / tF (input rise and fall time ) is 1ns

2. Access times to be measured with input signals of 1v/ns edge rate

Rev. 0. 5/ Jun. 01

HY57V641620HG

AC CHARACT E RISTICS I

-5

- 55

-6

-7

-K

-H

- 8

-P

-S

S y mb o

Pa r a me t e r

Uni t

Not e

M in

Ma x

M in

Ma x

M in Ma x

M in

Ma x

M in

Ma x

M in

Ma x

M in Ma x

Mi n

7 0

2 0

Ma x

M in

Ma x

Operation

n s

tRC

R A S Cycle

T i m e

A u t o R e f r e s h

tR R C

tR C D

R A S to C A S D e l a y

R A S Active Time

16. 5

1 0 0

tR A S

tRP

38.5 1 0 0 K 38. 5 1 0 0 K

120K

1 2 0 K

120K

5 0

2 0

1 2 0 K

n s

R A S P r e c h a r g e T i m e

16. 5

R A S to R A S Bank Active

D e l a y

n s

tR R D

tC C D

tW T L

C A S to C A S D e l a y

C L K

W r i t e C o m m a n d t o D a t a - I n

D e l a y

Data-In to Precharge

C o m m a n d

tD P L

C L K

D a t a - I n t o A c t i v e C o m m a n d

D Q M t o D a t a - O u t H i - Z

D Q M t o D a t a - I n M a s k

M R S t o N e w C o m m a n d

C A S L a t e n c y

tD A L

tD Q Z

tD Q M

tM R D

C L K

tP R O Z

C L K

= 3

Precharge to

D a t a O u t p u t

Hi-Z

C A S L a t e n c y

= 2

tP R O Z

P o w e r D o w n E x i t T i m e

S e l f R e f r e s h E x i t T i m e

R e f r e s h T i m e

tP D E

tS R E

tR E F

C L K

m s

6 4

N o t e :

1 . A n e w c o m m a n d c a n b e g i v e n t R R C a f t e r s e l f r e f r e s h e x i t

Rev. 0. 5/ Jun. 01

HY57V641620HG

DE V ICE OP E RAT ING OP T ION T ABL E

HY5 7 V6 4 1 6 2 0 HG( L) T- 5

C A S Lat ency

t RCD

t RAS

t RC

t RP

t AC

tO H

2 0 0 MHz ( 5 ns )

1 8 3 MHz ( 5 . 5 ns )

1 6 6 MHz ( 6 ns )

3 C L K s

7 C L K s

1 0 C L K s

3 C L K s

5 . 4 n s

2 . 5 n s

2 . 7 n s

HY5 7 V6 4 1 6 2 0 HG( L) T- 55

C A S Lat ency

t RCD

t RAS

t RC

t RP

t AC

tO H

1 8 3 MHz ( 5 . 5 ns )

1 6 6 MHz ( 6 ns )

1 4 3 MHz ( 7 ns )

3 C L K s

7 C L K s

1 0 C L K s

3 C L K s

5 . 4 n s

2 . 5 n s

2 . 7 n s

HY5 7 V6 4 1 6 2 0 HG( L) T- 6

C A S Lat ency

3 C L K s

t RCD

t RAS

t RC

t RP

t AC

tO H

1 6 6 MHz ( 6 ns )

1 4 3 MHz ( 7 ns )

1 3 3 MHz ( 7 . 5 ns )

3 C L K s

7 C L K s

6 C L K s

1 0 C L K s

9 C L K s

3 C L K s

5 . 4 n s

2 . 7 n s

3 C L K s

2 C L K s

HY5 7 V6 4 1 6 2 0 HG( L) T- 7

C A S Lat ency

3 C L K s

t RCD

t RAS

t RC

t RP

t AC

tO H

1 4 3 MHz ( 7 ns )

1 3 3 MHz ( 7 . 5 ns )

1 0 0 MHz ( 1 0 ns )

3 C L K s

2 C L K s

6 C L K s

5 C L K s

9 C L K s

7 C L K s

3 C L K s

2 C L K s

5 . 4 n s

6 n s

2 . 7 n s

3 n s

3 C L K s

2 C L K s

HY5 7 V6 4 1 6 2 0 HG( L) T- K

C A S Lat ency

2 C L K s

t RCD

t RAS

t RC

t RP

t AC

tO H

1 3 3 MHz ( 7 . 5 ns )

1 2 5 MHz ( 8 ns )

1 0 0 MHz ( 1 0 ns )

2 C L K s

3 C L K s

2 C L K s

6 C L K s

5 C L K s

8 C L K s

9 C L K s

7 C L K s

2 C L K s

3 C L K s

2 C L K s

5 . 4 n s

6 n s

2 . 7 n s

3 n s

3 C L K s

2 C L K s

6 n s

3 n s

HY5 7 V6 4 1 6 2 0 HG( L) T- H

C A S Lat ency

3 C L K s

t RCD

t RAS

t RC

t RP

t AC

tO H

1 3 3 MHz ( 7 . 5 ns )

1 2 5 MHz ( 8 ns )

1 0 0 MHz ( 1 0 ns )

3 C L K s

2 C L K s

6 C L K s

5 C L K s

9 C L K s

7 C L K s

3 C L K s

2 C L K s

5 . 4 n s

6 n s

2 . 7 n s

3 n s

3 C L K s

2 C L K s

6 n s

3 n s

Rev. 0. 5/ Jun. 01

HY57V641620HG

4 Banks x 1M x 16Bit Synchronous DRAM

HY5 7 V6 4 1 6 2 0 HG( L) T- 8

C A S Lat ency

3 C L K s

t RCD

t RAS

t RC

t RP

t AC

tO H

1 2 5 MHz ( 8 ns )

1 0 0 MHz ( 1 0 ns )

8 3 MHz ( 1 2 ns )

3 C L K s

2 C L K s

3 C L K s

7 C L K s

5 C L K s

6 C L K s

1 0 C L K s

7 C L K s

9 C L K s

3 C L K s

2 C L K s

6 n s

3 n s

2 C L K s

3 C L K s

HY5 7 V6 4 1 6 2 0 HG( L) T- P

C A S Lat ency

2 C L K s

t RCD

t RAS

t RC

t RP

t AC

tO H

1 0 0 MHz ( 1 0 ns )

8 3 MHz ( 1 2 ns )

6 6 MHz ( 1 5 ns )

2 C L K s

5 C L K s

4 C L K s

7 C L K s

6 C L K s

2 C L K s

6 n s

3 n s

2 C L K s

HY5 7 V6 4 1 6 2 0 HG( L) T- S

C A S Lat ency

3 C L K s

t RCD

t RAS

t RC

t RP

t AC

tO H

1 0 0 MHz ( 1 0 ns )

8 3 MHz ( 1 2 ns )

6 6 MHz ( 1 5 ns )

2 C L K s

5 C L K s

4 C L K s

7 C L K s

6 C L K s

2 C L K s

6 n s

3 n s

2 C L K s

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of

circuits described. No patent licenses are implied.

Rev. 0. 5/ Jun. 01

HY57V641620HG

COMMAND T RUT H T ABL E

A1 0 /

A D D R

C o mma n d

CKEn- 1

C K E n

C S

R A S

C A S

W E

D Q M

Not e

M o d e R e g i s t e r S e t

O P c o d e

No Operation

Bank Active

R A

Read

C A

R e a d w i t h A u t o p r e c h a r g e

Write

Write with Autoprecharge

Precharge All Banks

P r e c h a r g e s e l e c t e d B a n k

Burst Stop

D Q M

Auto Refresh

Entry

Self Refresh

Exit

Entry

P r e c h a r g e

p o w e r d o w n

Exit

Entry

C l o c k

S u s p e n d

Exit

N o t e :

1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high

2 . X = D o n¢t c a r e , H = L o g i c H i g h , L = L o g i c L o w . B A = B a n k A d d r e s s , R A = R o w A d d r e s s , C A = C o l u m n A d d r e s s ,

O p c o d e = O p e r a n d C o d e , N O P = N o O p e r a t i o n

Rev. 0. 5/ Jun. 01

1 1

HY57V641620HG

P ACKAGE INF ORMAT ION

4 0 0 m i l 54pi n Thi n Sm al l O u t l i ne Package

U N I T : m m ( i n c h )

11.938(0.4700)

11.735(0.4620)

22.327(0.8790)

22.149(0.8720)

10.262(0.4040)

10.058(0.3960)

0. 150(0. 0059)

0. 050(0. 0020)

1. 194(0. 0470)

0. 991(0. 0390)

5 d e g

0 d e g

0. 210(0. 0083)

0. 120(0. 0047)

0. 597(0. 0235)

0. 406(0. 0160)

0. 400(0. 016)

0. 80(0. 0315)BSC

0. 300(0. 012)

Rev. 0. 5/ Jun. 01

1 2

HY57V641620HG相关文章

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HY57V641620HGLT-5产品参数

型号:	HY57V641620HGLT-5
生命周期：	Obsolete
IHS 制造商：	SK HYNIX INC
零件包装代码：	TSOP2
包装说明：	TSOP2, TSOP54,.46,32
针数：	54
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.32.00.02
风险等级：	5.8
访问模式：	FOUR BANK PAGE BURST
最长访问时间：	4.5 ns
其他特性：	AUTO/SELF REFRESH
最大时钟频率 (fCLK)：	200 MHz
I/O 类型：	COMMON
交错的突发长度：	1,2,4,8
JESD-30 代码：	R-PDSO-G54
JESD-609代码：	e6
长度：	22.23 mm
内存密度：	67108864 bit
内存集成电路类型：	SYNCHRONOUS DRAM
内存宽度：	16
功能数量：	1
端口数量：	1
端子数量：	54
字数：	4194304 words
字数代码：	4000000
工作模式：	SYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	4MX16
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP2
封装等效代码：	TSOP54,.46,32
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE
电源：	3.3 V
认证状态：	Not Qualified
刷新周期：	4096
座面最大高度：	1.194 mm
自我刷新：	YES
连续突发长度：	1,2,4,8,FP
最大待机电流：	0.002 A
子类别：	DRAMs
最大压摆率：	0.17 mA
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	TIN BISMUTH
端子形式：	GULL WING
端子节距：	0.8 mm
端子位置：	DUAL
宽度：	10.16 mm
Base Number Matches：	1

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