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产品型号HY5DV641622AT的Datasheet PDF文件预览

HY5DV641622AT  
64M(4Mx16) DDR SDRAM  
HY5DV641622AT  
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev. 0.7/May. 02  
1
HY5DV641622AT  
Revision History  
4. Revision 0.7 (May. 02)  
1) Input leakage current changed from +/-5uA to +/-2uA  
3. Revision 0.6 (Dec. 01)  
1) Separated ‘Function description’ and ‘Timing diagram’ parts  
- These are available in Web site (www.hynix.com)  
2. Revision 0.5 (Nov. 01)  
1) Changed tCK maximum value  
a) 300/275Mhz : Changed from 4.5ns to 4.0ns  
b) 250/200Mhz : Changed from 8.0ns to 6.5ns  
2) Changed ‘VDDQ range’ from +/- 0.2V to +/- 5%  
- Changed from 2.3V/2.5V/2.7V to 2.375V/2.5V/2.625V (min/typ/max)  
1. Revision 0.4 (Sep. 01)  
1) Removed 183/166Mhz parts from speed bin  
2) Changed Cas Latency from 3 to 4 at 300/275Mhz  
3) Changed tRCD from 5clk to 6clk at 300/275Mhz  
4) Changed tCK maximum value from 8ns to 4.5ns at 300/275Mhz  
5) Changed VDD value  
a) 275Mhz : Changed from 3.15V/3.30V/3.45V to 3.20V/3.30V/3.45V (min/typ/max)  
b) 300Mhz : Changed from 3.15V/3.30V/3.45V to 3.35V/3.45V/3.55V (min/typ/max)  
6) Modified ‘Burst Read followed by Burst Write’ function  
- Burst Write command must be issued after (CL + BL/2 + 1) ticks of clock from Burst Read command,  
not (CL + BL/2) ticks of clock at 300/275Mhz  
Rev. 0.7/May. 02  
2
HY5DV641622AT  
DESCRIPTION  
The Hynix HY5DV641622 is a 67,108,864-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the  
point-to-point applications which requires high bandwidth.  
The Hynix 4Mx16 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the  
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,  
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-  
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible  
with SSTL_2.  
FEATURES  
3.3V for VDD and 2.5V for VDDQ power supply  
All addresses and control inputs except Data, Data  
strobes and Data masks latched on the rising edges  
of the clock  
All inputs and outputs are compatible with SSTL_2  
interface  
Write mask byte controls by LDM and UDM  
Programmable /CAS Latency 3 / 4 supported  
JEDEC standard 400mil 66pin TSOP-II with 0.65mm  
pin pitch  
Fully differential clock inputs (CK, /CK) operation  
Double data rate interface  
Programmable Burst Length 2 / 4 / 8 with both  
sequential and interleave mode  
Internal 4 bank operations with single pulsed /RAS  
tRAS Lock-Out function supported  
Source synchronous - data transaction aligned to  
bidirectional data strobe (DQS)  
x16 device has 2 bytewide data strobes (LDQS,  
UDQS) per each x8 I/O  
Auto refresh and self refresh supported  
4096 refresh cycles / 64ms  
Data outputs on DQS edges when read (edged DQ)  
Data inputs on DQS centers when write (centered  
DQ)  
Full, Half and Matched Impedance(Weak) strength  
driver option controlled by EMRS  
Data(DQ) and Write masks(DM) latched on the both  
rising and falling edges of the data strobe  
ORDERING INFORMATION  
Clock  
Frequency  
Part No.  
Power Supply  
Max Data Rate  
interface  
Package  
HY5DV641622AT-33  
HY5DV641622AT-36  
HY5DV641622AT-4  
HY5DV641622AT-5  
300MHz  
275MHz  
250MHz  
200MHz  
600Mbps/pin  
550Mbps/pin  
500Mbps/pin  
400Mbps/pin  
VDD=3.3V  
400mil 66pin  
TSOP-II  
SSTL_2  
VDDQ=2.5V  
Rev. 0.7/May. 02  
3
HY5DV641622AT  
PIN CONFIGURATION  
VDD  
DQ0  
VDDQ  
DQ1  
DQ2  
VSSQ  
DQ3  
DQ4  
VDDQ  
DQ5  
DQ6  
VSSQ  
DQ7  
NC  
1
66  
65  
64  
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54  
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52  
51  
50  
49  
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38  
37  
36  
35  
34  
VSS  
2
DQ15  
VSSQ  
DQ14  
DQ13  
VDDQ  
DQ12  
DQ11  
VSSQ  
DQ10  
DQ9  
VDDQ  
DQ8  
NC  
TOP VIEW  
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
400mil X 875mil  
66 Pin TSOP-II  
0.65mm Pin Pitch  
VDDQ  
LDQS  
NC  
VDD  
NC  
VSSQ  
UDQS  
NC  
VREF  
VSS  
LDM  
/WE  
/CAS  
/RAS  
/CS  
UDM  
/CLK  
CLK  
CKE  
NC  
NC  
NC  
BA0  
BA1  
A10/AP  
A0  
A11  
A9  
A8  
A7  
A1  
A6  
A2  
A5  
A3  
A4  
VDD  
VSS  
ROW and COLUMN ADDRESS TABLE  
Items  
4Mx16  
Organization  
Row Address  
1M x 16 x 4banks  
A0 ~ A11  
A0 ~ A7  
BA0, BA1  
A10  
Column Address  
Bank Address  
Auto Precharge Flag  
Refresh  
4K  
Rev. 0.7/May. 02  
4
HY5DV641622AT  
PIN DESCRIPTION  
PIN  
TYPE  
DESCRIPTION  
Clock: CK and /CK are differential clock inputs. All address and control input signals are  
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output  
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).  
CK, /CK  
Input  
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and  
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER  
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row  
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF  
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE  
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding  
CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are  
disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW  
level after Vdd is applied.  
CKE  
Input  
Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-  
mands are masked when CS is registered high. CS provides for external bank selection on  
systems with multiple banks. CS is considered part of the command code.  
/CS  
Input  
Input  
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-  
CHARGE command is being applied.  
BA0, BA1  
Address Inputs: Provide the row address for ACTIVE commands, and the column address  
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the  
memory array in the respective bank. A10 is sampled during a precharge command to  
determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10  
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The  
address inputs also provide the op code during a MODE REGISTER SET command. BA0  
and BA1 define which mode register is loaded during the MODE REGISTER SET command  
(MRS or EMRS).  
A0 ~ A11  
Input  
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being  
entered.  
/RAS, /CAS, /WE  
LDM, UDM  
Input  
Input  
Input Data Mask: DM(LDM,UDM) is an input mask signal for write data. Input data is  
masked when DM is sampled HIGH along with that input data during a WRITE access.  
DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading  
matches the DQ and DQS loading. LDM corresponds to the data on DQ0-Q7; UDM corre-  
sponds to the data on DQ8-Q15.  
Data Strobe: Output with read data, input with write data. Edge aligned with read data,  
centered in write data. Used to capture write data. LDQS corresponds to the data on  
DQ0-Q7; UDQS corresponds to the data on DQ8-Q15.  
LDQS, UDQS  
I/O  
DQ0 ~ DQ15  
VDD/VSS  
VDDQ/VSSQ  
VREF  
I/O  
Data input / output pin : Data Bus  
Supply  
Supply  
Supply  
NC  
Power supply for internal circuits and input buffers.  
Power supply for output buffers for noise immunity.  
Reference voltage for inputs for SSTL interface.  
No connection.  
NC  
Rev. 0.7/May. 02  
5
HY5DV641622AT  
FUNCTIONAL BLOCK DIAGRAM  
4Banks x 1Mbit x 16 I/O Double Data Rate Synchronous DRAM  
16  
Write Data Register  
2-bit Prefetch Unit  
DS  
32  
CLK  
/CLK  
CKE  
Bank  
Control  
1Mx16/Bank0  
1Mx16/Bank1  
1Mx16/Bank2  
1Mx16/Bank3  
32  
16  
/CS  
Command  
Decoder  
/RAS  
/CAS  
/WE  
LDM  
UDM  
DQ[0:15]  
Mode  
Register  
Row  
Decoder  
Column Decoder  
LDQS, UDQS  
A0 ~ A11  
BA0, BA1  
Address  
Buffer  
Column Address  
Counter  
Data Strobe  
Transmitter  
CLK_DLL  
Data Strobe  
Receiver  
DS  
DLL  
CLK  
Block  
Mode  
Register  
Rev. 0.7/May. 02  
6
HY5DV641622AT  
SIMPLIFIED COMMAND TRUTH TABLE  
A10/  
AP  
Command  
CKEn-1  
CKEn  
CS  
RAS  
CAS  
WE  
ADDR  
BA  
Note  
Extended Mode Register Set  
Mode Register Set  
Device Deselect  
No Operation  
H
H
X
X
L
L
L
L
L
L
L
L
OP code  
OP code  
1,2  
1,2  
H
L
X
H
L
X
H
H
X
H
H
H
H
H
X
X
X
X
1
Bank Active  
L
RA  
V
V
1
1
Read  
L
H
L
L
L
L
H
H
L
L
L
H
L
CA  
CA  
X
Read with Autoprecharge  
Write  
1,3  
1
H
H
X
X
V
Write with Autoprecharge  
Precharge All Banks  
Precharge selected Bank  
Read Burst Stop  
Auto Refresh  
H
H
L
1,4  
1,5  
1
X
V
H
L
H
H
H
X
H
L
L
L
H
L
H
L
L
H
H
X
H
X
H
X
H
X
V
X
X
1
1
Entry  
L
L
L
1
Self Refresh  
Exit  
H
L
X
H
X
H
X
H
X
V
X
H
X
H
X
H
X
V
X
X
X
L
H
L
H
L
1
H
L
1
1
1
1
1
1
1
Entry  
Precharge Power  
Down Mode  
H
L
Exit  
H
H
L
Entry  
H
L
L
Active Power  
Down Mode  
Exit  
H
X
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )  
Note :  
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.  
2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS.  
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP  
period from Prechagre command.  
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented  
to activated bank until CK(n+BL/2+tRP).  
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented  
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time  
(tWR) is needed to guarantee that the last data has been completely written.  
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be  
precharged.  
Rev. 0.7/May. 02  
7
HY5DV641622AT  
WRITE MASK TRUTH TABLE  
A10/  
AP  
ADDR  
Note  
Function  
Data Write  
CKEn-1  
CKEn  
/CS, /RAS, /CAS, /WE  
LDM  
UDM  
BA  
H
H
X
X
X
X
L
L
X
X
1,2  
1,2  
Data-In Mask  
H
H
Lower Byte Write /  
Upper Byte-In Mask  
H
H
X
X
X
X
L
H
L
X
X
1,2  
1,2  
Upper Byte Write /  
Lower Byte-In Mask  
H
Note :  
1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data.  
2. LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively.  
Rev. 0.7/May. 02  
8
HY5DV641622AT  
OPERATION COMMAND TRUTH TABLE - I  
Current  
State  
/CS  
/RAS  
/CAS  
/WE  
Address  
Command  
Action  
NOP or power down3  
NOP or power down3  
ILLEGAL4  
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DSEL  
NOP  
X
X
BST  
ILLEGAL4  
H
BA, CA, AP  
READ/READAP  
IDLE  
ILLEGAL4  
Row Activation  
NOP  
L
L
L
L
L
H
L
L
H
L
L
H
H
L
L
H
L
BA, CA, AP  
WRITE/WRITEAP  
ACT  
BA, RA  
L
BA, AP  
PRE/PALL  
AREF/SREF  
MRS  
Auto Refresh or Self Refresh5  
L
H
L
X
L
L
OPCODE  
Mode Register Set  
X
H
H
X
H
H
X
H
L
X
X
X
DSEL  
NOP  
NOP  
NOP  
ILLEGAL4  
Begin read : optional AP6  
Begin write : optional AP6  
ILLEGAL4  
BST  
L
L
L
L
L
H
H
L
L
L
H
L
BA, CA, AP  
BA, CA, AP  
BA, RA  
BA, AP  
X
READ/READAP  
WRITE/WRITEAP  
ACT  
ROW  
ACTIVE  
H
H
L
H
L
Precharge7  
L
PRE/PALL  
ILLEGAL11  
L
H
AREF/SREF  
ILLEGAL11  
L
H
L
L
L
L
L
L
L
L
X
H
H
H
H
L
L
X
H
H
L
L
X
H
L
OPCODE  
MRS  
DSEL  
X
Continue burst to end  
Continue burst to end  
Terminate burst  
X
X
NOP  
BST  
Term burst, new read:optional AP8  
ILLEGAL  
H
L
BA, CA, AP  
BA, CA, AP  
BA, RA  
BA, AP  
X
READ/READAP  
WRITE/WRITEAP  
ACT  
L
READ  
ILLEGAL4  
H
H
L
H
L
L
PRE/PALL  
AREF/SREF  
Term burst, precharge  
ILLEGAL11  
L
H
ILLEGAL11  
L
H
L
L
X
H
H
L
X
H
H
L
X
H
L
OPCODE  
MRS  
DSEL  
NOP  
BST  
X
X
X
Continue burst to end  
Continue burst to end  
L
WRITE  
ILLEGAL4  
Term burst, new read:optional AP8  
Term burst, new write:optional AP  
L
L
H
H
L
L
H
L
BA, CA, AP  
BA, CA, AP  
READ/READAP  
WRITE/WRITEAP  
Rev. 0.7/May. 02  
9
HY5DV641622AT  
OPERATION COMMAND TRUTH TABLE - II  
Current  
State  
/CS  
/RAS  
/CAS  
/WE  
Address  
Command  
Action  
ILLEGAL4  
L
L
L
L
L
L
H
H
L
H
L
BA, RA  
BA, AP  
X
ACT  
PRE/PALL  
AREF/SREF  
Term burst, precharge  
WRITE  
ILLEGAL11  
H
ILLEGAL11  
Continue burst to end  
Continue burst to end  
ILLEGAL  
L
H
L
L
X
L
X
H
H
L
L
X
H
L
OPCODE  
MRS  
DSEL  
X
H
H
H
X
X
NOP  
L
BST  
ILLEGAL10  
ILLEGAL10  
ILLEGAL4,10  
ILLEGAL4,10  
ILLEGAL11  
L
H
BA, CA, AP  
READ/READAP  
READ  
WITH  
AUTOPRE-  
CHARGE  
L
L
L
L
H
L
L
L
L
H
H
L
L
H
L
BA, CA, AP  
BA, RA  
BA, AP  
X
WRITE/WRITEAP  
ACT  
PRE/PALL  
AREF/SREF  
H
ILLEGAL11  
Continue burst to end  
Continue burst to end  
ILLEGAL  
L
H
L
L
X
L
X
H
H
L
L
X
H
L
OPCODE  
MRS  
DSEL  
X
H
H
H
X
X
NOP  
L
BST  
ILLEGAL10  
ILLEGAL10  
ILLEGAL4,10  
ILLEGAL4,10  
ILLEGAL11  
L
H
BA, CA, AP  
READ/READAP  
WRITE  
AUTOPRE-  
CHARGE  
L
L
L
L
H
L
L
L
L
H
H
L
L
H
L
BA, CA, AP  
BA, RA  
BA, AP  
X
WRITE/WRITEAP  
ACT  
PRE/PALL  
AREF/SREF  
H
ILLEGAL11  
L
H
L
L
X
H
H
L
X
H
H
L
X
H
L
OPCODE  
MRS  
DSEL  
NOP  
BST  
X
X
X
NOP-Enter IDLE after tRP  
NOP-Enter IDLE after tRP  
ILLEGAL4  
ILLEGAL4,10  
ILLEGAL4,10  
L
L
L
L
L
L
L
H
H
L
L
L
H
L
BA, CA, AP  
BA, CA, AP  
BA, RA  
BA, AP  
READ/READAP  
WRITE/WRITEAP  
ACT  
PRE-  
CHARGE  
ILLEGAL4,10  
H
H
L
H
L
L
PRE/PALL  
AREF/SREF  
MRS  
NOP-Enter IDLE after tRP  
ILLEGAL11  
ILLEGAL11  
L
H
L
X
L
L
OPCODE  
Rev. 0.7/May. 02  
10  
HY5DV641622AT  
OPERATION COMMAND TRUTH TABLE - III  
Current  
State  
/CS  
/RAS  
/CAS  
/WE  
Address  
Command  
Action  
H
L
X
H
H
X
H
H
X
H
L
X
X
X
DSEL  
NOP  
BST  
NOP - Enter ROW ACT after tRCD  
NOP - Enter ROW ACT after tRCD  
ILLEGAL4  
ILLEGAL4,10  
ILLEGAL4,10  
ILLEGAL4,9,10  
ILLEGAL4,10  
ILLEGAL11  
L
L
L
L
L
L
H
H
L
L
L
H
L
BA, CA, AP  
BA, CA, AP  
BA, RA  
BA, AP  
X
READ/READAP  
WRITE/WRITEAP  
ACT  
ROW  
ACTIVATING  
H
H
L
H
L
L
PRE/PALL  
L
H
AREF/SREF  
ILLEGAL11  
L
H
L
L
L
L
L
L
X
H
H
H
H
L
L
X
H
H
L
L
X
H
L
OPCODE  
MRS  
DSEL  
X
X
NOP - Enter ROW ACT after tWR  
NOP - Enter ROW ACT after tWR  
NOP  
ILLEGAL4  
ILLEGAL  
ILLEGAL  
X
BST  
H
L
BA, CA, AP  
BA, CA, AP  
BA, RA  
READ/READAP  
WRITE/WRITEAP  
ACT  
WRITE  
RECOVERING  
L
ILLEGAL4,10  
ILLEGAL4,11  
ILLEGAL11  
H
H
L
L
L
L
H
L
L
BA, AP  
X
PRE/PALL  
H
AREF/SREF  
ILLEGAL11  
L
H
L
L
X
H
H
L
X
H
H
L
X
H
L
OPCODE  
MRS  
DSEL  
NOP  
BST  
X
X
X
NOP - Enter precharge after tDPL  
NOP - Enter precharge after tDPL  
ILLEGAL4  
ILLEGAL4,8,10  
ILLEGAL4,10  
ILLEGAL4,10  
ILLEGAL4,11  
ILLEGAL11  
L
WRITE  
RECOVERING  
WITH  
AUTOPRE-  
CHARGE  
L
L
L
L
L
H
H
L
L
L
H
L
BA, CA, AP  
BA, CA, AP  
BA, RA  
BA, AP  
X
READ/READAP  
WRITE/WRITEAP  
ACT  
H
H
L
H
L
L
PRE/PALL  
L
H
AREF/SREF  
ILLEGAL11  
L
H
L
L
X
H
H
L
X
H
H
L
X
H
L
OPCODE  
MRS  
DSEL  
NOP  
BST  
X
X
X
NOP - Enter IDLE after tRC  
NOP - Enter IDLE after tRC  
REFRESHING  
ILLEGAL11  
ILLEGAL11  
L
L
H
L
H
BA, CA, AP  
READ/READAP  
Rev. 0.7/May. 02  
11  
HY5DV641622AT  
OPERATION COMMAND TRUTH TABLE - IV  
Current  
State  
/CS  
/RAS  
/CAS  
/WE  
Address  
Command  
Action  
ILLEGAL11  
ILLEGAL11  
ILLEGAL11  
ILLEGAL11  
L
L
L
L
H
L
L
L
L
H
H
L
L
H
L
BA, CA, AP  
BA, RA  
BA, AP  
X
WRITE/WRITEAP  
ACT  
WRITE  
PRE/PALL  
AREF/SREF  
H
ILLEGAL11  
L
H
L
L
X
H
H
L
X
H
H
L
X
H
L
OPCODE  
MRS  
DSEL  
NOP  
BST  
X
X
X
NOP - Enter IDLE after tMRD  
NOP - Enter IDLE after tMRD  
ILLEGAL11  
ILLEGAL11  
ILLEGAL11  
ILLEGAL11  
ILLEGAL11  
ILLEGAL11  
ILLEGAL11  
L
L
L
L
L
L
L
H
H
L
L
L
H
L
BA, CA, AP  
BA, CA, AP  
BA, RA  
BA, AP  
READ/READAP  
WRITE/WRITEAP  
ACT  
MODE  
REGISTER  
ACCESSING  
H
H
L
H
L
L
PRE/PALL  
AREF/SREF  
MRS  
L
H
L
X
L
L
OPCODE  
Note :  
1. H - Logic High Level, L - Logic Low Level, X - Don’t Care, V - Valid Data Input,  
BA - Bank Address, AP - AutoPrecharge Address, CA - Column Address, RA - Row Address, NOP - NO Operation.  
2. All entries assume that CKE was active(high level) during the preceding clock cycle.  
3. If both banks are idle and CKE is inactive(low level), then in power down mode.  
4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Address(BA) depending on the state of  
that bank.  
5. If both banks are idle and CKE is inactive(low level), then self refresh mode.  
6. Illegal if tRCD is not met.  
7. Illegal if tRAS is not met.  
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.  
9. Illegal if tRRD is not met.  
10. Illegal for single bank, but legal for other banks in multi-bank devices.  
11. Illegal for all banks.  
Rev. 0.7/May. 02  
12  
HY5DV641622AT  
CKE FUNCTION TRUTH TABLE  
Current  
State  
CKEn-  
1
CKEn  
/CS  
/RAS  
/CAS  
/WE  
/ADD  
Action  
H
L
X
H
H
H
H
H
L
X
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID  
Exit self refresh, enter idle after tSREX  
Exit self refresh, enter idle after tSREX  
ILLEGAL  
L
SELF  
REFRESH1  
L
L
L
L
X
X
X
X
X
H
L
ILLEGAL  
L
L
X
X
X
X
H
H
L
ILLEGAL  
L
X
X
H
L
X
X
X
H
H
H
L
NOP, continue self refresh  
INVALID  
H
L
X
H
H
H
H
H
L
Exit power down, enter idle  
Exit power down, enter idle  
ILLEGAL  
L
POWER  
DOWN2  
L
L
L
L
X
X
X
X
H
X
H
L
ILLEGAL  
L
L
X
X
X
L
ILLEGAL  
L
X
X
L
X
X
L
NOP, continue power down mode  
See operation command truth table  
Enter self refresh  
Exit power down  
Exit power down  
ILLEGAL  
H
H
H
H
H
H
H
H
L
H
L
L
H
L
X
H
H
H
L
X
H
H
L
L
ALL BANKS  
IDLE4  
L
L
L
L
X
X
L
ILLEGAL  
L
L
H
L
ILLEGAL  
L
L
L
ILLEGAL  
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOP  
H
H
L
H
L
See operation command truth table  
ANY STATE  
OTHER  
THAN  
ILLEGAL5  
INVALID  
INVALID  
H
L
ABOVE  
L
Note :  
When CKE=L, all DQ and DQS must be in Hi-Z state.  
1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command.  
2. All command can be stored after 2 clocks from low to high transition of CKE.  
3. Illegal if CK is suspended or stopped during the power down mode.  
4. Self refresh can be entered only from the all banks idle state.  
5. Disabling CK may cause malfunction of any bank which is in active state.  
Rev. 0.7/May. 02  
13  
HY5DV641622AT  
SIMPLIFIED STATE DIAGRAM  
MRS  
SREF  
SREX  
MODE  
REGISTER  
SET  
SELF  
REFRESH  
IDLE  
PDEN  
PDEX  
AREF  
ACT  
POWER  
DOWN  
AUTO  
REFRESH  
POWER  
DOWN  
PDEN  
BST  
PDEX  
BANK  
ACTIVE  
READ  
WRITE  
READ  
READAP  
WRITE  
WITH  
READ  
WITH  
READAP  
WRITE  
READ  
AUTOPRE-  
CHARGE  
AUTOPRE-  
CHARGE  
WRITEAP  
WRITEAP  
WRITE  
PRE(PALL)  
PRE(PALL)  
PRE-  
CHARGE  
Command Input  
POWER-UP  
Automatic Sequence  
POWER APPLIED  
Rev. 0.7/May. 02  
14  
HY5DV641622AT  
POWER-UP SEQUENCE AND DEVICE INITIALIZATION  
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those  
specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and finally to VREF (and  
to the system VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause permanent damage to  
the device. VREF can be applied anytime after VDDQ, but is expected to be nominally coincident with VTT. Except for  
CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input, but will detect an LVCMOS  
LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to guarantee  
that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a  
read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM  
requires a 200us delay prior to applying an executable command.  
Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be  
brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED  
MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE  
REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating  
parameters. 200 clock cycles are required between the DLL reset and any command. During the 200 cycles of CK, for  
DLL locking, executable commands are disallowed (a DESELECT or NOP command must be applied). After the 200  
clock cycles, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state.  
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command  
for the Mode Register with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the  
DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.  
1. Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVC-  
MOS low state. (All the other input pins may be undefined.)  
• VDD and VDDQ are driven from a single power converter output.  
• VTT is limited to 1.44V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation.  
• VREF tracks VDDQ/2.  
• A minimum resistance of 42 Ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the  
input current from the VTT supply into any pin.  
• If the above criteria cannot be met by the system design, then the following sequencing and voltage relation-  
ship must be adhered to during power up.  
Votage description  
Sequencing  
Voltage relationship to avoid latch-up  
< VDD + 0.3V  
VDDQ  
VTT  
After or with VDD  
After or with VDDQ  
After or with VDDQ  
< VDDQ + 0.3V  
VREF  
< VDDQ + 0.3V  
2. Start clock and maintain stable clock for a minimum of 200usec.  
3. After stable power and clock, apply NOP condition and take CKE high.  
4. Issue Extended Mode Register Set (EMRS) to enable DLL.  
5. Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=High. (An additional 200  
cycles of clock are required for locking DLL)  
6. Issue Precharge commands for all banks of the device.  
Rev. 0.7/May. 02  
15  
HY5DV641622AT  
7. Issue 2 or more Auto Refresh commands.  
8. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low.  
Power-Up Sequence  
VDD  
VDDQ  
tVTD  
VTT  
VREF  
/CLK  
CLK  
tIS tIH  
CKE  
NOP  
PRE  
EMRS  
MRS  
NOP  
PRE  
AREF  
MRS  
CMD  
LDM,UDM  
ADDR  
CODE  
CODE  
CODE  
CODE  
CODE  
CODE  
CODE  
CODE  
CODE  
A10  
BA0,BA1  
LDQS,  
UDQS  
DQ’s  
T=200usec  
tMRD  
200 cycles of CK*  
tRP  
tRFC  
tRP  
Power up  
EMRS Set  
MRS Set  
Reset DLL  
(with A8=H)  
2 or more  
MRS Set  
Precharge All  
Precharge All  
VDD and CK stable  
Auto Refresh (with A8=L)  
*200 cycles of CK are required (for DLL locking) before any executable command can be applied.  
Rev. 0.7/May. 02  
16  
HY5DV641622AT  
MODE REGISTER SET (MRS)  
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,  
burst type, test mode, DLL reset. The mode register is program via MRS command. This command is issued by the low  
signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and CKE  
must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to  
write the data in mode register. During the the MRS cycle, any command cannot be issued. Once mode register field is  
determined, the information will be held until resetted by another MRS command.  
BA1 BA0 A11 A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
BT  
A2  
A1  
A0  
0
0
RFU  
DR  
TM  
CAS Latency  
Burst Length  
BA0  
0
MRS Type  
A7  
0
Test Mode  
MRS  
Normal  
Test  
1
EMRS  
1
Burst Length  
A2  
A1  
A0  
A8  
0
DLL Reset  
No  
Sequential  
Interleave  
Reserved  
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved  
2
1
Yes  
4
4
8
8
A6  
0
A5  
0
A4  
0
CAS Latency  
Reserved  
Reserved  
Reserved  
3
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
1
0
1
0
0
1
1
1
0
0
4
A3  
0
Burst Type  
Sequential  
Interleave  
1
0
1
Reserved  
Reserved  
Reserved  
1
1
0
1
1
1
1
Rev. 0.7/May. 02  
17  
HY5DV641622AT  
BURST DEFINITION  
Burst Length  
2
Starting Address (A2,A1,A0)  
Sequential  
0, 1  
Interleave  
XX0  
XX1  
X00  
X01  
X10  
X11  
000  
001  
010  
011  
100  
101  
110  
111  
0, 1  
1, 0  
1, 0  
0, 1, 2, 3  
0, 1, 2, 3  
1, 2, 3, 0  
1, 0, 3, 2  
4
2, 3, 0, 1  
2, 3, 0, 1  
3, 0, 1, 2  
3, 2, 1, 0  
0, 1, 2, 3, 4, 5, 6, 7  
1, 2, 3, 4, 5, 6, 7, 0  
2, 3, 4, 5, 6, 7, 0, 1  
3, 4, 5, 6, 7, 0, 1, 2  
4, 5, 6, 7, 0, 1, 2, 3  
5, 6, 7, 0, 1, 2, 3, 4  
6, 7, 0, 1, 2, 3, 4, 5  
0, 1, 2, 3, 4, 5, 6, 7  
0, 1, 2, 3, 4, 5, 6, 7  
1, 0, 3, 2, 5, 4, 7, 6  
2, 3, 0, 1, 6, 7, 4, 5  
3, 2, 1, 0, 7, 6, 5, 4  
4, 5, 6, 7, 0, 1, 2, 3  
5, 4, 7, 6, 1, 0, 3, 2  
6, 7, 4, 5, 2, 3, 0, 1  
7, 6, 5, 4, 3, 2, 1, 0  
8
BURST LENGTH & TYPE  
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst  
length determines the maximum number of column locations that can be accessed for a given Read or Write com-  
mand. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types.  
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.  
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All  
accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is  
reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is  
set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a  
given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within  
the block. The programmed burst length applies to both Read and Write bursts.  
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the  
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the  
burst type and the starting column address, as shown in Burst Definitionon Table  
Rev. 0.7/May. 02  
18  
HY5DV641622AT  
CAS LATENCY  
The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the  
availability of the first burst of output data. The latency can be programmed 3 or 4 clocks.  
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident  
with clock edge n + m.  
Reserved states should not be used as unknown operation or incompatibility with future versions may result.  
DLL RESET  
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon return-  
ing to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically  
disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any  
time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally  
applied clock before an any command can be issued.  
OUTPUT DRIVER IMPEDANCE CONTROL  
The HY5DV641622A supports Full, Half strength driver and Matched impedance driver, intended for lighter load and/or  
point-to-point environments. The Full drive strength for all output is specified to be SSTL_2, CLASS II. Half strength  
driver is to define about 50% of Full drive strength and Matched impedance driver, about 30% of Full drive strength.  
Rev. 0.7/May. 02  
19  
HY5DV641622AT  
EXTENDED MODE REGISTER SET (EMRS)  
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional func-  
tions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits  
shown below. The Extended Mode Register is programmed via the Mode Register Set command ( BA0=1 and BA1=0)  
and will retain the stored information until it is programmed again or the device loses power.  
The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller  
must wait the specified time before initiating any subsequent operation. Violating either of these requirements will  
result in unspecified operation.  
BA1 BA0 A11 A10  
A9  
A8  
A7  
A6  
DS  
A5  
A4  
A3  
A2  
A1  
DS  
A0  
0
1
RFU*  
RFU*  
DLL  
A0  
0
DLL enable  
Enable  
BA0  
0
MRS Type  
MRS  
1
Diable  
1
EMRS  
A6  
A1  
0
Output Driver Impedance Control  
0
0
1
1
Full  
1
Half  
RFU*  
0
1
Matched Impedance (Weak)  
* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage.  
Rev. 0.7/May. 02  
20  
HY5DV641622AT  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Ambient Temperature  
Storage Temperature  
Symbol  
TA  
Rating  
0 ~ 70  
Unit  
oC  
oC  
V
TSTG  
-55 ~ 125  
Voltage on Any Pin relative to VSS  
Voltage on VDD relative to VSS  
Voltage on VDDQ relative to VSS  
Output Short Circuit Current  
Power Dissipation  
VIN, VOUT  
VDD  
-0.5 ~ 3.6  
-0.5 ~ 3.6  
-0.5 ~ 3.6  
50  
V
VDDQ  
IOS  
V
mA  
W
PD  
1
oC sec  
Soldering Temperature Time  
TSOLDER  
260 10  
Note : Operation at above absolute maximum rating can adversely affect device reliability  
DC OPERATING CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)  
Parameter  
Symbol  
Min  
Typ.  
Max  
Unit  
Note  
3.15  
3.2  
3.3  
3.45  
3.45  
V
V
V
V
V
V
V
V
1
2
3
4
3.3  
Power Supply Voltage  
VDD  
3.35  
3.45  
3.55  
Power Supply Voltage  
Input High Voltage  
Input Low Voltage  
Termination Voltage  
Reference Voltage  
VDDQ  
VIH  
2.375  
2.5  
2.625  
VREF + 0.15  
-0.3  
-
-
VDDQ + 0.3  
VREF - 0.15  
VREF + 0.04  
0.51*VDDQ  
VIL  
5
6
VTT  
VREF - 0.04  
0.49*VDDQ  
VREF  
0.5*VDDQ  
VREF  
Note :  
1. VDD specification for 250/200Mhz  
2. VDD specification for 275Mhz  
3. VDD specification for 300Mhz  
4. VDDQ must not exceed the level of VDD.  
5. VIL (min) is acceptable -1.5V AC pulse width with 5ns of duration.  
6. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same.  
Peak to peak noise on VREF may not exceed ± 2% of the dc value.  
Rev. 0.7/May. 02  
21  
HY5DV641622AT  
DC CHARACTERISTICS I (TA=0 to 70oC, Voltage referenced to VSS = 0V)  
Parameter  
Symbol  
Min.  
Max  
Unit  
Note  
Input Leakage Current  
Output Leakage Current  
Output High Voltage  
Output Low Voltage  
ILI  
ILO  
-2  
2
uA  
uA  
V
1
-5  
5
2
VOH  
VOL  
VTT + 0.76  
-
-
IOH = -15.2mA  
IOL = +15.2mA  
VTT - 0.76  
V
Note : 1. VIN = 0 to 3.6V, All other pins are not tested under VIN = 0V. 2. DOUT is disabled, VOUT = 0 to 2.7V  
DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V)  
Speed  
Note  
Parameter  
Symbol  
Test Condition  
Unit  
33  
36  
4
5
Burst length=2, One bank active  
tRC tRC(min), IOL=0mA  
Operating Current  
IDD1  
150  
130  
120  
100  
mA  
mA  
1
Precharge Standby Current  
in Power Down Mode  
IDD2P  
CKE VIL(max), tCK = min  
20  
20  
CKE VIH(min), CS VIH(min), tCK = min  
Input signals are changed one time during  
2clks  
Precharge Standby Current  
in Non Power Down Mode  
IDD2N  
IDD3P  
IDD3N  
IDD4  
100  
90  
80  
70  
mA  
mA  
mA  
mA  
Active Standby Current  
in Power Down Mode  
CKE VIL(max), tCK = min  
CKE VIH(min), CS VIH(min), tCK = min  
Input signals are changed one time during  
2clks  
Active Standby Current  
in Non Power Down Mode  
100  
250  
90  
80  
70  
Burst Mode Operating  
Current  
tCK tCK(min), IOL= 0mA  
All banks active  
230  
210  
190  
1
tRC tRFC (min),  
All banks active  
Auto Refresh Current  
Self Refresh Current  
Note :  
IDD5  
IDD6  
200  
2
mA  
mA  
1,2  
CKE 0.2V  
1. IDD1, IDD4 and IDD5 depend on output loading and cycle rates. Specified values are measured with the output open.  
2. Min. of tRFC (Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS.  
Rev. 0.7/May. 02  
22  
HY5DV641622AT  
AC OPERATING CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)  
Parameter  
Symbol  
Min  
Max  
Unit  
Note  
Input High (Logic 1) Voltage, DQ, DQS and DM signals  
Input Low (Logic 0) Voltage, DQ, DQS and DM signals  
Input Differential Voltage, CK and /CK inputs  
VIH(AC)  
VIL(AC)  
VID(AC)  
VIX(AC)  
VREF + 0.35  
V
V
V
V
VREF - 0.35  
VDDQ + 0.6  
0.7  
1
2
Input Crossing Point Voltage, CK and /CK inputs  
0.5*VDDQ-0.2  
0.5*VDDQ+0.2  
Note :  
1. VID is the magnitude of the difference between the input level on CK and the input on CK.  
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.  
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)  
Parameter  
Value  
Unit  
Reference Voltage  
Termination Voltage  
VDDQ x 0.5  
V
V
VDDQ x 0.5  
AC Input High Level Voltage (VIH, min)  
AC Input Low Level Voltage (VIL, max)  
Input Timing Measurement Reference Level Voltage  
Output Timing Measurement Reference Level Voltage  
Input Signal maximum peak swing  
VREF + 0.35  
V
VREF - 0.35  
V
VREF  
VTT  
1.5  
1
V
V
V
Input minimum Signal Slew Rate  
V/ns  
Termination Resistor (RT)  
50  
Series Resistor (RS)  
25  
Output Load Capacitance for Access Time Measurement (CL)  
30  
pF  
Rev. 0.7/May. 02  
23  
HY5DV641622AT  
AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)  
33  
36  
4
5
Unit Note  
Parameter  
Symbol  
Min  
52.8  
72  
Max  
Min  
54  
72  
36  
6
Max  
Min  
56  
72  
36  
5
Max  
Min  
60  
75  
40  
4
Max  
Row Cycle Time  
tRC  
-
-
-
-
ns  
ns  
ns  
CK  
CK  
Auto Refresh Row Cycle Time  
Row Active Time  
tRFC  
tRAS  
-
-
-
-
36.3  
6
120K  
120K  
120K  
120K  
Row Address to Column Address Delay tRCD  
-
-
-
-
-
-
-
-
Row Active to Row Active Delay  
tRRD  
tCCD  
tRP  
2
2
2
2
Column Address to Column Address  
Delay  
1
5
3
2
8
-
-
-
-
-
1
5
3
2
8
-
-
-
-
-
1
5
2
2
7
-
-
-
-
-
1
4
2
1
6
-
-
-
-
-
CK  
CK  
CK  
CK  
CK  
Row Precharge Time  
Last Data-In to Precharge Delay Time  
(Write Recovery Time : tWR)  
tDPL  
tDRL  
tDAL  
Last Data-In to Read Command  
Auto Precharge Write Recovery +  
Precharge Time  
CL = 4.0 tCK  
CL = 3.0 tCK  
3.3  
-
4.0  
-
3.6  
-
4.0  
-
-
-
-
-
ns  
ns  
CK  
CK  
ns  
ns  
ns  
System Clock Cycle Time  
4
6.5  
0.55  
0.55  
0.5  
0.5  
0.4  
5
6.5  
0.55  
0.55  
0.5  
0.5  
0.4  
Clock High Level Width  
tCH  
0.45  
0.45  
-1.0  
-1.0  
-
0.55  
0.55  
0.5  
0.5  
0.4  
0.45  
0.45  
-1.0  
-1.0  
-
0.55  
0.55  
0.5  
0.5  
0.4  
0.45  
0.45  
-1.0  
-1.0  
-
0.45  
0.45  
-1.0  
-1.0  
-
Clock Low Level Width  
tCL  
Data-Out edge to Clock edge Skew  
DQS-Out edge to Clock edge Skew  
tAC  
tDQSCK  
DQS-Out edge to Data-Out edge Skew tDQSQ  
tHPmin  
-tQHS  
tHPmin  
-tQHS  
tHPmin  
-tQHS  
tHPmin  
-tQHS  
Data-Out hold time from DQS  
Clock Half Period  
tQH  
tHP  
-
-
-
-
-
-
-
-
ns 1, 6  
ns 1, 5  
tCH/L  
min  
tCH/L  
min  
tCH/L  
min  
tCH/L  
min  
Data Hold Skew Factor  
Input Setup Time  
tQHS  
tIS  
-
0.4  
-
-
0.4  
-
-
0.4  
-
-
0.75  
-
ns  
ns  
6
2
2
0.9  
0.9  
0.4  
0.4  
0.8  
0.9  
0.9  
0.4  
0.4  
0.8  
0.9  
0.9  
0.4  
0.4  
0.8  
0.9  
0.9  
0.4  
0.4  
0.75  
Input Hold Time  
tIH  
-
-
-
-
ns  
Write DQS High Level Width  
Write DQS Low Level Width  
Clock to First Rising edge of DQS-In  
tDQSH  
tDQSL  
tDQSS  
0.6  
0.6  
1.25  
0.6  
0.6  
1.25  
0.6  
0.6  
1.25  
0.6  
0.6  
1.25  
CK  
CK  
CK  
Rev. 0.7/May. 02  
24  
HY5DV641622AT  
33  
36  
4
5
Unit Note  
Parameter  
Symbol  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Data-In Setup Time to DQS-In  
(DQ & DM)  
tDS  
tDH  
0.4  
-
0.4  
-
0.4  
-
0.5  
-
ns  
ns  
3
3
Data-In Hold Time to DQS-In  
(DQ & DM)  
0.4  
-
0.4  
-
0.4  
-
0.5  
-
Read DQS Preamble Time  
Read DQS Postamble Time  
Write DQS Preamble Setup Time  
Write DQS Preamble Hold Time  
Write DQS Postamble Time  
Mode Register Set Delay  
tRPRE  
0.9  
0.4  
0
1.1  
0.6  
-
0.9  
0.4  
0
1.1  
0.6  
-
0.9  
0.4  
0
1.1  
0.6  
-
0.9  
0.4  
0
1.1  
0.6  
-
CK  
CK  
ns  
tRPST  
tWPRES  
tWPREH  
tWPST  
tMRD  
1.5  
0.4  
3
-
1.5  
0.4  
3
-
1.5  
0.4  
3
-
1.5  
0.4  
2
-
ns  
0.6  
-
0.6  
-
0.6  
-
0.6  
-
CK  
CK  
Exit Self Refresh to Any Execute  
Command  
tXSC  
200  
-
-
200  
-
-
200  
-
-
200  
-
-
CK  
us  
4
Average Periodic Refresh Interval  
tREFI  
15.6  
15.6  
15.6  
15.6  
Note :  
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.  
2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.  
3. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.  
4. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete  
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.  
5. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this  
value can be greater than the minimum specification limits for tCL and tCH).  
6. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of  
tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects, and p-channel to  
n-channel variation of the output drivers.  
7. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.  
Signal transitions through the DC region must be monotonic.  
Rev. 0.7/May. 02  
25  
HY5DV641622AT  
CAPACITANCE (TA=25oC, f=1MHz )  
Parameter  
Pin  
Symbol  
Min  
Max  
Unit  
Input Clock Capacitance  
Input Capacitance  
CK, CK  
CCK  
CIN  
CIO  
2.0  
2.0  
4.0  
3.0  
3.0  
5.0  
pF  
pF  
pF  
All other input-only pins  
DQ, DQS, DM  
Input / Output Capacitanc  
Note :  
1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V  
2. Pins not under test are tied to GND.  
3. These values are guaranteed by design and are tested on a sample basis only.  
OUTPUT LOAD CIRCUIT  
VTT  
VTT  
RT=50Ω  
RT=50Ω  
Output  
RS=25Ω  
Zo=50Ω  
VREF  
CL=30pF  
Rev. 0.7/May. 02  
26  
HY5DV641622AT  
PACKAGE INFORMATION  
400mil 66pin Thin Small Outline Package  
Unit : mm(Inch)  
11.94 (0.470)  
11.79 (0.462)  
10.26 (0.404)  
10.05 (0.396)  
BASE PLANE  
22.33 (0.879)  
22.12 (0.871)  
0 ~ 5 Deg.  
0.35 (0.0138)  
0.25 (0.0098)  
0.65 (0.0256) BSC  
SEATING PLANE  
1.194 (0.0470)  
0.991 (0.0390)  
0.15 (0.0059)  
0.05 (0.0020)  
0.597 (0.0235)  
0.406 (0.0160)  
0.210 (0.0083)  
0.120 (0.0047)  
Note : Package do not mold protrusion. Allowable protrusion of both sides is 0.4mm.  
Rev. 0.7/May. 02  
27  
配单直通车
HY5DV641622AT-33产品参数
型号:HY5DV641622AT-33
生命周期:Obsolete
IHS 制造商:SK HYNIX INC
零件包装代码:TSOP2
包装说明:TSOP2, TSSOP66,.46
针数:66
Reach Compliance Code:unknown
ECCN代码:EAR99
HTS代码:8542.32.00.02
风险等级:5.81
访问模式:FOUR BANK PAGE BURST
最长访问时间:0.5 ns
其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):300 MHz
I/O 类型:COMMON
交错的突发长度:2,4,8
JESD-30 代码:R-PDSO-G66
JESD-609代码:e6
长度:22.225 mm
内存密度:67108864 bit
内存集成电路类型:DDR DRAM
内存宽度:16
功能数量:1
端口数量:1
端子数量:66
字数:4194304 words
字数代码:4000000
工作模式:SYNCHRONOUS
最高工作温度:70 °C
最低工作温度:
组织:4MX16
输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2
封装等效代码:TSSOP66,.46
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE
电源:2.5,3.3 V
认证状态:Not Qualified
刷新周期:4096
座面最大高度:1.2 mm
自我刷新:YES
连续突发长度:2,4,8
最大待机电流:0.02 A
子类别:DRAMs
最大压摆率:0.25 mA
最大供电电压 (Vsup):3.55 V
最小供电电压 (Vsup):3.35 V
标称供电电压 (Vsup):3.45 V
表面贴装:YES
技术:CMOS
温度等级:COMMERCIAL
端子面层:TIN BISMUTH
端子形式:GULL WING
端子节距:0.65 mm
端子位置:DUAL
宽度:10.16 mm
Base Number Matches:1
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