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产品型号HYI25D512160C的Datasheet PDF文件预览

November 2006  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
DDR SDRAM  
Internet Data Sheet  
Rev. 1.0  
Internet Data Sheet  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
HYI25D512160C[C/E/F/T]  
Revision History: 2006-11, Rev. 1.0  
Page  
Subjects (major changes since last revision)  
All  
All  
Adapted internet edition  
Qimonda update, first final revision  
We Listen to Your Comments  
Any information within this document that you feel is wrong, unclear or missing at all?  
Your feedback will help us to continuously improve the quality of this document.  
Please send your proposal (including a reference to this document) to:  
techdoc@qimonda.com  
qag_techdoc_rev400 / 3.2 QAG / 2006-08-07  
11082006-S9OT-UFSN  
2
Internet Data Sheet  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
1
Overview  
This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main  
characteristics.  
1.1  
Features  
Double data rate architecture: two data transfers per clock cycle  
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver  
DQS is edge-aligned with data for reads and is center-aligned with data for writes  
Differential clock inputs (CK and CK)  
Four internal banks for concurrent operation  
Data mask (DM) for write data  
DLL aligns DQ and DQS transitions with CK transitions  
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS  
Burst Lengths: 2, 4, or 8  
CAS Latency: 2, 2.5, 3  
Auto Precharge option for each burst access  
Auto Refresh and Self Refresh Modes  
RAS-lockout supported tRAP= tRCD  
7.8 µs Maximum Average Periodic Refresh Interval  
2.5 V (SSTL_2 compatible) I/O  
VDDQ = 2.5 V ± 0.2 V  
VDD = 2.5 V ± 0.2 V  
Packages : P-TSOPII-66, PG-TSOPII-66, P-TFBGA-60, PG-TFBGA-60  
TABLE 1  
Performance for –5 and –6  
Part Number Speed Code  
–5  
–6  
Unit  
Speed Grade  
Component  
@CL3  
DDR400B  
200  
DDR333B  
166  
Max. Clock Frequency  
fCK3  
MHz  
MHz  
MHz  
@CL2.5  
@CL2  
fCK2.5  
fCK2  
166  
166  
133  
133  
Rev. 1.0, 2006-11  
3
11082006-S9OT-UFSN  
Internet Data Sheet  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
1.2  
Description  
The 512-Mbit Double-Data-Rate SDRAM is a high-speed  
CMOS, dynamic random-access memory containing  
536,870,912 bits. It is internally configured as a quad-bank  
DRAM.  
Read and write accesses to the DDR SDRAM are burst  
oriented; accesses start at a selected location and continue  
for a programmed number of locations in a programmed  
sequence. Accesses begin with the registration of an Active  
command, which is then followed by a Read or Write  
command. The address bits registered coincident with the  
Active command are used to select the bank and row to be  
accessed. The address bits registered coincident with the  
Read or Write command are used to select the bank and the  
starting column location for the burst access.  
The 512-Mbit Double-Data-Rate SDRAM uses a double-  
data-rate architecture to achieve high-speed operation. The  
double data rate architecture is essentially a 2n prefetch  
architecture with an interface designed to transfer two data  
words per clock cycle at the I/O pins. A single read or write  
access  
for  
the  
512-Mbit Double-Data-Rate SDRAM  
effectively consists of a single 2n-bit wide, one clock cycle  
data transfer at the internal DRAM core and two  
corresponding n-bit wide, one-half-clock-cycle data transfers  
at the I/O pins.  
The DDR SDRAM provides for programmable Read or Write  
burst lengths of 2, 4 or 8 locations. An Auto Precharge  
function may be enabled to provide a self-timed row  
precharge that is initiated at the end of the burst access.  
A bidirectional data strobe (DQS) is transmitted externally,  
along with data, for use in data capture at the receiver. DQS  
is a strobe transmitted by the DDR SDRAM during Reads and  
by the memory controller during Writes. DQS is edge-aligned  
with data for Reads and center-aligned with data for Writes.  
As with standard SDRAMs, the pipelined, multibank  
architecture of DDR SDRAMs allows for concurrent  
operation, thereby providing high effective bandwidth by  
hiding row precharge and activation time.  
An auto refresh mode is provided along with a power-saving  
power-down mode. All inputs are compatible with the Industry  
Standard for SSTL_2. All outputs are SSTL_2, Class II  
compatible.  
The 512-Mbit Double-Data-Rate SDRAM operates from a  
differential clock (CK and CK; the crossing of CK going HIGH  
and CK going LOW is referred to as the positive edge of CK).  
Commands (address and control signals) are registered at  
every positive edge of CK. Input data is registered on both  
edges of DQS, and output data is referenced to both edges of  
DQS, as well as to both edges of CK.  
Note: The functionality described and the timing  
specifications included in this data sheet are for the  
DLL Enabled mode of operation.  
TABLE 2  
Ordering Information for non RoHS Compliant Products  
Part Number1)  
Org. CAS-RCD-RP  
Latencies  
Clock  
(MHz)  
CAS-RCD-RP Clock  
Speed  
Package  
Latencies  
(MHz)  
HYI25D512160CC-5  
HYI25D512160CT-5  
HYI25D512160CC-6  
HYI25D512160CT-6  
×16 3.0-3-3  
200  
2.5-3-3  
166  
DDR400B  
DDR333  
P-TFBGA-60  
P-TSOPII-66  
P-TFBGA-60  
P-TSOPII-66  
2.5-3-3  
166  
2.0-3-3  
133  
1) HYI: designator for memory components  
25D : DDR SDRAMs at VDDQ = 2.5 V  
512: 512-Mbit density  
160: Product variation x16  
C: Die revision C  
C/F/E/T: Package type FBGA and TSOP  
Rev. 1.0, 2006-11  
4
11082006-S9OT-UFSN  
Internet Data Sheet  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
TABLE 3  
Ordering Information for RoHS Compliant Products  
Part Number  
Org. CAS-RCD-RP Clock  
CAS-RCD-RP Clock Speed  
Package  
Note  
Latencies  
(MHz)  
Latencies  
(MHz)  
1)  
HYI25D512160CE-5 ×16 3.0-3-3  
200  
2.5-3-3  
166  
DDR400B PG-TSOPII-66  
PG-TFBGA-60  
HYI25D512160CF-5  
HYI25D512160CE-6  
HYI25D512160CF-6  
2.5-3-3  
166  
2.0-3-3  
133  
DDR333 PG-TSOPII-66  
PG-TFBGA-60  
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined  
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,  
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.  
Rev. 1.0, 2006-11  
5
11082006-S9OT-UFSN  
Internet Data Sheet  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
2
Chip Configuration  
The pin configuration of a DDR SDRAM is listed by function in Table 4 (60 pins). The abbreviations used in the Pin#/Buffer#  
column are explained in Table 5 and Table 6 respectively. The pin numbering for FBGA is depicted in Figure 1 and that of the  
TSOP package in Figure 2.  
TABLE 4  
Ball Configuration of DDR SDRAM  
Ball#/Pin#  
Name  
Pin  
Type  
Buffer  
Type  
Function  
Clock Signals  
G2, 45  
CK1  
CK1  
CKE  
I
I
I
SSTL  
SSTL  
SSTL  
Clock Signal  
G3, 46  
Complementary Clock Signal  
Clock Enable  
H3, 44  
Control Signals  
H7, 23  
RAS  
CAS  
WE  
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
Row Address Strobe  
Column Address Strobe  
Write Enable  
G8, 22  
G7, 21  
H8, 24  
CS  
Chip Select  
Address Signals  
J8, 26  
J7, 27  
K7, 29  
L8, 30  
L7, 31  
M8, 32  
M2, 35  
L3, 36  
L2, 37  
K3, 38  
K2, 39  
J3, 40  
K8, 28  
BA0  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Bank Address Bus 2:0  
Address Bus 11:0  
BA1  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
A10  
AP  
A11  
A12  
J2, 41  
H2, 42  
Address Signal 12  
Note: Module based on 256 Mbit or larger dies  
Note: Module based on 128 Mbit or smaller dies  
NC  
NC  
Rev. 1.0, 2006-11  
6
11082006-S9OT-UFSN  
Internet Data Sheet  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
Ball#/Pin#  
Name  
A13  
Pin  
Type  
Buffer  
Type  
Function  
F9, 17  
I
SSTL  
Address Signal 13  
Note: 1 Gbit based module  
NC  
NC  
Note: Module based on 512 Mbit or smaller dies  
Data Signals ×4 organization  
B7, 5  
DQ0  
DQ1  
DQ2  
DQ3  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
Data Signal Bus 3:0  
D7, 11  
D3, 56  
B3, 62  
Data Strobe ×4 organisation  
E3, 51  
Data Mask ×4 organization  
F3, 47 DM  
DQS  
I/O  
I
SSTL  
SSTL  
Data Strobe  
Data Mask  
Data Signals ×8 organization  
A8, 2  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Signal Bus 7:0  
B7, 5  
C7, 8  
D7, 11  
D3, 56  
C3, 59  
B3, 62  
A2, 65  
Data Strobe ×8 organisation  
E3, 51  
Data Mask ×8 organization  
F3, 47 DM  
DQS  
I/O  
I
SSTL  
SSTL  
Data Strobe  
Data Mask  
Rev. 1.0, 2006-11  
7
11082006-S9OT-UFSN  
Internet Data Sheet  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
Ball#/Pin#  
Name  
Pin  
Type  
Buffer  
Type  
Function  
Data Signals ×16 organization  
A8, 2  
DQ0  
DQ1  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Signal 15:0  
B9, 4  
B7, 5  
DQ2  
C9, 7  
DQ3  
C7, 8  
DQ4  
D9, 10  
D7, 11  
E9, 13  
E1, 54  
D3, 56  
D1, 57  
C3, 59  
C1, 60  
B3, 62  
B1, 63  
A2, 65  
DQ5  
DQ6  
DQ7  
DQ8  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
Data Strobe ×16 organization  
E3, 51  
E7, 16  
UDQS  
LDQS  
I/O  
I/O  
SSTL  
SSTL  
Data Strobe Upper Byte  
Data Strobe Lower Byte  
Data Mask ×16 organization  
F3, 47  
UDM  
LDM  
I
I
SSTL  
SSTL  
Data Mask Upper Byte  
Data Mask Lower Byte  
F7, 20  
Power Supplies  
F1, 49  
VREF  
AI  
I/O Reference Voltage  
A9, B2, C8, D2, VDDQ  
E8, 3, 9, 15, 55,  
61  
PWR  
I/O Driver Power Supply  
A7, F8, M7, 1, VDD  
18, 33  
PWR  
PWR  
Power Supply  
Power Supply  
A1, B8, C2, D8, VSSQ  
E2, 6, 12, 52,  
58, 64  
A3, F2, M3, 34 VSS  
PWR  
NC  
Power Supply  
Not Connected  
A2, 65  
NC  
NC  
NC  
Not Connected  
Note: ×4 organization  
Not Connected  
A8, 2  
NC  
Note: ×4 organization  
Not Connected  
B1, 63  
NC  
Note: ×8 and ×4 organisation  
Rev. 1.0, 2006-11  
8
11082006-S9OT-UFSN  
Internet Data Sheet  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
Ball#/Pin#  
B9, 4  
Name  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
Pin  
Type  
Buffer  
Type  
Function  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
Not Connected  
Note: ×8 and ×4 organization  
Not Connected  
C1, 60  
C3, 59  
C7, 8  
Note: ×8 and ×4 organization  
Not Connected  
Note: ×4 organization  
Not Connected  
Note: ×4 organization  
Not Connected  
C9, 7  
Note: ×8 and ×4 organization  
Not Connected  
D1, 57  
D9, 10  
E1, 54  
E7, 16  
E9, 13  
F7, 20  
Note: ×8 and ×4 organization  
Not Connected  
Note: ×8 and ×4 organization  
Not Connected  
Note: ×8 and ×4 organization  
Not Connected  
Note: ×8 and ×4 organization  
Not Connected  
Note: ×8 and ×4 organization  
Not Connected  
Note: ×8 and ×4 organization  
Not Connected  
14, 17, 19, 25, NC  
43, 50  
Note: ×16,×8 and ×4 organization  
TABLE 5  
Abbreviations for Pin Type  
Abbreviation  
Description  
I
Standard input-only pin. Digital levels.  
Output. Digital levels.  
O
I/O  
AI  
I/O is a bidirectional input/output signal.  
Input. Analog levels.  
PWR  
GND  
NC  
Power  
Ground  
Not Connected (JEDEC Standard)  
Rev. 1.0, 2006-11  
9
11082006-S9OT-UFSN  
Internet Data Sheet  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
TABLE 6  
Abbreviations for Buffer Type  
Abbreviation  
Description  
SSTL  
Serial Stub Terminalted Logic (SSTL2)  
Low Voltage CMOS  
LV-CMOS  
CMOS  
OD  
CMOS Levels  
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and  
allows multiple devices to share as a wire-OR.  
Rev. 1.0, 2006-11  
10  
11082006-S9OT-UFSN  
                                
                                                                     
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Internet Data Sheet  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
FIGURE 1  
Pin Configuration P(G)-TFBGA-60 Top View, see the balls throught the package  
ꢅꢀꢀ  
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Rev. 1.0, 2006-11  
11082006-S9OT-UFSN  
11  
                                                      
                                                       
                                                      
                                                       
                                                        
9''  
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ꢊꢆꢀ  
                                                                                                                  
ꢁꢁ  
Internet Data Sheet  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
FIGURE 2  
Pin Configuration P(G)-TSOPII-66  
                                                      
[ꢀ  
[ꢀ  
[ꢀ  
                                                       
ꢈꢀ  
ꢇꢀ  
ꢀꢀꢀ  
ꢅꢂꢀ  
Rev. 1.0, 2006-11  
11082006-S9OT-UFSN  
12  
Internet Data Sheet  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
3
Functional Description  
The 512-Mbit Double-Data-Rate SDRAM is a high-speed  
CMOS, dynamic random-access memory containing  
536,870,912 bits. The 512-Mbit Double-Data-Rate SDRAM  
is internally configured as a quad-bank DRAM.  
Read and write accesses to the DDR SDRAM are burst  
oriented; accesses start at a selected location and continue  
for a programmed number of locations in a programmed  
sequence. Accesses begin with the registration of an Active  
command, which is then followed by a Read or Write  
command. The address bits registered coincident with the  
Active command are used to select the bank and row to be  
accessed (BA0, BA1 select the bank; A0-A12 select the row).  
The address bits registered coincident with the Read or Write  
command are used to select the starting column location for  
the burst access.  
The 512-Mbit Double-Data-Rate SDRAM uses a double-  
data-rate architecture to achieve high-speed operation. The  
double-data-rate architecture is essentially a 2n prefetch  
architecture, with an interface designed to transfer two data  
words per clock cycle at the I/O pins. A single read or write  
access for the 512-Mbit Double-Data-Rate SDRAM consists  
of a single 2n-bit wide, one clock cycle data transfer at the  
internal DRAM core and two corresponding n-bit wide, one-  
half clock cycle data transfers at the I/O pins.  
Prior to normal operation, the DDR SDRAM must be  
initialized. The following sections provide detailed information  
covering device initialization, register definition, command  
descriptions and device operation.  
Rev. 1.0, 2006-11  
13  
11082006-S9OT-UFSN  
Internet Data Sheet  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
"!ꢃ  
"!ꢀ  
!ꢃꢄ  
!ꢃꢃ  
!ꢃꢀ  
!ꢅ  
!ꢂ  
!ꢆ  
!ꢇ  
!ꢈ  
#,  
W
!ꢁ  
!ꢉ  
"4  
W
!ꢄ  
!ꢃ  
",  
W
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/PERATING -/$%  
W
REGꢊ ADDR  
-0"4ꢀꢁꢂꢀ  
TABLE 7  
Mode Register Definition  
Field Bits  
Type1) Description  
Burst Length  
BL  
[2:0]  
w
Number of sequential bits per DQ related to one read/write command.  
Note: All other bit combinations are RESERVED.  
001B  
010B  
011B  
2
4
8
BT  
CL  
3
Burst Type  
See Table 8 for internal address sequence of low order address bits.  
0B  
1B  
Sequential  
Interleaved  
[6:4]  
CAS Latency  
Number of full clocks from read command to first data valid window.  
Note: All other bit combinations are RESERVED.  
010B  
011B  
2
3
110B 2.5  
MODE [12:7]  
Operating Mode  
Note: All other bit combinations are RESERVED.  
000000B Normal Operation without DLL Reset  
000010B Normal DLL Reset  
1) w = write only register bit  
Rev. 1.0, 2006-11  
14  
11082006-S9OT-UFSN  
Internet Data Sheet  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
TABLE 8  
Burst Definition  
Burst Length  
Starting Column Address  
Order of Accesses Within a Burst  
A2  
A1  
A0  
Type = Sequential  
Type = Interleaved  
2
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0-1  
0-1  
1-0  
1-0  
0
0
1
1
0
0
1
1
0
0
1
1
0-1-2-3  
0-1-2-3  
1-2-3-0  
1-0-3-2  
2-3-0-1  
2-3-0-1  
3-0-1-2  
3-2-1-0  
8
0
0-1-2-3-4-5-6-7  
1-2-3-4-5-6-7-0  
2-3-4-5-6-7-0-1  
3-4-5-6-7-0-1-2  
4-5-6-7-0-1-2-3  
5-6-7-0-1-2-3-4  
6-7-0-1-2-3-4-5  
7-0-1-2-3-4-5-6  
0-1-2-3-4-5-6-7  
1-0-3-2-5-4-7-6  
2-3-0-1-6-7-4-5  
3-2-1-0-7-6-5-4  
4-5-6-7-0-1-2-3  
5-4-7-6-1-0-3-2  
6-7-4-5-2-3-0-1  
7-6-5-4-3-2-1-0  
0
0
0
1
1
1
1
Notes  
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.  
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block.  
3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within the block.  
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.  
Rev. 1.0, 2006-11  
15  
11082006-S9OT-UFSN  
Internet Data Sheet  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
"!ꢃ  
"!ꢀ  
!ꢃꢄ  
!ꢃꢃ  
!ꢃꢀ  
!ꢅ  
!ꢂ  
!ꢆ  
!ꢇ  
!ꢈ  
!ꢁ  
!ꢉ  
!ꢄ  
!ꢃ  
$3  
W
!ꢀ  
$,,  
W
/PERATING -/$%  
W
REGꢊ ADDR  
W
-0"4ꢀꢁꢅꢀ  
TABLE 9  
Extended Mode Register  
Field  
Bits  
Type1)  
Description  
DLL Status  
DLL  
0
w
0B  
1B  
Enabled  
Disabled  
DS  
1
Drive Strength  
0B  
1B  
Normal  
Weak  
MODE  
[12:3]  
Operating Mode  
00000000000 B Normal Operation  
Notes  
1. A2 must be 0 to provide compatibility with early DDR devices  
2. All other bit combinations are RESERVED  
1) w = write only register bit  
Rev. 1.0, 2006-11  
16  
11082006-S9OT-UFSN  
Internet Data Sheet  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
TABLE 10  
Truth Table 1a: Commands  
Name (Function)  
CS RAS CAS WE Address  
MNE  
Note  
1)2)  
Deselect (NOP)  
H
L
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
X
X
NOP  
NOP  
1)2)  
No Operation (NOP)  
1)3)  
Active (Select Bank And Activate Row)  
Read (Select Bank And Column, And Start Read Burst)  
Write (Select Bank And Column, And Start Write Burst)  
Burst Terminate  
Bank/Row ACT  
1)4)  
H
H
H
L
Bank/Col  
Bank/Col  
X
Read  
Write  
BST  
1)4)  
L
1)5)  
H
H
L
L
1)6)  
Precharge (Deactivate Row In Bank Or Banks)  
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)  
Mode Register Set  
L
Code  
PRE  
1)7)8)  
1)9)  
L
H
L
X
AR/SR  
MRS  
L
L
Op-Code  
1) CKE is HIGH for all commands shown exceptSelf Refresh. VREF must be maintained during Self Refresh operation.  
2) Deselect and NOP are functionally interchangeable.  
3) BA0-BA1 provide bank address and A0-A12 provide row address.  
4) BA0, BA1 provide bank address; A0-Ai provide column address (where i = 8 for x16, i = 9 for x8 and 9, 11 for x4); A10 HIGH enables the  
Auto Precharge feature (nonpersistent), A10 LOW disables the Auto Precharge feature.  
5) Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto  
Precharge enabled or for write bursts.  
6) A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.  
7) This command is AUTO REFRESH if CKE is HIGH; Self Refresh if CKE is LOW.  
8) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.  
9) BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects  
Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode  
Register).  
TABLE 11  
Truth Table 1b: DM Operation  
Name (Function)  
DM  
DQs  
Note  
1)  
Write Enable  
L
Valid  
X
1)  
Write Inhibit  
H
1) Used to mask write data; provided coincident with the corresponding data.  
Rev. 1.0, 2006-11  
17  
11082006-S9OT-UFSN  
Internet Data Sheet  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
TABLE 12  
Truth Table 2: Clock Enable (CKE)  
Current State CKE n-1  
CKEn  
Command n  
Action n  
Note  
Previous Current  
Cycle  
Cycle  
1)  
2)  
Self Refresh  
Self Refresh  
Power Down  
Power Down  
All Banks Idle  
All Banks Idle  
Bank(s) Active  
L
L
X
Maintain Self-Refresh  
Exit Self-Refresh  
L
H
L
Deselect or NOP  
X
L
Maintain Power-Down  
Exit Power-Down  
L
H
L
Deselect or NOP  
Deselect or NOP  
AUTO REFRESH  
Deselect or NOP  
See Table 13  
H
H
H
H
Precharge Power-Down Entry  
Self Refresh Entry  
Active Power-Down Entry  
L
L
H
1) VREF must be maintained during Self Refresh operation  
2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (VXSNR) period. A minimum of  
200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.  
Notes  
1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.  
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.  
3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.  
4. All states and sequences not shown are illegal or reserved.  
TABLE 13  
Truth Table 3: Current State Bank n - Command to Bank n (same bank)  
Current State CS  
RAS CAS WE  
Command  
Action  
Note  
1)2)3)4)5)6)  
1) to 6)  
Any  
H
L
L
L
L
X
H
L
L
L
X
H
H
L
X
H
H
H
L
Deselect  
NOP. Continue previous operation.  
No Operation  
Active  
NOP. Continue previous operation.  
1) to 6)  
Idle  
Select and activate row  
1) to 7)  
AUTO REFRESH  
1) to 7)  
L
MODE REGISTER  
SET  
1) to 6), 8)  
1) to 6), 8)  
1) to 6), 9)  
1) to 6), 8)  
1) to 6), 9)  
1) to 6), 10)  
Row Active  
L
L
L
L
L
L
H
H
L
L
H
L
Read  
Select column and start Read burst  
Select column and start Write burst  
Deactivate row in bank(s)  
L
Write  
H
L
L
Precharge  
Read  
Read (Auto  
Precharge  
Disabled)  
H
L
H
L
Select column and start new Read burst  
Truncate Read burst, start Precharge  
BURST TERMINATE  
H
H
Precharge  
H
L
BURST  
TERMINATE  
1) to 6), 8), 11)  
1) to 6), 8)  
Write (Auto  
Precharge  
Disabled)  
L
L
L
H
H
L
L
L
H
H
L
Read  
Select column and start Read burst  
Select column and start Write burst  
Truncate Write burst, start Precharge  
Write  
1) to 6), 9), 10)  
L
Precharge  
Rev. 1.0, 2006-11  
11082006-S9OT-UFSN  
18  
Internet Data Sheet  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 12 and after tXSNR/tXSRD has been met (if the previous state  
was self refresh).  
2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed  
to be issued to that bank when in that state. Exceptions are covered in the notes below.  
3) Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated,  
and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with  
Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge  
disabled, and has not yet terminated or been terminated.  
4) The following states must not be interrupted by a command issued to the same bank. Precharging: Starts with registration of a Precharge  
command and ends when tRP is met. Once tRP is met, the bank is in the idle state. Row Activating: Starts with registration of an Active  
command and ends when tRCD is met. Once tRCD is met, the bank is in the “row active” state. Read w/Auto Precharge Enabled: Starts with  
registration of a Read command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle  
state. Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has  
been met. Once tRP is met, the bank is in the idle state. Deselect or NOP commands, or allowable commands to the other bank should be  
issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and  
according to Table 14.  
5) The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive  
clock edge during these states. Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is  
met, the DDR SDRAM is in the “all banks idle” state. Accessing Mode Register: Starts with registration of a Mode Register Set command  
and ends when tMRD has been met. Once tMRD is met, the DDR SDRAM is in the “all banks idle” state. Precharging All: Starts with  
registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle state.  
6) All states and sequences not shown are illegal or reserved.  
7) Not bank-specific; requires that all banks are idle.  
8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with  
Auto Precharge disabled.  
9) May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.  
10) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.  
11) Requires appropriate DM masking.  
TABLE 14  
Truth Table 4: Current State Bank n - Command to Bank m  
Current State  
CS  
RAS CAS WE Command  
Action  
Note  
1)2)3)4)5)6)  
Any  
H
L
X
H
X
X
H
X
X
H
X
Deselect  
NOP. Continue previous operation.  
1) to 6)  
1) to 6)  
No Operation  
NOP. Continue previous operation.  
Idle  
X
Any Command  
Otherwise Allowed to  
Bank m  
1) to 6)  
1) to 7)  
1) to 7)  
1) to 6)  
1) to 6)  
1) to 7)  
1) to 6)  
1) to 6)  
1) to 8)  
1) to 7)  
1) to 6)  
Row Activating,  
Active, or  
Precharging  
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
H
L
Active  
Select and activate row  
Select column and start Read burst  
Select column and start Write burst  
H
H
L
Read  
L
Write  
H
H
L
L
Precharge  
Active  
Read (Auto  
Precharge  
Disabled)  
L
H
H
L
Select and activate row  
Select column and start new Read burst  
H
L
Read  
H
H
L
Precharge  
Active  
Write (Auto  
Precharge  
Disabled)  
L
H
H
L
Select and activate row  
Select column and start Read burst  
Select column and start new Write burst  
H
H
L
Read  
L
Write  
H
L
Precharge  
Rev. 1.0, 2006-11  
19  
11082006-S9OT-UFSN  
Internet Data Sheet  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
Current State  
CS  
RAS CAS WE Command  
Action  
Note  
1) to 6)  
Read (With Auto  
Precharge)  
L
L
L
L
L
L
L
L
L
H
L
H
H
L
Active  
Select and activate row  
Select column and start new Read burst  
Select column and start Write burst  
1) to 7), 9)  
1) to 7), 9), 10)  
1) to 6)  
H
H
L
Read  
L
Write  
H
H
L
L
Precharge  
Active  
1) to 6)  
Write (With Auto  
Precharge)  
L
H
H
L
Select and activate row  
Select column and start Read burst  
Select column and start new Write burst  
1) to 7), 9)  
1) to 7), 9)  
1) to 6)  
H
H
L
Read  
L
Write  
H
L
Precharge  
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 12: Clock Enable (CKE) and after tXSNR/tXSRD has been met (if  
the previous state was self refresh).  
2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those  
allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in  
the notes below.  
3) Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated,  
and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with  
Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge  
disabled, and has not yet terminated or been terminated. Read with Auto Precharge Enabled: See 10). Write with Auto Precharge Enabled:  
See 10)  
.
4) AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle.  
5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.  
6) All states and sequences not shown are illegal or reserved.  
7) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with  
Auto Precharge disabled.  
8) Requires appropriate DM masking.  
9) Concurrent Auto Precharge: This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto  
precharge is enabled any command may follow to the other banks as long as that command does not interrupt the read or write data  
transfer and all other limitations apply (e.g. contention between READ data and WRITE data must be avoided). The minimum delay from  
a read or write command with auto precharge enable, to a command to a different banks is summarized in Table 15.  
10) A Write command may be applied after the completion of data output.  
TABLE 15  
Truth Table 5: Concurrent Auto Precharge  
From Command  
To Command (different bank)  
Minimum Delay with Concurrent Auto Unit  
Precharge Support  
WRITE w/AP  
Read or Read w/AP  
Write to Write w/AP  
Precharge or Activate  
Read or Read w/AP  
Write or Write w/AP  
Precharge or Activate  
1 + (BL/2) + tWTR  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
BL/2  
1
Read w/AP  
BL/2  
CL (rounded up) + BL/2  
1
Rev. 1.0, 2006-11  
20  
11082006-S9OT-UFSN  
Internet Data Sheet  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
4
Electrical Characteristics  
This chapter describes the electrical characteristics.  
4.1  
Operating Conditions  
This chapter contains the operating conditions.  
TABLE 16  
Absolute Maximum Ratings  
Parameter  
Symbol  
Values  
Unit Note/ Test  
Condition  
Min.  
Typ. Max.  
Voltage on I/O pins relative to VSS  
Voltage on inputs relative to VSS  
Voltage on VDD supply relative to VSS  
Voltage on VDDQ supply relative to VSS  
Operating temperature (ambient)  
Storage temperature (plastic)  
VIN, VOUT  
VIN  
–0.5  
–1  
1
V
DDQ + 0.5  
V
+3.6  
+3.6  
+3.6  
+85  
+150  
V
VDD  
–1  
V
VDDQ  
TA  
–1  
V
–40  
–55  
°C  
°C  
W
mA  
TSTG  
PD  
Power dissipation (per SDRAM component)  
Short circuit output current  
IOUT  
50  
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to  
absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings  
are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated  
circuit.  
Rev. 1.0, 2006-11  
21  
11082006-S9OT-UFSN  
Internet Data Sheet  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
TABLE 17  
Input and Output Capacitances  
Parameter  
Symbol  
Values  
Typ.  
Unit  
Note/  
Test Condition  
Min.  
Max.  
Input Capacitance: CK, CK  
CI1  
2.0  
1.5  
3.0  
2.5  
0.25  
2.5  
3.0  
0.5  
pF  
pF  
pF  
pF  
pF  
pF  
TSOPII1)  
TFBGA 1)  
1)  
Delta Input Capacitance  
CdI1  
CI2  
Input Capacitance: All other input-only pins  
1.5  
2.0  
TFBGA 1)  
TSOPII 1)  
1)  
Delta Input Capacitance: All other input-only CdIO  
pins  
Input/Output Capacitance: DQ, DQS, DM  
CIO  
3.5  
4.0  
4.5  
5.0  
0.5  
pF  
pF  
pF  
TFBGA 1)2)  
TSOPII 1)2)  
1)  
Delta Input/Output Capacitance: DQ, DQS,  
DM  
CdIO  
1) These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5 V ± 0.2 V, f = 100 MHz, TA = 25 °C,  
OUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.  
V
2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the  
board level.  
Rev. 1.0, 2006-11  
22  
11082006-S9OT-UFSN  
Internet Data Sheet  
HYI25D512160C[C/E/F/T]  
512-Mbit Double-Data-Rate SDRAM  
TABLE 18  
Electrical Characteristics and DC Operating Conditions  
Parameter  
Symbol  
Values  
Unit Note1)/ Test Condition  
Min.  
Typ.  
Max.  
Device Supply Voltage  
Device Supply Voltage  
Output Supply Voltage  
Output Supply Voltage  
VDD  
2.3  
2.5  
2.3  
2.5  
0
2.5  
2.6  
2.5  
2.6  
2.7  
2.7  
2.7  
2.7  
0
V
V
V
V
V
fCK 166 MHz  
f
CK > 166 MHz 2)  
fCK 166 MHz 3)  
fCK > 166 MHz 2)3)  
VDD  
VDDQ  
VDDQ  
Supply Voltage, I/O Supply VSS, VSSQ  
Voltage  
4)  
5)  
Input Reference Voltage  
VREF  
VTT  
0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ  
V
V
I/O Termination Voltage  
(System)  
VREF – 0.04  
VREF + 0.04  
6)  
6)  
6)  
Input High (Logic1) Voltage VIH(DC)  
Input Low (Logic0) Voltage VIL(DC)  
VREF + 0.15  
–0.3  
VDDQ + 0.3  
VREF – 0.15  
VDDQ + 0.3  
V
V
V
Input Voltage Level, CK and VIN(DC)  
–0.3  
CK Inputs  
6)7)  
8)  
Input Differential Voltage,  
CK and CK Inputs  
VID(DC)  
0.36  
0.71  
–2  
VDDQ + 0.6  
V
VI-Matching Pull-up Current VIRatio  
to Pull-down Current  
1.4  
2
µA  
µA  
Input Leakage Current  
Output Leakage Current  
II  
Any input 0 V VIN VDD; All  
other pins not under test = 0 V9)  
IOZ  
–5  
5
DQs are disabled; 0 V VOUT  
VDDQ  
9)  
Output High Current, Normal IOH  
Strength Driver  
–16.2  
mA VOUT = 1.95 V  
mA VOUT = 0.35 V  
Output Low Current, Normal IOL  
16.2  
Strength Driver  
1) -40 °C TA