R
XC5200 Series Field Programmable Gate Arrays
XC3000 family: XC5200 devices support an additional pro-
gramming mode: Peripheral Synchronous.
Input/Output Blocks (IOBs)
XC3000 family: The XC5200 family does not support
Power-down, but offers a Global 3-state input that does not
reset any flip-flops.
VersaRing
XC3000 family: The XC5200 family does not provide an
on-chip crystal oscillator amplifier, but it does provide an
internal oscillator from which a variety of frequencies up to
12 MHz are available.
GRM
GRM
GRM
Versa-
Block
Versa-
Block
Versa-
Block
GRM
GRM
GRM
Architectural Overview
Versa-
Block
Versa-
Block
Versa-
Block
Figure 1 presents a simplified, conceptual overview of the
XC5200 architecture. Similar to conventional FPGAs, the
XC5200 family consists of programmable IOBs, program-
mable logic blocks, and programmable interconnect. Unlike
other FPGAs, however, the logic and local routing
resources of the XC5200 family are combined in flexible
VersaBlocks (Figure 2). General-purpose routing connects
to the VersaBlock through the General Routing Matrix
(GRM).
GRM
GRM
GRM
Versa-
Block
Versa-
Block
Versa-
Block
VersaRing
X4955
Figure 1: XC5200 Architectural Overview
VersaBlock: Abundant Local Routing Plus
Versatile Logic
GRM
4
4
The basic logic element in each VersaBlock structure is the
Logic Cell, shown in Figure 3. Each LC contains a 4-input
function generator (F), a storage device (FD), and control
logic. There are five independent inputs and three outputs
to each LC. The independence of the inputs and outputs
allows the software to maximize the resource utilization
within each LC. Each Logic Cell also contains a direct
feedthrough path that does not sacrifice the use of either
the function generator or the register; this feature is a first
for FPGAs. The storage device is configurable as either a D
flip-flop or a latch. The control logic consists of carry logic
for fast implementation of arithmetic functions, which can
also be configured as a cascade chain allowing decode of
very wide input functions.
24
24
7
TS
CLB
LC3
4
LC2
LC1
LC0
4
4
4
4
LIM
4
4
Direct Connects
X5707
Figure 2: VersaBlock
CO
DO
DI
D
Q
F4
F3
FD
F
F2
F1
X
CI
CE CK
CLR
X4956
Figure 3: XC5200 Logic Cell (Four LCs per CLB)
November 5, 1998 (Version 5.2)
7-85
ETC [ ETC ]
