Continuous Integration Timing
T
INT
'
T
INT
SYSTEM
CLOCK
t
1
FDS In
Internal
Oversampling
Interval
Internal
Reset
DATA VALID
Out
FDS In should be coincident with negative clock.
t
2
FDS initiates oversampling period.
M Clock Periods
End of oversample period
initiates reset for next integration.
M Clock Periods
Next integration begins when 1 clock
period wide Internal Reset ends.
Non-Continuous Integration Timing
SYSTEM
CLOCK
FDS In should be coincident with negative clock.
FDS In
Internal
Oversampling
Interval
Internal
Reset
DATA VALID Out
t
3
FDS initiates oversampling period.
End of oversample
period initiates
reset.
t
4
End of FDS In
initiates end of Internal Reset.
When Internal Reset period ends,
next integration begins.
FIGURE 4. Conversion Timing Diagrams.
RESET SETUP In
t
5
DATA CLOCK
(4MHz, max for setup)
t
6
SETUP In
Read
t
7
Read
Read
Input
Range
Read
Output
Format
ACQ
MSB
ACQ
LSB
FIGURE 5. Input/Output Timing Diagram—SETUP Timing Diagram.
SYSTEM
CLOCK
t
8
DATA VALID
Out
DATA TRANSMIT
In
t
9
t
17
t
10
DATA TRANSMIT In resets DATA VALID Out.
Data can be read on rising or falling edge of Data Clock
DATA CLOCK
(8MHz, max for data)
t
11
DATA OUTPUT
Output Disabled
DDC(1)
Bit 1, MSB
Output Enabled
Last DDC
Bit 21
t
12
DDC(n)
Bit 21, LSB
DDC
(n+1)
Bit 1
t
13
Output Disabled
FIGURE 6. DATA TRANSMIT Timing Diagram.
®
DDC101
8
ETC [ ETC ]
