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DSP56311VF150 参数 Datasheet PDF下载

DSP56311VF150图片预览
型号: DSP56311VF150
PDF下载: 下载PDF文件 查看货源
内容描述: [DSP|24-BIT|CMOS|BGA|196PIN|PLASTIC ]
分类和应用: 外围集成电路时钟
文件页数/大小: 96 页 / 1892 K
品牌: ETC [ ETC ]
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Technical Data
DSP56311/D
Rev. 2, 1/2002
24-Bit Digital Signal
Processor
3
16
6
6
Memory Expansion Area
Program
RAM
32 K
×
24 bits
or
31 K
×
24 bits
and
Instruction
Cache
1024
×
24 bits
PM_EB
SCI
Triple
Timer
HI08
ESSI
EFCOP
X Data
RAM
48 K
×
24 bits
Y Data
RAM
48 K
×
24 bits
The DSP56311 is
intended for
applications requiring
a large amount of
on-chip memory, such
as networking and
wireless infrastructure
applications. The
EFCOP can accelerate
general filtering
applications, such as
echo-cancellation
applications,
correlation, and
general-purpose
convolution-based
algorithms.
PIO_EB
XM_EB
Address
Generation
Unit
Six Channel
DMA Unit
Bootstrap
ROM
YAB
XAB
PAB
DAB
YM_EB
Peripheral
Expansion Area
External
Address
Bus
Switch
External
Bus
Interface
and
I - Cache
Control
External
Data
Bus
Switch
Power
Management
JTAG
OnCE™
18
Address
24-Bit
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
13
Control
Internal
Data
Bus
Switch
24
Data
Clock
PLL
Generator
EXTAL
XTAL
RESET
PINIT/NMI
Program
Interrupt
Controller
Program
Decode
Controller
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Program
Address
Generator
Data ALU
24
×
24 + 56
56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
5
DE
PCAP
Figure 1.
DSP56311 Block Diagram
The Motorola DSP56311, a member of the
DSP56300 Digital Signal Processor (DSP) family,
supports network applications with general
filtering operations. The Enhanced Filter
Coprocessor (EFCOP) executes filter algorithms in
parallel with core operations enhancing signal
quality with no impact on channel throughput or
total channels supported. The result is increased
overall performance. Like the other DSP56300
family members, the DSP56311 uses a
high-performance, single-clock-cycle-per-
instruction engine (DSP56000 code-compatible), a
barrel shifter, 24-bit addressing, an instruction
cache, and a direct memory access (DMA)
controller (see
The DSP56311 performs
at 150 million instructions per second (MIPS),
attaining 270 MIPS when the EFCOP is in use. It
operates with an internal 150 MHz clock with a
1.8 volt core and independent 3.3 volt input/output
(I/O) power.