欢迎访问ic37.com |
会员登录 免费注册
发布采购

24FC512T-I/SM 参数 Datasheet PDF下载

24FC512T-I/SM图片预览
型号: 24FC512T-I/SM
PDF下载: 下载PDF文件 查看货源
内容描述: EEPROM\n [EEPROM ]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 22 页 / 274 K
品牌: ETC [ ETC ]
 浏览型号24FC512T-I/SM的Datasheet PDF文件第2页浏览型号24FC512T-I/SM的Datasheet PDF文件第3页浏览型号24FC512T-I/SM的Datasheet PDF文件第4页浏览型号24FC512T-I/SM的Datasheet PDF文件第5页浏览型号24FC512T-I/SM的Datasheet PDF文件第6页浏览型号24FC512T-I/SM的Datasheet PDF文件第7页浏览型号24FC512T-I/SM的Datasheet PDF文件第8页浏览型号24FC512T-I/SM的Datasheet PDF文件第9页  
24AA515/24LC515/24FC515
512K I
2
C
CMOS Serial EEPROM
Device Selection Table
Part
Number
24AA515
24LC515
24FC515
Package Type
Temp
Ranges
I
I
I
PDIP
A0
A1
A2
V
SS
1
8
V
CC
WP
SCL
SDA
V
CC
Range
1.8-5.5V
2.5-5.5V
2.5-5.5V
Max Clock
Frequency
400 kHz
400 kHz
1 MHz
24AA515/
2
3
4
7
6
5
100 kHz for V
CC
< 2.5V.
SOIC
A0
A1
A2
V
SS
1
8
V
CC
WP
SCL
SDA
Features
• Low-power CMOS technology
- Maximum write current 3 mA at 5.5V
- Maximum read current 400
µA
at 5.5V
- Standby current 100 nA typical at 5.5V
• 2-wire serial interface bus, I
2
C
compatible
• Cascadable for up to four devices
• Self-timed ERASE/WRITE cycle
• 64-byte Page Write mode available
• 5 ms max write cycle time
• Hardware write-protect for entire array
• Output slope control to eliminate ground bounce
• Schmitt Trigger inputs for noise suppression
• 100,000 erase/write cycles
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP, SOIC packages
• Temperature ranges:
- Industrial (I):
-40°C to +85°C
24AA515/
2
3
4
7
6
5
Block Diagram
A0 A1
WP
HV Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
Page Latches
I/O
SCL
YDEC
Description
The Microchip Technology Inc. 24AA515/24LC515/
24FC515 (24XX515*) is a 64K x 8 (512K bit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.8V to 5.5V). It has
been developed for advanced, low power applications
such as personal communications or data acquisition.
This device has both byte write and page write capabil-
ity of up to 64 bytes of data. This device is capable of
both random and sequential reads. Reads may be
sequential within address boundaries 0000h to 7FFFh
& 8000h to FFFFh. Functional address lines allow up to
four devices on the same data bus. This allows for up
to 2 Mbits total system EEPROM memory. This device
is available in the standard 8-pin plastic DIP and SOIC
packages.
SDA
V
CC
V
SS
Sense AMP
R/W Control
24XX515 is used in this document as a generic part number
for the 24AA515/24LC515/24FC515 devices.
2003 Microchip Technology Inc.
Preliminary
DS21673C-page 1