ADM7008
5.3.2 REFCLK Output Timing (When REFCLK_SEL is set to 0)
Electrical Specification
t_OUT50_PER
t_OUT50_HI
t_OUT50_LO
V
IH_RMII
V
IL_RMII
t_OUT50_RISE
t_OUT50_FALL
Figure 5-3 REFCLK Output Timing
Symbol
t_OUT50_PER
Description
REFCLK Clock Period
MIN
TYP
40.0 - 40.0
50ppm
14
14
20.0
20.0
t_OUT50_HI
REFCLK Clock High
t_OUT50_LO
REFCLK Clock Low
t_OUT50_RISE REFCLK Clock Rise Time , V
IL
(max) to V
IH
(min)
t_OUT50_FALL REFCLK Clock Fall Time , V
IH
(min) to V
IL
(max)
t_OUT50_JIT
REFCLK Clock Jittering (p-p)
Table 5-6 REFCLK Output Timing
MAX
40.0 +
50pp
m
26
26
2
2
UNIT
ns
ns
ns
ns
ns
ns
0.15
ADMtek Inc.
5-4