PHYSICAL PACKAGING
The receiver is packaged as a hybrid SMD module with sixteen pads spaced
0.100" on center. The castellated SMD package allows for easy prototyping or
hand assembly while maintaining full compatibility with automated pick-and-
place equipment. Modules are supplied in tube packaging.
TYPICAL PERFORMANCE GRAPHS
SENSITIVITY vs. VSWR
(VSWR)
10.0
6.0
5.0
4.0
3.0
2.5
2.0
1.5
1.0
0 0.18 0.5 0.9 1.25 1.94 2.53 3.10 4.80
SENSITIVITY DECREASE (dB)
V
DATA
3.7
Supply current
(mA)
16
12
8
4
0.812"
0.630"
LOT 2000
16
15
14
13
12
11
10
9
ANT
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
VCC
PDN
NC
DATA
1
2
3
4
5
6
7
8
2.7
2.7
0
3
2.7
3.5
4
3
4.5
3.5
5
5.2 (V)
4 (V)
V
CC
Supply voltage
Figure 3: Sensitivity vs. VSWR
Figure 4: Consumption vs. Supply Voltage
0.14"
Data Out
Bottom View
Figure 2: LC-S Series Receiver Package Dimensions
Data Out
PIN DESCRIPTIONS:
Pin 1, 2, 3, 7, 9, 10, 11, 12, 13, 14 - NO CONNECTION
Attach to an isolated pad to provide support for the module. Do not make any electrical
connection.
Carrier
Carrier
Figure 5: RF in vs. Receiver Response Time
Figure 6: Typical Receiver Turn-Off Time
Pin 4, 15 - GROUND
Connect to quiet ground or groundplane. It is internally connected to pin 8.
Original
Original
Pin 5 - POSITIVE SUPPLY
(V
CC
2.7 - 4.2 VDC *4.7 - 5.2 w/ external dropping resistor)
The supply must be clean (<20mVpp), stable and free of high-frequency noise. A supply
filter is recommended unless the module is operated from its own regulated supply or
battery. Please note that operation from 4.7 to 5.2 volts requires the use of an external
200 resistor placed in series with V .
CC
Received
Received
Pin 6 - POWER DOWN
Pull this line low to put the receiver in sleep mode (700 µA). Leave floating or pull high to
enable the receiver.
Figure 7: Original vs. Received Data
4,800bps 20% Duty Cycle
Figure 8: Original vs. Received Data
4,800bps 80% Duty Cycle
Pin 8 - DATA OUT
Internally pulled to V
CC
. Open collector data output with internal pullup to V
CC
. Recovered data
is output on this pin. Output voltage during a high bit will average V
CC
- 0.3V.
P
DN
Pin
Data Out
Pin 16 - RF IN
The receiver antenna connects to this input. It has nominal RF impedance of 50 and is
capacitively isolated from the internal circuitry.
Page 4
Figure 9: Power-On Settling Time
(Time to Valid Data)
Page 5
ETC [ ETC ]
