TP6312
1/4 TO 1/11-DUTY VFD CONTROLLER/DRIVER
Functional Description
Display RAM Address and Display Mode
The display RAM stores the data transmitted from an
external device to TP6312 through the serial interface,
and is assigned addresses as follows, in units of 8
bits:
Seg
1
00H
L
02H
L
04H
L
06H
L
08H
L
0AH
L
0CH
L
0EH
L
10H
L
12H
L
14H
L
b
0
XX H
L
Lower 4 bits
Seg
4
00H
U
02H
U
04H
U
06H
U
08H
U
0AH
U
0CH
U
0EH
U
10H
U
12H
U
14H
U
b
3
b
4
XX H
U
Higher 4 bits.
On power application, all LEDs are unlit.
The data of each Key is stored as illustrated below,
and is read by a read command, starting from the
least significant bit.
Key
1
Key
4
Key
1
Key
4
Seg
2
/ KS
2
Seg
1
/ KS
1
Seg
3
/ KS
3
Seg
5
/ KS
5
b0
b3 b4
Seg
8
01H
L
03H
L
05H
L
07H
L
09H
L
0BH
L
0DH
L
0FH
L
11H
L
13H
L
15H
L
Seg
12
Seg
16
DIG1
DIG2
DIG3
DIG4
DIG5
DIG6
DIG7
DIG8
DIG9
DIG10
DIG11
Seg
4
/ KS
4
Seg
6
/ KS
6
b7
Reading sequence
01H
U
03H
U
05H
U
07H
U
09H
U
0BH
U
0DH
U
0FH
U
11H
U
13H
U
15H
U
b
7
LED Port
Data is written to the LED port by a write command,
starting from the least significant bit of the port.
When a bit of this port is 0, the corresponding LED
lights; when the bit is 1, the LED goes off. The data
of bits 5 through 8 is ignored.
----
----
----
----
b3
b2
b1
b0
LED1
LED2
LED3
LED4
Don't care
Key Matrix and Key-Input Data Storage
RAM
The Key matrix is of 6
×
4 configuration, as shown
below.
KEY1
KEY2
KEY3
KEY4
Seg1/KS1
Seg2/KS2
Seg3/KS3
Seg4/KS4
Seg5/KS5
Seg6/KS6
SW Data
The SW data is read by a read command, starting
from the least significant bit.
SW data are 0.
MSB
0
0
0
0
b3
b2
b1
LSB
b0
SW1
SW2
SW3
SW4
Bits 5 through 8 of the
Commands
A command sets the display mode and status of the
VFD driver.
The first 1 byte input to TP6312 through the D
IN
pin
after the STB pin has fallen is regarded as a
command.
If STB is high while a command/data is transmitted,
serial
communication
is
initialized,
and
the
transmitting command/data is invalid; however, the
Version 1.1
September 2003
Page 3 of 9
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