CD4514BC• CD4515BC 4-Bit Latched/4-to-16 Line Decoders
October 1987
Revised January 1999
CD4514BC• CD4515BC
4-Bit Latched/4-to-16 Line Decoders
General Description
The CD4514BC and CD4515BC are 4-to-16 line decoders
with latched inputs implemented with complementary MOS
(CMOS) circuits constructed with N- and P-channel
enhancement mode transistors. These circuits are prima-
rily used in decoding applications where low power dissipa-
tion and/or high noise immunity is required.
The CD4514BC (output active high option) presents a logi-
cal “1” at the selected output, whereas the CD4515BC pre-
sents a logical “0” at the selected output. The input latches
are R–S type flip-flops, which hold the last input data pre-
sented prior to the strobe transition from “1” to “0”. This
input data is decoded and the corresponding output is acti-
vated. An output inhibit line is also available.
Features
s
Wide supply voltage range:
s
High noise immunity:
compatibility:
s
Low power TTL: fan out of 2
driving 74L
s
Low quiescent power dissipation:
0.025
µW/package
@ 5.0 V
DC
s
Single supply operation
s
Input impedance
=
10
12
Ω
typically
s
Plug-in replacement for MC14514, MC14515
3.0V to 15V
0.45 V
DD
(typ.)
Ordering Code:
Order Number
CD4514BCWM
CD4514BCN
CD4515BCWM
CD4515BCN
Package Number
M24B
N24A
M24B
N24A
Package Diagram
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for SOIC and DIP
Top View
© 1999 Fairchild Semiconductor Corporation
DS005994.prf
www.fairchildsemi.com
ETC [ ETC ]
