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DG406DN 参数 Datasheet PDF下载

DG406DN图片预览
型号: DG406DN
PDF下载: 下载PDF文件 查看货源
内容描述: 模拟多路复用器|单| 16路| CMOS | LDCC | 28PIN |塑料\n [ANALOG MUX|SINGLE|16-CHANNEL|CMOS|LDCC|28PIN|PLASTIC ]
分类和应用: 复用器
文件页数/大小: 9 页 / 105 K
品牌: ETC [ ETC ]
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DG406/407
Vishay Siliconix
16-Ch/Dual 8-Ch High-Performance CMOS Analog Multiplexers
FEATURES
D
D
D
D
D
D
Low On-Resistance—r
DS(on)
: 50
W
Low Charge Injection—Q: 15 pC
Fast Transition Time—t
TRANS:
200 ns
Low Power: 0.2 mW
Single Supply Capability
44-V Supply Max Rating
BENEFITS
D
D
D
D
D
D
Higher Accuracy
Reduced Glitching
Improved Data Throughput
Reduced Power Consumption
Increased Ruggedness
Wide Supply Ranges:
"5
V to
"20
V
APPLICATIONS
D
D
D
D
D
D
D
Data Acquisition Systems
Audio Signal Routing
Medical Instrumentation
ATE Systems
Battery Powered Systems
High-Rel Systems
Single Supply Systems
DESCRIPTION
The DG406 is a 16-channel single-ended analog multiplexer
designed to connect one of sixteen inputs to a common output as
determined by a 4-bit binary address. The DG407 selects one of
eight differential inputs to a common differential output.
Break-before-make switching action protects against momentary
shorting of inputs.
An on channel conducts current equally well in both directions. In
the off state each channel blocks voltages up to the power supply
rails. An enable (EN) function allows the user to reset the
multiplexer/demultiplexer to all switches off for stacking several
devices. All control inputs, address (A
x
) and enable (EN) are TTL
compatible over the full specified operating temperature range.
Applications for the DG406/407 include high speed data
acquisition, audio signal switching and routing, ATE systems, and
avionics. High performance and low power dissipation make
them ideal for battery operated and remote instrumentation
applications. For additional application information order Faxback
document numbers 70601 and 70604.
Designed in the 44-V silicon-gate CMOS process, the absolute
maximum voltage rating is extended to 44 volts, allowing
operation with
"20-V
supplies. Additionally single (12-V) supply
operation is allowed. An epitaxial layer prevents latchup.
For applications information please request FaxBack documents
70601 and 70604.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG406
V+
NC
NC
S
16
S
15
S
14
S
13
S
12
S
11
S
10
S
9
GND
NC
A
3
Dual-In-Line and SOIC Wide-Body
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Top View
Decoders/Drivers
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D
V–
S
8
S
7
S
6
S
5
S
4
S
3
S
2
S
1
EN
A
0
A
1
A
2
DG407
V+
D
b
NC
S
8b
S
7b
S
6b
S
5b
S
4b
S
3b
S
2b
S
1b
GND
NC
NC
1
2
3
4
5
6
7
8
9
Dual-In-Line and SOIC Wide-Body
28
27
26
25
24
23
22
21
20
19
18
Decoders/Drivers
17
16
15
Top View
D
a
V–
S
8a
S
7a
S
6a
S
5a
S
4a
S
3a
S
2a
S
1a
EN
A
0
A
1
A
2
10
11
12
13
14
Document Number: 70061
S-00399—Rev. H, 13-Sep-99
www.vishay.com
S
FaxBack 408-970-5600
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