Part II Features
Figure 2-1 is a block diagram of the MPC850, showing its major components and the
relationships among those components:
2-Kbyte
I-Cache
Embedded
MPC8xx
Core
Instruction
Bus
Instruction
MMU
1-Kbyte
D-Cache
Load/Store
Bus
Data
MMU
System Interface Unit
Memory Controller
Unified Bus
Bus Interface Unit
System Functions
Real-Time Clock
PCMCIA Interface
Baud Rate
Generators
Parallel I/O
Ports
Four
Timers
Interrupt
Controller
Dual-Port
RAM
20 Virtual
Serial DMA
Channels
and
2 Virtual
IDMA
Channels
Peripheral Bus
Communications
Processor
Module
32-Bit RISC Communications
Processor (CP) and Program ROM
UTOPIA
(850SR & DSL) Timer
SCC2
TDMa
SCC3
SMC1
SMC2
USB
SPI
I
2
C
Time Slot Assigner
Non-Multiplexed Serial Interface
Figure 2-1. MPC850 Microprocessor Block Diagram
The following list summarizes the main features of the MPC850:
•
Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC
architecture) with thirty-two 32-bit general-purpose registers (GPRs)
— Performs branch folding and branch prediction with conditional prefetch, but
without conditional execution
MOTOROLA
MPC850 (Rev. A/B/C) Hardware Specifications
3
ETC [ ETC ]
