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82C54

CMOS Programmable Interval Timer

March 1997

Features

Description

• 8MHz to 12MHz Clock Input Frequency

The Intersil 82C54 is a high performance CMOS Program-

mable Interval Timer manufactured using an advanced 2

micron CMOS process.

• Compatible with NMOS 8254

- Enhanced Version of NMOS 8253

The 82C54 has three independently programmable and

functional 16-bit counters, each capable of handling clock

input frequencies of up to 8MHz (82C54) or 10MHz

(82C54-10) or 12MHz (82C54-12).

• Three Independent 16-Bit Counters

• Six Programmable Counter Modes

• Status Read Back Command

• Binary or BCD Counting

The high speed and industry standard conﬁguration of the

82C54 make it compatible with the Intersil 80C86, 80C88,

and 80C286 CMOS microprocessors along with many other

industry standard processors. Six programmable timer

modes allow the 82C54 to be used as an event counter,

elapsed time indicator, programmable one-shot, and many

other applications. Static CMOS circuit design insures low

power operation.

• Fully TTL Compatible

• Single 5V Power Supply

• Low Power

- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10µA

- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . .10mA at 8MHz

• Operating Temperature Ranges

The Intersil advanced CMOS process results in a signiﬁcant

reduction in power with performance equal to or greater than

existing equivalent products.

o

- C82C54 . . . . . . . . . . . . . . . . . . . . . . . . . .0 C to +70 C

o

- I82C54 . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C

o

- M82C54 . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C

Pinouts

82C54 (PDIP, CERDIP, SOIC)

82C54 (PLCC/CLCC)

TOP VIEW

D7

D6

1

2

3

4

5

6

7

8

9

24

VCC

23 WR

22

4

3

2

1

28 27 26

D5

RD

D4

D3

5

6

25 NC

21 CS

D4

24 CS

D3

20 A1

D2

19 A0

D2

7

23 A1

D1

18 CLK 2

17 OUT 2

16 GATE 2

D1

8

22 A0

D0

9

D0

21 CLK2

20 OUT 2

19 GATE 2

CLK 0

10

11

CLK 0

NC

15

OUT 0 10

GATE 0 11

GND 12

CLK 1

14 GATE 1

13 OUT 1

12 13 14 15 16 17 18

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 2970.1

82C54

Ordering Information

PART NUMBERS

10MHz

CP82C54-10

TEMPERATURE

RANGE

8MHz

CP82C54

12MHz

CP82C54-12

PACKAGE

24 Lead PDIP

PKG. NO.

E24.6

o

0 C to +70 C

o

IP82C54

IP82C54-10

CS82C54-10

IS82C54-10

CD82C54-10

ID82C54-10

MD82C54-10/B

MR82C54-10/B

-

IP82C54-12

CS82C54-12

IS82C54-12

CD82C54-12

ID82C54-12

-40 C to +85 C

24 Lead PDIP

E24.6

o

CS82C54

0 C to +70 C

28 Lead PLCC

24 Lead CERDIP

28 Lead CLCC

24 Lead CERDIP

28 Lead CLCC

24 Lead SOIC

N28.45

F24.6

o

IS82C54

-40 C to +85 C

o

CD82C54

0 C to +70 C

o

ID82C54

-40 C to +85 C

F24.6

o

MD82C54/B

MR82C54/B

SMD # 8406501JA

SMD# 84065013A

CM82C54

MD82C54-12/B

MR82C54-12/B

8406502JA

-55 C to +125 C

F24.6

o

-55 C to +125 C

J28.A

o

-55 C to +125 C

F24.6

o

-

84065023A

-55 C to +125 C

J28.A

o

CM82C54-10

CM82C54-12

0 C to +70 C

M24.3

Functional Diagram

CLK 0

DATA/

COUNTER

BUS

8

D

- D

0

GATE 0

OUT 0

7

INTERNAL BUS

0

BUFFER

CONTROL

WORD

STATUS

LATCH

REGISTER

CR

L

M

RD

STATUS

REGISTER

CLK 1

GATE 1

OUT 1

READ/

WRITE

LOGIC

WR

COUNTER

1

A

0

1

A

CE

CONTROL

LOGIC

CS

CLK 2

GATE 2

OUT 2

OL

M

OL

L

CONTROL

WORD

REGISTER

COUNTER

2

GATE n

CLK n

OUT n

COUNTER INTERNAL BLOCK DIAGRAM

Pin Description

DIP PIN

SYMBOL

D7 - D0

CLK 0

NUMBER

TYPE

DEFINITION

1 - 8

9

I/O

DATA: Bi-directional three-state data bus lines, connected to system data bus.

CLOCK 0: Clock input of Counter 0.

OUT 0: Output of Counter 0.

I

O

I

OUT 0

GATE 0

GND

10

11

12

13

14

15

16

17

GATE 0: Gate input of Counter 0.

GROUND: Power supply connection.

OUT 1: Output of Counter 1.

OUT 1

GATE 1

CLK 1

O

I

GATE 1: Gate input of Counter 1.

I

CLOCK 1: Clock input of Counter 1.

GATE 2: Gate input of Counter 2.

GATE 2

OUT 2

I

O

OUT 2: Output of Counter 2.

4-2

82C54

Pin Description (Continued)

DIP PIN

SYMBOL

CLK 2

NUMBER

TYPE

DEFINITION

18

I

CLOCK 2: Clock input of Counter 2.

A0, A1

19 - 20

ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write

operations. Normally connected to the system address bus.

A1

0

A0

0

SELECTS

Counter 0

0

1

Counter 1

1

0

Counter 2

1

Control Word Register

CS

21

I

CHIP SELECT: A low on this input enables the 82C54 to respond to RD and WR signals. RD and

WR are ignored otherwise.

RD

22

23

24

I

READ: This input is low during CPU read operations.

WRITE: This input is low during CPU write operations.

WR

V

: The +5V power supply pin. A 0.1µF capacitor between pins VCC and GND is recommended

CC

for decoupling.

Functional Description

General

The 82C54 is a programmable interval timer/counter

designed for use with microcomputer systems. It is a general

purpose, multi-timing element that can be treated as an

array of I/O ports in the system software.

CLK 0

GATE 0

OUT 0

DATA/

BUS

BUFFER

COUNTER

0

D

- D

0

8

7

The 82C54 solves one of the most common problems in any

microcomputer system, the generation of accurate time

delays under software control. Instead of setting up timing

loops in software, the programmer conﬁgures the 82C54 to

match his requirements and programs one of the counters

for the desired delay. After the desired delay, the 82C54 will

interrupt the CPU. Software overhead is minimal and vari-

able length delays can easily be accommodated.

RD

CLK 1

GATE 1

OUT 1

READ/

WRITE

LOGIC

WR

COUNTER

1

A

0

1

A

CS

Some of the other computer/timer functions common to micro-

computers which can be implemented with the 82C54 are:

CLK 2

GATE 2

OUT 2

CONTROL

WORD

REGISTER

COUNTER

2

• Real time clock

• Event counter

• Digital one-shot

• Programmable rate generator

• Square wave generator

• Binary rate multiplier

• Complex waveform generator

• Complex motor controller

FIGURE 1. DATA BUS BUFFER AND READ/WRITE LOGIC

FUNCTIONS

Read/Write Logic

The Read/Write Logic accepts inputs from the system bus and

generates control signals for the other functional blocks of the

82C54. A1 and A0 select one of the three counters or the Con-

trol Word Register to be read from/written into. A “low” on the

RD input tells the 82C54 that the CPU is reading one of the

counters. A “low” on the WR input tells the 82C54 that the CPU

is writing either a Control Word or an initial count. Both RD and

WR are qualiﬁed by CS; RD and WR are ignored unless the

82C54 has been selected by holding CS low.

Data Bus Buffer

This three-state, bi-directional, 8-bit buffer is used to inter-

face the 82C54 to the system bus (see Figure 1).

4-3

82C54

Control Word Register

The Control Word Register (Figure 2) is selected by the

Read/Write Logic when A1, A0 = 11. If the CPU then does a

write operation to the 82C54, the data is stored in the Con-

trol Word Register and is interpreted as a Control Word used

to deﬁne the Counter operation.

INTERNAL BUS

CONTROL

WORD

REGISTER

STATUS

LATCH

CR

L

M

The Control Word Register can only be written to; status

information is available with the Read-Back Command.

STATUS

REGISTER

CE

CONTROL

LOGIC

CLK 0

DATA/

COUNTER

D

- D

0

8

BUS

7

GATE 0

OUT 0

0

BUFFER

OL

M

OL

L

RD

GATE n

CLK 1

GATE 1

OUT 1

READ/

WRITE

LOGIC

WR

COUNTER

1

CLK n

OUT n

A

0

FIGURE 3. COUNTER INTERNAL BLOCK DIAGRAM

1

OLM and OLL are two 8-bit latches. OL stands for “Output

Latch”; the subscripts M and L for “Most signiﬁcant byte” and

“Least signiﬁcant byte”, respectively. Both are normally referred

to as one unit and called just OL. These latches normally “fol-

low” the CE, but if a suitable Counter Latch Command is sent to

the 82C54, the latches “latch” the present count until read by

the CPU and then return to “following” the CE. One latch at a

time is enabled by the counter’s Control Logic to drive the inter-

nal bus. This is how the 16-bit Counter communicates over the

8-bit internal bus. Note that the CE itself cannot be read; when-

ever you read the count, it is the OL that is being read.

CS

CLK 2

GATE 2

OUT 2

CONTROL

WORD

REGISTER

COUNTER

2

FIGURE 2. CONTROL WORD REGISTER AND COUNTER

FUNCTIONS

Similarly, there are two 8-bit registers called CRM and CRL (for

“Count Register”). Both are normally referred to as one unit and

called just CR. When a new count is written to the Counter, the

count is stored in the CR and later transferred to the CE. The

Control Logic allows one register at a time to be loaded from

the internal bus. Both bytes are transferred to the CE simulta-

neously. CRM and CRL are cleared when the Counter is pro-

grammed for one byte counts (either most signiﬁcant byte only

or least signiﬁcant byte only) the other byte will be zero. Note

that the CE cannot be written into; whenever a count is written,

it is written into the CR.

Counter 0, Counter 1, Counter 2

These three functional blocks are identical in operation, so

only a single Counter will be described. The internal block

diagram of a signal counter is shown in Figure 3. The

counters are fully independent. Each Counter may operate

in a different Mode.

The Control Word Register is shown in the ﬁgure; it is not

part of the Counter itself, but its contents determine how the

Counter operates.

The Control Logic is also shown in the diagram. CLK n,

GATE n, and OUT n are all connected to the outside world

through the Control Logic.

The status register, shown in the ﬁgure, when latched, con-

tains the current contents of the Control Word Register and

status of the output and null count ﬂag. (See detailed expla-

nation of the Read-Back command.)

82C54 System Interface

The 82C54 is treated by the system software as an array of

peripheral I/O ports; three are counters and the fourth is a

control register for MODE programming.

The actual counter is labeled CE (for Counting Element). It is

a 16-bit presettable synchronous down counter.

Basically, the select inputs A0, A1 connect to the A0, A1

address bus signals of the CPU. The CS can be derived

directly from the address bus using a linear select method or

it can be connected to the output of a decoder.

4-4

82C54

Operational Description

SC - Select Counter

General

SC1

SC0

0

1

0

1

0

1

Select Counter 0

After power-up, the state of the 82C54 is undeﬁned. The

Mode, count value, and output of all Counters are undeﬁned.

Select Counter 1

How each Counter operates is determined when it is pro-

grammed. Each Counter must be programmed before it can

be used. Unused counters need not be programmed.

Select Counter 2

Read-Back Command (See Read Operations)

RW - Read/Write

RW1 RW0

Programming the 82C54

Counters are programmed by writing a Control Word and

then an initial count.

0

1

0

1

0

1

Counter Latch Command (See Read Operations)

Read/Write least significant byte only.

All Control Words are written into the Control Word Register,

which is selected when A1, A0 = 11. The Control Word spec-

iﬁes which Counter is being programmed.

Read/Write most significant byte only.

Read/Write least significant byte first, then most

significant byte.

By contrast, initial counts are written into the Counters, not

the Control Word Register. The A1, A0 inputs are used to

select the Counter to be written into. The format of the initial

count is determined by the Control Word used.

M - Mode

M2

0

M1

M0

0

1

0

1

0

1

0

1

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

ADDRESS BUS (16)

A1 A0

0

X

1

CONTROL BUS

I/OR I/OW

DATA BUS (8)

1

8

BCD - Binary Coded Decimal

RD

WR

CS

D0 - D7

82C54

A0

A1

0

1

Binary Counter 16-bit

COUNTER

0

COUNTER

1

COUNTER

2

Binary Coded Decimal (BCD) Counter (4 Decades)

NOTE: Don’t Care bits (X) should be 0 to insure compatibility with

future products.

OUTGATE CLK OUTGATE CLK OUTGATECLK

Possible Programming Sequence

FIGURE 4. 82C54 SYSTEM INTERFACE

A1

1

A0

1

Write Operations

Control Word - Counter 0

LSB of Count - Counter 0

MSB of Count - Counter 0

Control Word - Counter 1

LSB of Count - Counter 1

MSB of Count - Counter 1

Control Word - Counter 2

LSB of Count - Counter 2

MSB of Count - Counter 2

The programming procedure for the 82C54 is very ﬂexible.

Only two conventions need to be remembered:

0

1. For Each Counter, the Control Word must be written

before the initial count is written.

1

0

1

2. The initial count must follow the count format speciﬁed in the

Control Word (least signiﬁcant byte only, most signiﬁcant byte

only, or least signiﬁcant byte and then most signiﬁcant byte).

0

1

Since the Control Word Register and the three Counters have

separate addresses (selected by the A1, A0 inputs), and each

Control Word speciﬁes the Counter it applies to (SC0, SC1 bits),

no special instruction sequence is required. Any programming

sequence that follows the conventions above is acceptable.

1

0

1

0

Possible Programming Sequence

A1

1

A0

1

Control Word Format

Control Word - Counter 0

Control Word - Counter 1

Control Word - Counter 2

LSB of Count - Counter 2

A1, A0 = 11; CS = 0; RD = 1; WR = 0

1

D7

D6

D5

D4

D3

D2

D1

D0

1

0

SC1

SC0

RW1

RW0

M2

M1

M0

BCD

4-5

82C54

Possible Programming Sequence (Continued)

A1

explained later. The second is a simple read operation of the

Counter, which is selected with the A1, A0 inputs. The only

requirement is that the CLK input of the selected Counter

must be inhibited by using either the GATE input or external

logic. Otherwise, the count may be in process of changing

when it is read, giving an undeﬁned result.

A0

1

LSB of Count - Counter 1

LSB of Count - Counter 0

MSB of Count - Counter 0

MSB of Count - Counter 1

MSB of Count - Counter 2

0

1

0

Counter Latch Command

1

The other method for reading the Counters involves a spe-

cial software command called the “Counter Latch Com-

mand”. Like a Control Word, this command is written to the

Control Word Register, which is selected when A1, A0 = 11.

Also, like a Control Word, the SC0, SC1 bits select one of

the three Counters, but two other bits, D5 and D4, distin-

guish this command from a Control Word.

0

Possible Programming Sequence

A1

1

A0

1

Control Word - Counter 2

Control Word - Counter 1

Control Word - Counter 0

LSB of Count - Counter 2

MSB of Count - Counter 2

LSB of Count - Counter 1

MSB of Count - Counter 1

LSB of Count - Counter 0

MSB of Count - Counter 0

1

.

1

A1, A0 = 11; CS = 0; RD = 1; WR = 0

1

0

D7

D6

D5

D4

D3

D2

D1

D0

1

0

SC1

SC0

0

X

0

1

0

1

SC1, SC0 - specify counter to be latched

0

SC1

SC0

COUNTER

0

1

0

1

0

1

0

1

2

Possible Programming Sequence

A1

1

A0

1

Control Word - Counter 1

Control Word - Counter 0

LSB of Count - Counter 1

Control Word - Counter 2

LSB of Count - Counter 0

MSB of Count - Counter 1

LSB of Count - Counter 2

MSB of Count - Counter 0

MSB of Count - Counter 2

Read-Back Command

1

D5, D4 - 00 designates Counter Latch Command, X - Don’t Care.

NOTE: Don’t Care bits (X) should be 0 to insure compatibility with

future products.

0

1

0

The selected Counter’s output latch (OL) latches the count

when the Counter Latch Command is received. This count is

held in the latch until it is read by the CPU (or until the Counter

is reprogrammed). The count is then unlatched automatically

and the OL returns to “following” the counting element (CE).

This allows reading the contents of the Counters “on the ﬂy”

without affecting counting in progress. Multiple Counter Latch

Commands may be used to latch more than one Counter.

Each latched Counter’s OL holds its count until read. Counter

Latch Commands do not affect the programmed Mode of the

Counter in any way.

0

1

0

1

0

NOTE: In all four examples, all counters are programmed to

Read/Write two-byte counts. These are only four of many

programming sequences.

A new initial count may be written to a Counter at any time

without affecting the Counter’s programmed Mode in any way.

Counting will be affected as described in the Mode deﬁnitions.

The new count must follow the programmed count format.

If a Counter is latched and then, some time later, latched

again before the count is read, the second Counter Latch

Command is ignored. The count read will be the count at the

time the ﬁrst Counter Latch Command was issued.

If a Counter is programmed to read/write two-byte counts,

the following precaution applies. A program must not transfer

control between writing the ﬁrst and second byte to another

routine which also writes into that same Counter. Otherwise,

the Counter will be loaded with an incorrect count.

With either method, the count must be read according to the

programmed format; speciﬁcally, if the Counter is pro-

grammed for two byte counts, two bytes must be read. The

two bytes do not have to be read one right after the other;

read or write or programming operations of other Counters

may be inserted between them.

Read Operations

It is often desirable to read the value of a Counter without

disturbing the count in progress. This is easily done in the

82C54.

Another feature of the 82C54 is that reads and writes of the

same Counter may be interleaved; for example, if the

Counter is programmed for two byte counts, the following

sequence is valid.

There are three possible methods for reading the Counters.

The ﬁrst is through the Read-Back command, which is

4-6

82C54

1. Read least signiﬁcant byte.

2. Write new least signiﬁcant byte.

3. Read most signiﬁcant byte.

4. Write new most signiﬁcant byte.

The read-back command may also be used to latch status

information of selected counter(s) by setting STATUS bit D4

= 0. Status must be latched to be read; status of a counter is

accessed by a read from that counter.

The counter status format is shown in Figure 6. Bits D5

through D0 contain the counter’s programmed Mode exactly

as written in the last Mode Control Word. OUTPUT bit D7

contains the current state of the OUT pin. This allows the

user to monitor the counter’s output via software, possibly

eliminating some hardware from a system.

If a counter is programmed to read or write two-byte counts,

the following precaution applies: A program MUST NOT

transfer control between reading the ﬁrst and second byte to

another routine which also reads from that same Counter.

Otherwise, an incorrect count will be read.

Read-Back Command

D7

D6

D5

D4

D3

D2

D1

D0

The read-back command allows the user to check the count

value, programmed Mode, and current state of the OUT pin

and Null Count ﬂag of the selected counter(s).

OUTPUT

NULL

COUNT

RW1 RW0 M2

M1

M0 BCD

D7: 1 =Out pin is 1

=Out pin is 0

D6: 1 =Null count

=Count available for reading

The command is written into the Control Word Register and

has the format shown in Figure 5. The command applies to

the counters selected by setting their corresponding bits D3,

D2, D1 = 1.

0

D5 - D0 =Counter programmed mode (See Control Word Formats)

FIGURE 6. STATUS BYTE

A0, A1 = 11; CS = 0; RD = 1; WR = 0

D7 D6

D5

D4

D3

D2

D1

D0

NULL COUNT bit D6 indicates when the last count written to

the counter register (CR) has been loaded into the counting

element (CE). The exact time this happens depends on the

Mode of the counter and is described in the Mode Deﬁnitions,

but until the counter is loaded into the counting element (CE),

it can’t be read from the counter. If the count is latched or read

before this time, the count value will not reﬂect the new count

just written. The operation of Null Count is shown below.

1

COUNT

STATUS CNT 2 CNT 1 CNT 0

0

D5: 0 = Latch count of selected Counter (s)

D4: 0 = Latch status of selected Counter(s)

D3: 1 = Select Counter 2

D2: 1 = Select Counter 1

D1: 1 = Select Counter 0

D0: Reserved for future expansion; Must be 0

THIS ACTION:

CAUSES:

FIGURE 5. READ-BACK COMMAND FORMAT

A. Write to the control word register:(1) . . . . . . . . . . Null Count = 1

B. Write to the count register (CR):(2) . . . . . . . . . . . Null Count = 1

C. New count is loaded into CE (CR - CE). . . . . . . . Null Count = 0

The read-back command may be used to latch multiple

counter output latches (OL) by setting the COUNT bit D5 = 0

and selecting the desired counter(s). This signal command

is functionally equivalent to several counter latch commands,

one for each counter latched. Each counter’s latched count

is held until it is read (or the counter is reprogrammed). That

counter is automatically unlatched when read, but other

counters remain latched until they are read. If multiple count

read-back commands are issued to the same counter with-

out reading the count, all but the ﬁrst are ignored; i.e., the

count which will be read is the count at the time the ﬁrst

read-back command was issued.

(1) Only the counter speciﬁed by the control word will have its null

count set to 1. Null count bits of other counters are unaffected.

(2) If the counter is programmed for two-byte counts (least signiﬁ-

cant byte then most signiﬁcant byte) null count goes to 1 when

the second byte is written.

If multiple status latch operations of the counter(s) are per-

formed without reading the status, all but the ﬁrst are ignored;

i.e., the status that will be read is the status of the counter at

the time the ﬁrst status read-back command was issued.

COMMANDS

D7

1

D6

1

D5

0

D4

0

D3

0

D2

0

D1

1

D0

0

DESCRIPTION

RESULT

Read-Back Count and Status of Counter 0 Count and Status Latched for Counter 0

1

0

1

0

Read-Back Status of Counter 1

Status Latched for Counter 1

1

0

1

0

Read-Back Status of Counters 2, 1

Status Latched for Counter 2,

But Not Counter 1

1

0

1

0

1

0

1

0

Read-Back Count of Counter 2

Count Latched for Counter 2

Read-Back Count and Status of Counter 1 Count Latched for Counter 1,

But Not Status

1

0

1

0

Read-Back Status of Counter 1

Command Ignored, Status Already

Latched for Counter 1

FIGURE 7. READ-BACK COMMAND EXAMPLE

4-7

82C54

Both count and status of the selected counter(s) may be If a new count is written to the Counter it will be loaded on

latched simultaneously by setting both COUNT and STATUS the next CLK pulse and counting will continue from the new

bits D5, D4 = 0. This is functionally the same as issuing two count. If a two-byte count is written, the following happens:

separate read-back commands at once, and the above dis-

(1)Writing the ﬁrst byte disables counting. Out is set low

cussions apply here also. Speciﬁcally, if multiple count

immediately (no clock pulse required).

and/or status read-back commands are issued to the same

counter(s) without any intervening reads, all but the ﬁrst are

ignored. This is illustrated in Figure 7.

(2)Writing the second byte allows the new count to be

loaded on the next CLK pulse.

If both count and status of a counter are latched, the ﬁrst

read operation of that counter will return latched status,

regardless of which was latched ﬁrst. The next one or two

reads (depending on whether the counter is programmed for

one or two type counts) return latched count. Subsequent

reads return unlatched count.

This allows the counting sequence to be synchronized by

software. Again OUT does not go high until N + 1 CLK

pulses after the new count of N is written.

If an initial count is written while GATE = 0, it will still be

loaded on the next CLK pulse. When GATE goes high, OUT

will go high N CLK pulses later; no CLK pulse is needed to

load the counter as this has already been done.

CS

0

RD WR

A1

0

A0

0

CW = 10 LSB = 4

1

0

X

1

0

1

X

1

Write into Counter 0

WR

0

1

Write into Counter 1

0

1

0

Write into Counter 2

CLK

0

1

Write Control Word

GATE

OUT

0

Read from Counter 0

Read from Counter 1

Read from Counter 2

No-Operation (Three-State)

0

1

0

4

0

3

0

2

0

1

0

FF FF

FF FE

N

0

1

0

1

CW = 10 LSB = 3

1

X

WR

CLK

0

FIGURE 8. READ/WRITE OPERATIONS SUMMARY

Mode Deﬁnitions

GATE

The following are deﬁned for use in describing the operation

of the 82C54.

OUT

0

3

0

2

0

2

0

2

0

1

0

FF

CLK PULSE:

N

A rising edge, then a falling edge, in that order, of a

Counter’s CLK input.

CW = 10 LSB = 3

LSB = 2

WR

TRIGGER:

A rising edge of a Counter’s Gate input.

CLK

COUNTER LOADING:

GATE

OUT

The transfer of a count from the CR to the CE (See “Func-

tional Description”)

0

3

0

2

0

1

0

2

0

1

0

FF

N

Mode 0: Interrupt on Terminal Count

FIGURE 9. MODE 0

NOTES: The following conventions apply to all mode timing diagrams.

Mode 0 is typically used for event counting. After the Control

Word is written, OUT is initially low, and will remain low until

the Counter reaches zero. OUT then goes high and remains

high until a new count or a new Mode 0 Control Word is writ-

ten to the Counter.

1. Counters are programmed for binary (not BCD) counting and for

reading/writing least signiﬁcant byte (LSB) only.

2. The counter is always selected (CS always low).

3. CW stands for “Control Word”; CW = 10 means a control word of

10, Hex is written to the counter.

GATE = 1 enables counting; GATE = 0 disables counting.

GATE has no effect on OUT.

4. LSB stands for Least significant “byte” of count.

After the Control Word and initial count are written to a

Counter, the initial count will be loaded on the next CLK

pulse. This CLK pulse does not decrement the count, so for

an initial count of N, OUT does not go high until N + 1 CLK

pulses after the initial count is written.

5. Numbers below diagrams are count values. The lower number is

the least significant byte. The upper number is the most signifi-

cant byte. Since the counter is programmed to read/write LSB

only, the most significant byte cannot be read.

6. N stands for an undefined count.

7. Vertical lines show transitions between count values.

4-8

82C54

Mode 1: Hardware Retriggerable One-Shot

Mode 2: Rate Generator

OUT will be initially high. OUT will go low on the CLK pulse This Mode functions like a divide-by-N counter. It is typically

following a trigger to begin the one-shot pulse, and will remain used to generate a Real Time Clock Interrupt. OUT will ini-

low until the Counter reaches zero. OUT will then go high and tially be high. When the initial count has decremented to 1,

remain high until the CLK pulse after the next trigger.

OUT goes low for one CLK pulse. OUT then goes high

again, the Counter reloads the initial count and the process

is repeated. Mode 2 is periodic; the same sequence is

repeated indeﬁnitely. For an initial count of N, the sequence

repeats every N CLK cycles.

After writing the Control Word and initial count, the Counter is

armed. A trigger results in loading the Counter and setting

OUT low on the next CLK pulse, thus starting the one-shot

pulse N CLK cycles in duration. The one-shot is retriggerable,

hence OUT will remain low for N CLK pulses after any trigger. GATE = 1 enables counting; GATE = 0 disables counting. If

The one-shot pulse can be repeated without rewriting the GATE goes low during an output pulse, OUT is set high

same count into the counter. GATE has no effect on OUT.

immediately. A trigger reloads the Counter with the initial

count on the next CLK pulse; OUT goes low N CLK pulses

after the trigger. Thus the GATE input can be used to syn-

chronize the Counter.

If a new count is written to the Counter during a one-shot

pulse, the current one-shot is not affected unless the

Counter is retriggerable. In that case, the Counter is loaded

with the new count and the one-shot pulse continues until After writing a Control Word and initial count, the Counter will

the new count expires.

be loaded on the next CLK pulse. OUT goes low N CLK

pulses after the initial count is written. This allows the

Counter to be synchronized by software also.

CW = 12 LSB = 3

WR

Writing a new count while counting does not affect the current

counting sequence. If a trigger is received after writing a new

count but before the end of the current period, the Counter will

be loaded with the new count on the next CLK pulse and count-

ing will continue from the end of the current counting cycle.

CLK

GATE

OUT

CW = 14

LSB = 3

WR

0

3

0

2

0

1

0

FF

0

3

0

2

N

CLK

GATE

OUT

CW = 12 LSB = 3

WR

0

3

0

2

0

1

0

3

0

2

0

1

0

3

N

CLK

CW = 14

LSB = 3

GATE

OUT

WR

CLK

0

3

0

2

0

1

0

3

0

2

0

1

0

N

GATE

OUT

CW = 12 LSB = 2

LSB = 4

WR

0

3

0

2

0

2

0

3

0

2

0

1

0

3

N

CW = 14

LSB = 4

LSB = 5

CLK

WR

GATE

OUT

CLK

GATE

OUT

0

2

0

1

0

FF FF

FF FE

0

4

0

3

N

0

4

0

3

0

2

0

1

0

5

0

4

0

3

FIGURE 10. MODE 1

N

FIGURE 11. MODE 2

4-9

82C54

Mode 3: Square Wave Mode

Mode 3 is Implemented as Follows:

Mode 3 is typically used for Baud rate generation. Mode 3 is EVEN COUNTS: OUT is initially high. The initial count is

similar to Mode 2 except for the duty cycle of OUT. OUT will loaded on one CLK pulse and then is decremented by two

initially be high. When half the initial count has expired, OUT on succeeding CLK pulses. When the count expires, OUT

goes low for the remainder of the count. Mode 3 is periodic; changes value and the Counter is reloaded with the initial

the sequence above is repeated indeﬁnitely. An initial count count. The above process is repeated indeﬁnitely.

of N results in a square wave with a period of N CLK cycles.

ODD COUNTS: OUT is initially high. The initial count is loaded

GATE = 1 enables counting; GATE = 0 disables counting. If on one CLK pulse, decremented by one on the next CLK pulse,

GATE goes low while OUT is low, OUT is set high immedi- and then decremented by two on succeeding CLK pulses.

ately; no CLK pulse is required. A trigger reloads the When the count expires, OUT goes low and the Counter is

Counter with the initial count on the next CLK pulse. Thus reloaded with the initial count. The count is decremented by

the GATE input can be used to synchronize the Counter.

three on the next CLK pulse, and then by two on succeeding

CLK pulses. When the count expires, OUT goes high again and

the Counter is reloaded with the initial count. The above pro-

cess is repeated indeﬁnitely. So for odd counts, OUT will be

high for (N + 1)/2 counts and low for (N - 1)/2 counts.

After writing a Control Word and initial count, the Counter will

be loaded on the next CLK pulse. This allows the Counter to

be synchronized by software also.

Writing a new count while counting does not affect the cur-

rent counting sequence. If a trigger is received after writing a

Mode 4: Software Triggered Mode

new count but before the end of the current half-cycle of the OUT will be initially high. When the initial count expires, OUT

square wave, the Counter will be loaded with the new count will go low for one CLK pulse then go high again. The count-

on the next CLK pulse and counting will continue from the ing sequence is “Triggered” by writing the initial count.

new count. Otherwise, the new count will be loaded at the

GATE = 1 enables counting; GATE = 0 disables counting.

end of the current half-cycle.

GATE has no effect on OUT.

CW = 16 LSB = 4

After writing a Control Word and initial count, the Counter will be

loaded on the next CLK pulse. This CLK pulse does not decre-

WR

ment the count, so for an initial count of N, OUT does not strobe

low until N + 1 CLK pulses after the initial count is written.

CLK

If a new count is written during counting, it will be loaded on

the next CLK pulse and counting will continue from the new

GATE

count. If a two-byte count is written, the following happens:

OUT

(1)Writing the ﬁrst byte has no effect on counting.

0

4

0

2

0

4

0

2

0

4

0

2

0

4

0

2

0

4

0

2

N

(2)Writing the second byte allows the new count to be

loaded on the next CLK pulse.

CW = 16 LSB = 5

WR

This allows the sequence to be “retriggered” by software. OUT

strobes low N + 1 CLK pulses after the new count of N is written.

CLK

GATE

OUT

0

5

0

4

0

2

0

5

0

2

0

5

0

4

0

2

0

5

0

2

N

CW = 16 LSB = 4

WR

CLK

GATE

OUT

0

4

0

2

0

4

0

2

0

2

0

2

0

4

0

2

0

4

0

2

N

FIGURE 12. MODE 3

4-10

82C54

CW = 18 LSB = 3

CW = 1A LSB = 3

WR

CLK

GATE

OUT

CLK

GATE

OUT

0

3

0

2

0

1

0

FF FF FF

FF FE FD

N

0

3

0

2

0

1

0

FF

0

3

N

CW = 18 LSB = 3

CW = 1A LSB = 3

WR

CLK

GATE

OUT

GATE

OUT

0

1

0

FF

N

3

2

0

3

0

2

0

3

0

2

0

1

0

FF

N

CW = 18 LSB = 3

LSB = 2

CW = 1A LSB = 3

LSB = 5

WR

CLK

GATE

OUT

GATE

OUT

0

3

0

2

0

1

0

2

0

1

0

FF

N

0

5

FIGURE 13. MODE 4

0

3

0

2

0

1

0

FF FF

FF FE

0

4

N

Mode 5: Hardware Triggered Strobe (Retriggerable)

FIGURE 14. MODE 5

OUT will initially be high. Counting is triggered by a rising

edge of GATE. When the initial count has expired, OUT will

go low for one CLK pulse and then go high again.

Operation Common to All Modes

Programming

After writing the Control Word and initial count, the counter

will not be loaded until the CLK pulse after a trigger. This

CLK pulse does not decrement the count, so for an initial

count of N, OUT does not strobe low until N + 1 CLK pulses

after trigger.

When a Control Word is written to a Counter, all Control

Logic, is immediately reset and OUT goes to a known initial

state; no CLK pulses are required for this.

Gate

A trigger results in the Counter being loaded with the initial The GATE input is always sampled on the rising edge of

count on the next CLK pulse. The counting sequence is trig- CLK. In Modes 0, 2, 3 and 4 the GATE input is level sensi-

gerable. OUT will not strobe low for N + 1 CLK pulses after tive, and logic level is sampled on the rising edge of CLK. In

any trigger GATE has no effect on OUT.

modes 1, 2, 3 and 5 the GATE input is rising-edge sensitive.

In these Modes, a rising edge of Gate (trigger) sets an edge-

sensitive ﬂip-ﬂop in the Counter. This ﬂip-ﬂop is then sam-

pled on the next rising edge of CLK. The ﬂip-ﬂop is reset

immediately after it is sampled. In this way, a trigger will be

detected no matter when it occurs - a high logic level does

not have to be maintained until the next rising edge of CLK.

Note that in Modes 2 and 3, the GATE input is both edge-

and level-sensitive.

If a new count is written during counting, the current count-

ing sequence will not be affected. If a trigger occurs after the

new count is written but before the current count expires, the

Counter will be loaded with new count on the next CLK pulse

and counting will continue from there.

4-11

82C54

Counter

New counts are loaded and Counters are decremented on

the falling edge of CLK.

MODE

MIN COUNT

MAX COUNT

0

1

2

3

4

5

1

2

1

0

16

The largest possible initial count is 0; this is equivalent to 2

for binary counting and 10 for BCD counting.

4

The counter does not stop when it reaches zero. In Modes 0,

1, 4, and 5 the Counter “wraps around” to the highest count,

either FFFF hex for binary counting or 9999 for BCD count-

ing, and continues counting. Modes 2 and 3 are periodic; the

Counter reloads itself with the initial count and continues

counting from there.

0

4

16

NOTE: 0 is equivalent to 2 for binary counting and 10 for BCD

counting.

SIGNAL

STATUS

MODES

LOW OR

GOING LOW

FIGURE 16. MINIMUM AND MAXIMUM INITIAL COUNTS

RISING

HIGH

0

1

Disables Counting

-

Enables Counting

-

1) Initiates

Counting

2) Resets output

after next clock

2

3

1) Disables

counting

2) Sets output im-

mediately high

Initiates Counting Enables Counting

1) Disables

Initiates Counting Enables Counting

counting

2) Sets output im-

mediately high

4

5

1) Disables

Counting

-

Enables Counting

-

Initiates Counting

FIGURE 15. GATE PIN OPERATIONS SUMMARY

4-12

82C54

Absolute Maximum Ratings

Thermal Information

o

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V Thermal Resistance (Typical)

θ_JA( C/W) θ_JC( C/W)

Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.5V to V

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

+0.5V

CC

CERDIP Package . . . . . . . . . . . . . . . .

CLCC Package . . . . . . . . . . . . . . . . . .

PDIP Package . . . . . . . . . . . . . . . . . . .

PLCC Package . . . . . . . . . . . . . . . . . .

SOIC Package. . . . . . . . . . . . . . . . . . .

55

65

60

65

75

12

14

N/A

Operating Conditions

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Operating Temperature Range

o

Storage Temperature Range. . . . . . . . . . . . . . . . . .-65 C to +150 C

Maximum Junction Temperature Ceramic Package . . . . . . . +175 C

Maximum Junction Temperature Plastic Package. . . . . . . . . +150 C

Maximum Lead Temperature Package (Soldering 10s) . . . . +300 C

o

C82C54, C82C54-10, -12 . . . . . . . . . . . . . . . . . . . . 0 C to +70 C

o

I82C54, I82C54-10, -12 . . . . . . . . . . . . . . . . . . . . -40 C to +85 C

o

M82C54, M82C54-10, -12 . . . . . . . . . . . . . . . . . -55 C to +125 C

(PLCC and SOIC - Lean Tips Only)

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2250 Gates

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

)

o

DC Electrical Speciﬁcations

V

= +5.0V ± 10%, T = 0 C to +70 C (C82C54, C82C54-10, C82C54-12)

CC A

o

T = -40 C to +85 C (I82C54, I82C54-10, I82C54-12)

A

o

T = -55 C to +125 C (M82C54, M82C54-10, M82C54-12

A

SYMBOL

PARAMETER

MIN

2.0

2.2

-

MAX

UNITS

TEST CONDITIONS

C82C54, I82C54

VIH

Logical One Input Voltage

-

V

M82C54

VIL

Logical Zero Input Voltage

Output HIGH Voltage

0.8

-

V

VOH

3.0

V

IOH = -2.5mA

IOH = -100µA

IOL = +2.5mA

VIN = GND or V

V

-0.4

-

V

CC

VOL

II

Output LOW Voltage

Input Leakage Current

-

0.4

+1

V

-1

µA

CC

DIP Pins 9,11,14-16,18-23

IO

Output Leakage Current

-10

-

+10

10

µA

VOUT = GND or V

DIP Pins 1-8

CC

ICCSB

Standby Power Supply Current

V

= 5.5V, VIN = GND or V

,

CC

Outputs Open, Counters

Programmed

ICCOP

Operating Power Supply Current

-

10

mA

V

= 5.5V,

CC

CLK0 = CLK1 = CLK2 = 8MHz,

VIN = GND or V

Outputs Open

,

CC

o

Capacitance T = +25 C; All Measurements Referenced to Device GND, Note 1

A

SYMBOL

CIN

PARAMETER

Input Capacitance

TYP

20

UNITS

TEST CONDITIONS

FREQ = 1MHz

pF

COUT

CI/O

Output Capacitance

I/O Capacitance

20

FREQ = 1MHz

20

NOTE:

1. Not tested, but characterized at initial design and at major process/design changes.

4-13

82C54

o

AC Electrical Speciﬁcations V = +5.0V ± 10%, T = 0 C to +70 C (C82C54, C82C54-10, C82C54-12)

CC

A

o

T = -40 C to +85 C (I82C54, I82C54-10, I82C54-12)

A

o

T = -55 C to +125 C (M82C54, M82C54-10, M82C54-12)

A

82C54

82C54-10

82C54-12

TEST

SYMBOL

PARAMETER

MIN

MAX

MIN

MAX

MIN

MAX

UNITS CONDITIONS

READ CYCLE

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

TAR

Address Stable Before RD

CS Stable Before RD

Address Hold Time After RD

RD Pulse Width

30

0

-

25

0

-

25

0

-

ns

1

TSR

TRA

TRR

TRD

TAD

TDF

TRV

-

1

0

-

0

-

1

150

-

95

-

95

-

1

Data Delay from RD

120

210

85

-

85

185

65

-

85

185

65

-

1

Data Delay from Address

RD to Data Floating

-

5

2, Note 1

Command Recovery Time

200

165

WRITE CYCLE

(9)

TAW

TSW

TWA

TWW

TDW

TWD

TRV

Address Stable Before WR

CS Stable Before WR

0

-

0

-

0

-

ns

(10)

(11)

(12)

(13)

(14)

(15)

Address Hold Time After WR

WR Pulse Width

0

95

140

25

200

95

0

95

0

Data Setup Time Before WR

Data Hold Time After WR

Command Recovery Time

165

CLOCK AND GATE

TCLK Clock Period

TPWH High Pulse Width

TPWL Low Pulse Width

(16)

(17)

(18)

(19)

(20)

(21)

(22)

(23)

(24)

(25)

(26)

(27)

(28)

(29)

(30)

NOTE:

125

60

-

DC

-

100

30

40

-

DC

-

80

30

-

DC

-

ns

1

-

TR

TF

Clock Rise Time

25

-

25

-

25

-

Clock Fall Time

-

TGW

TGL

TGS

TGH

TOD

Gate Width High

50

-

50

40

50

-

50

40

50

-

1

Gate Width Low

-

Gate Setup Time to CLK

Gate Hold Time After CLK

Output Delay from CLK

-

150

120

260

55

40

100

240

55

40

100

240

55

40

TODG Output Delay from Gate

-

TWO

TWC

TWG

TCL

OUT Delay from Mode Write

CLK Delay for Loading

-

0

Gate Delay for Sampling

CLK Setup for Count Latch

-5

-40

-5

-40

-5

-40

1. Not tested, but characterized at initial design and at major process/design changes.

4-14

82C54

Timing Waveforms

A0 - A1

(9)

tAW

tWA (11)

CS

DATA BUS

WR

(10)

tSW

VALID

(13)

tDW

tWD (14)

(12)

tWW

FIGURE 17. WRITE

A0 - A1

CS

tRA (3)

tAR (1)

(2)

tSR

(4)

tRR

RD

(5)

tRD

(7)

tDF

(6)

tAD

DATA BUS

VALID

FIGURE 18. READ

(8) (15)

tRV

RD, WR

FIGURE 19. RECOVERY

COUNT

(SEE NOTE)

MODE

WR

(23)

tGS

tWC (28)

(16)

tCLK

(17)

tCL (30)

tPWH

(18)

tPWL

CLK

GATE

OUT

(19)

tR

tF (20)

tGS

(23)

tGH (24)

(21)

tGW

(24)

(22)

tGL

tGH

tOD (25)

(27)

tWO

tODG (26)

NOTE: LAST BYTE OF COUNT BEING WRITTEN

FIGURE 20. CLOCK AND GATE

4-15

82C54

Burn-In Circuits

MD 82C54 CERDIP

V

CC

C1

R1

R2

Q1

Q2

1

2

24

23

22

21

20

19

18

17

16

15

14

13

R1

Q3

VCC

GND

Q5

Q4

F2

VCC

GND

F9

3

4

R1

R2

V

CC

5

F10

F11

F12

F0

6

7

R3

R4

A

8

A

R1

9

Q8

F1

Q7

A

R2

R1

A

Q6

10

11

12

R1

GND

MR 82C54 CLCC

VCC

C1

Q3 VCC

R1 R1

VCC Q2 Q1 OPEN

R1 R1 R1

4

3

2

1

28 27 26

R1

R2

25

24

23

22

21

20

19

GND

OPEN

5

6

R1

R2

R5

R1

F9

F10

F11

F12

F0

GND

Q5

7

8

Q4

9

F2

10

11

VCC/2

OPEN

Q8

12 13 14 15 16 17 18

R5 R1

R5 R1 R2

VCC/2 Q6 GND

VCC/2 Q7 F1

OPEN

NOTES:

1. V

= 5.5V ± 0.5V

8. R4 = 1.8kΩ ±5%

9. R5 = 1.2kΩ ±5%

CC

2. GND = 0V

3. VIH = 4.5V ±10%

4. VIL = -0.2V to 0.4V

5. R1 = 47kΩ ±5%

6. R2 = 1.0kΩ ±5%

7. R3 = 2.7kΩ ±5%

10. C1 = 0.01µF Min

11. F0 = 100kHz ±10%

12. F1 = F0/2, F2 = F1/2, ...F12 = F11/2

4-16

82C54

Die Characteristics

DIE DIMENSIONS:

129mils x 155mils x 19mils

(3270µm x 3940µm x 483µm)

Thickness: Metal 1: 8kÅ ± 0.75kÅ

Metal 2: 12kÅ ± 1.0kÅ

GLASSIVATION:

METALLIZATION:

Type: Nitrox

Type: Si-Al-Cu

Thickness: 10kÅ ± 3.0kÅ

Metallization Mask Layout

82C54

D5

D6

D7

VCC

WR

RD

D4

D3

CS

A1

D2

D1

A0

CLK2

OUT2

GATE2

D0

CLK0

OUT0

GATE0

GND

OUT1

GATE1

CLK1

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

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型号:	ID82C54
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	THOMSON CONSUMER ELECTRONICS
包装说明：	DIP, DIP24,.6
Reach Compliance Code：	unknown
风险等级：	5.82
Is Samacsys：	N
JESD-30 代码：	R-XDIP-T24
端子数量：	24
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	CERAMIC
封装代码：	DIP
封装等效代码：	DIP24,.6
封装形状：	RECTANGULAR
封装形式：	IN-LINE
电源：	5 V
认证状态：	Not Qualified
子类别：	Analog Waveform Generation Functions
标称供电电压 (Vsup)：	5 V
表面贴装：	NO
技术：	CMOS
温度等级：	INDUSTRIAL
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
Base Number Matches：	1

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