IDT71016S15PHGI中文资料应用文章市场行情现货热卖使用介绍-中国IC网-芯三七

CMOS Static RAM

1 Meg (64K x 16-Bit)

IDT71016

Features

Description

◆

64K x 16 advanced high-speed CMOS Static RAM

TheIDT71016is a1,048,576-bithigh-speedStaticRAMorganized

as64Kx16.ItisfabricatedusingIDT’shigh-perfomance,high-reliability

CMOS technology. This state-of-the-art technology, combined with

innovativecircuitdesigntechniques,providesacost-effectivesolutionfor

high-speedmemoryneeds.

◆

Equal access and cycle times

– CommercialandIndustrial:12/15/20ns

One Chip Select plus one Output Enable pin

Bidirectional data inputs and outputs directly TTL-

◆

compatible

Low power consumption via chip deselect

Upper and Lower Byte Enable Pins

Commercial and industrial product available in 44-pin

TheIDT71016hasanoutputenablepinwhichoperatesasfastas7ns,

withaddress access times as fastas 12ns. Allbidirectionalinputs and

outputsoftheIDT71016areTTL-compatibleandoperationisfromasingle

5Vsupply. Fullystaticasynchronouscircuitryisused,requiringnoclocks

orrefreshforoperation.

◆

Plastic SOJ package and 44-pin TSOP package

TheIDT71016ispackagedinaJEDECstandard44-pinPlasticSOJ

and 44-pin TSOP Type II.

FunctionalBlockDiagram

Output

Enable

Buffer

OE

Address

Buffers

Row / Column

Decoders

A0 - A15

,

I/O 15

High

Byte

I/O

8

Chip

Enable

Buffer

CS

Buffer

I/O 8

Sense

Amps

and

Write

Drivers

16

64K x 16

Memory

Array

Write

Enable

Buffer

WE

I/O 7

I/O 0

Low

Byte

I/O

8

Buffer

BHE

BLE

Byte

Enable

Buffers

3210 drw 01

JANUARY 2004

1

DSC-3210/8

IDT71016, CMOS Static RAM

1 Meg (64K x 16-bit)

Commercial and Industrial Temperature Ranges

PinConfigurations

PinDescriptions

A0

- A15

Address Inputs

Input

I/O

A4

A3

A2

A1

A0

CS

1

A5

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

Chip Select

CS

2

A6

Write Enable

WE

OE

3

A7

Output Enable

High Byte Enable

Low Byte Enable

Data Input/Output

5.0V Power

4

OE

5

BHE

BLE

I/O 15

I/O 14

I/O 13

I/O 12

BHE

BLE

6

I/O 0

I/O 1

I/O 2

I/O 3

7

I/O0 - I/O15

8

9

VCC

Pwr

10

11

12

13

14

15

16

17

18

19

20

21

22

VSS

Ground

Gnd

SO44-1

SO44-2

VCC

VSS

3210 tbl 01

VSS

VCC

,

I/O 4

I/O 5

I/O 6

I/O 7

WE

I/O 11

I/O 10

I/O 9

I/O 8

NC

A15

A14

A13

A12

NC

A8

A9

A10

A11

NC

3210 drw 02

SOJ/TSOP

Top View

Truth Table ⁽¹⁾

CS

H

L

OE

X

L

WE

X

H

L

BLE

X

L

BHE

X

H

L

I/O

0

- I/O

7

I/O

8

- I/O15

Function

Deselected - Standby

LowByte Read

High Byte Read

Word Read

High-Z

DATAOUT

High-Z

L

H

L

DATAOUT

DATAOUT`

DATAIN

High-Z

L

DATAOUT

DATAIN

High-Z

L

X

H

X

L

Word Write

L

H

L

Low Byte Write

High Byte Write

Outputs Disabled

L

H

X

H

DATAIN

High-Z

L

H

X

H

High-Z

L

High-Z

3210 tbl 02

NOTE:

1. H = V^IH, L = VIL, X = Don't care.

6.422

IDT71016, CMOS Static RAM

1 Meg (64K x 16-bit)

Commercial and Industrial Temperature Ranges

Absolute Maximum Ratings⁽¹⁾

Recommended Operating

Temperature and Supply Voltage

Symbol

Rating

Value

Unit

Grade

Temperature

0°C to +70°C

–40°C to +85°C

GND

VCC

(2)

V

TERM

Terminal Voltage with

Respect to GND

-0.5 to +7.0

V

Commercial

Industrial

0V

5.0V ± 10%

TA

Operating Temperature

0 to +70

^oC

0V

5.0V ± 10%

3210 tbl 04

Temperature

Under Bias

-55 to +125

TBIAS

Recommended DC Operating

Conditions

Storage

-55 to +125

^oC

TSTG

Temperature

Symbol

Parameter

Supply Voltage

GND Ground

Min.

Typ.

Max.

5.5

0

Unit

V

P

T

Power Dissipation

DC Output Current

1.25

50

W

VCC

4.5

5.0

IOUT

mA

0

V

3210 tbl 03

NOTES:

____

V

IH

Input High Voltage

Input Low Voltage

2.2

V

DD +0.5

V

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operationofthe device atthese oranyotherconditions above those indicatedinthe

operationalsectionsofthisspecificationisnotimplied.Exposuretoabsolutemaximum

ratingconditionsforextendedperiodsmayaffectreliability.

VIL

-0.5⁽¹⁾

0.8

V

____

3210 tbl 05

NOTE:

1. VIL (min.) = –1.5V for pulse width less than tRC/2, once per cycle.

2. VTERM mustnotexceedVCC +0.5V.

Capacitance

(TA = +25° C, f = 1.0MHz, SOJ Package)

Symbol

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

IN = 3dV

OUT = 3dV

Max. Unit

CIN

V

6

7

pF

CI/O

V

pF

3210 tbl 06

NOTE:

1. This parameter is guaranteed by device characterization, but not production

tested.

DC Electrical Characteristics

(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Range)

Symbol

Parameter

Input Leakage Current

Test Conditions

CC = Max., VIN = GND to VCC

CC = Max., CS = VIH, VOUT = GND to VCC

OL = 8mA, VCC = Min.

OH = -4mA, VCC = Min.

Min.

Max.

Unit

µA

V

___

|ILI|

V

5

___

|ILO

|

Output Leakage Current

Output Low Voltage

Output High Voltage

V

VOL

I

0.4

___

VOH

I

2.4

V

3210 tbl 07

DC Electrical Characteristics⁽¹⁾

(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC–0.2V)

71016S12

71016S15

71016S20

Symbol

Parameter

Com'l.

Ind.

Com'l.

Ind.

Com'l.

Ind.

Unit

Dynamic Operating Current

210

180

170

mA

ICC

(2)

CS < VIL, Outputs Open, VCC = Max., f = fMAX

Standby Power Supply Current (TTL Level)

60

10

50

10

45

10

mA

I

SB

(2)

CS > VIH, Outputs Open, VCC = Max., F = fMAX

Standby Power Supply Current (CMOS Level)

10

ISB1

CS > VHC, Outputs Open, VCC = Max., f = 0⁽²⁾

VIN < VLC or VIN > VHC

3210 tbl 08

NOTES:

1. All values are maximum guaranteed values.

2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing .

6.42

3

IDT71016, CMOS Static RAM

1 Meg (64K x 16-bit)

Commercial and Industrial Temperature Ranges

AC Test Conditions

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

1.5ns

1.5V

Input Timing Reference Levels

Output Reference Levels

AC Test Load

1.5V

See Figure 1, 2 and 3

3210 tbl 09

AC Test Loads

5V

480Ω

255Ω

480Ω

OUT

DATA

OUT

DATA

30pF*

5pF*

255Ω

3210 drw 04

,

3210 drw 03

,

*Including jig and scope capacitance.

Figure 2. AC Test Load

Figure 1. AC Test Load

(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)

7

6

5

4

3

•

∆tAA,

t

ACS

(Typical, ns)

•

2

1

•

,

180

8 20 40 60 80 100 120 140 160

CAPACITANCE (pF)

200

3210 drw 05

Figure 3. Output Capacitive Derating

6.442

IDT71016, CMOS Static RAM

1 Meg (64K x 16-bit)

Commercial and Industrial Temperature Ranges

AC Electrical Characteristics (VCC = 5.0V ± 10%, Commercial and Industrial Range)

71016S12

71016S15

71016S20

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

____

t

RC

AA

ACS

Read Cycle Time

12

15

20

ns

___ _

____

t

Address Access Time

Chip Select Access Time

12

15

20

___ _

____

t

12

15

20

____

(1)

Chip Select Low to Output in Low-Z

Chip Select High to Output in High-Z

Output Enable Low to Output Valid

Output Enable Low to Output in Low-Z

4

5

tCLZ

___ _

____

(1)

6

8

ns

tCHZ

___ _

____

tOE

7

8

10

____

(1)

0

tOLZ

___ _

____

(1)

OHZ

Output Enable High to Output in High-Z

Output Hold from Address Change

Byte Enable Low to Output Valid

Byte Enable Low to Output in Low-Z

6

8

ns

t

____

tOH

4

5

___ _

____

tBE

7

8

10

(1)

BLZ

____

0

t

___ _

____

(1)

BHZ

Byte Enable High to Output in High-Z

6

8

ns

t

WRITE CYCLE

____

t

WC

AW

CW

BW

AS

WR

WP

DW

DH

Write Cycle Time

12

9

0

9

7

0

15

10

0

20

12

0

ns

t

Address Valid to End of Write

Chip Select Low to End of Write

Byte Enable Low to End of Write

Address Set-up Time

t

Address Hold from End of Write

Write Pulse Width

0

t

10

8

12

10

0

t

Data Valid to End of Write

Data Hold Time

t

0

(1)

OW

____

Write Enable High to Output in Low-Z

1

t

___ _

____

(1)

WHZ

Write Enable Low to Output in High-Z

6

8

ns

t

3210 tbl 10

NOTE:

1. This parameteris guaranteedwiththe ACLoad(Figure 2)bydevice characterization, butis notproductiontested.

Timing Waveform of Read Cycle No. 1^(1,2,3)

tRC

ADDRESS

tAA

tOH

DATAOUT VALID

DATAOUT

PREVIOUS DATAOUT VALID

3210 drw 06

,

NOTES:

1. WE is HIGH for Read Cycle.

2. Device is continuously selected, CS is LOW.

3. OE, BHE, and BLE are LOW.

6.42

5

IDT71016, CMOS Static RAM

1 Meg (64K x 16-bit)

Commercial and Industrial Temperature Ranges

Timing Waveform of Read Cycle No. 2⁽¹⁾

tRC

ADDRESS

tAA

t

OH

OE

(3)

tOE

tOHZ

,

(3)

tOLZ

CS

(2)

tACS

(3)

t

CHZ

tCLZ

BHE, BLE

(2)

(3)

t

BE

(3)

tBHZ

t

BLZ

DATAOUT

DATA_OUTVALID

3210 drw 07

NOTES:

1. WE is HIGH for Read Cycle.

2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter.

3. Transition is measured ±200mV from steady state.

Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)^(1,2,4)

tWC

ADDRESS

t

AW

CS

(2)

(5)

t

CW

tCHZ

tBW

BHE BLE

,

(5)

tWR

t

BHZ

t

WP

WE

t

AS

(5)

tWHZ

(5)

t

OW

(3)

DATAOUT

DATAIN

PREVIOUS DATA VALID

DATA VALID

tDH

,

t

DW

DATAIN VALID

3210 drw 08

NOTES:

1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.

2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and

data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the

minimum write pulse is as short as the specified tWP.

3. During this period, I/O pins are in the output state, and input signals must not be applied.

4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

5. Transition is measured ±200mV from steady state.

6.462

IDT71016, CMOS Static RAM

1 Meg (64K x 16-bit)

Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)^(1,4)

t

WC

ADDRESS

t

AW

CS

(2)

tAS

tCW

t

BW

BHE BLE

,

tWP

tWR

WE

,

DATAOUT

DATAIN

t

DH

t

DW

DATAIN VALID

3210 drw 9

Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)^(1,4)

t

WC

ADDRESS

t

AW

CS

BHE_,BLE

WE

(2)

t

CW

tAS

t

BW

t

WP

tWR

DATAOUT

DATAIN

t

DH

t

DW

DATAIN VALID

3210 drw 10

,

NOTES:

1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.

2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and

data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the

minimum write pulse is as short as the specified tWP.

3. During this period, I/O pins are in the output state, and input signals must not be applied.

4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

5. Transition is measured ±200mV from steady state.

6.42

7

IDT71016, CMOS Static RAM

1 Meg (64K x 16-bit)

Commercial and Industrial Temperature Ranges

OrderingInformation

IDT

71016

S

XX

XXX

X

Device

Type

Power

Speed

Package

Process/

Temperature

Range

Blank

I

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

Restricted hazardous

substance device.

G

Y

PH

400-mil SOJ (SO44-1)

400-mil TSOP Type II (SO44-2)

12

15

20

Speed in nanoseconds

3210 drw 11

6.482

IDT71016, CMOS Static RAM

1 Meg (64K x 16-bit)

Commercial and Industrial Temperature Ranges

DatasheetDocumentHistory

7/30/99

8/5/99

Updated to new format

Expressed commercial and industrial ranges on DC Electrical table

Pg. 3

Pg. 5

Removed Icc, ISB, and ISB1 values for S12 industrial speed

Expressed commercial and industrial ranges on AC Electrical table

Changed footnote #2 to commercial temperature only

Revised footnotes on Write Cycle No. 1 diagram

Revised footnotes on Write Cycle No. 2 and No. 3 diagrams

Removed SCD 2752 footnote

Pg. 6

Pg. 7

Pg. 8

Added commercial only for 12ns speed

8/13/99

9/30/99

08/09/00

02/01/01

01/30/04

Pg. 9

Pg. 3, 5, 8

Added Datasheet Document History

Added12nsindustrialtemperaturespeedgradeoffering

Notrecommendedfornewdesigns

Removed"Notrecommendedfornewdesigns"

Added"Restrictedhazardoussubstancedevice"toorderinformation.

Pg. 8

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

for Tech Support:

sramhelp@idt.com

800-544-7726

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.42

9

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