IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
Symbol
Name
I/O
Description
At the beginning of each long word transfer, one of four modes of byte-order
SW0, SW1 Port B byte swap
Select
I
(Port B) swapping is selected by SW0 and SW1. The four modes are no swap, byte
swap, word swap, and byte-word swap. Byte-order swapping is possible with
any bus-size selection.
W/RA
W/RB
Port A Write/Read
Select
I
A HIGH selects a write operation and a LOW selects a read operation on
port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the
high-impedance state when W/RA is HIGH.
Port B Write/Read
Select
I
A HIGH selects a write operation and a LOW selects a read operation on
port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the
high-impedance state when W/RB is HIGH.
SIGNAL DESCRIPTIONS
RESET
FIFO1 to the B0-B35 outputs by a LOW-to-HIGH transition of
The IDT723614 is reset by taking the reset (RST) input
LOW for at least four port A clock (CLKA) and four port B clock
(CLKB) LOW-to-HIGH transitions. The reset input can switch
asynchronously to the clocks. A device reset initializes the
internal read and write pointers of each FIFO and forces the
full flags (FFA, FFB) LOW, the empty flags (EFA, EFB) LOW,
the almost-empty flags (AEA, AEB) LOW and the almost-full
flags (AFA, AFB) HIGH. A reset also forces the mailbox flags
(MBF1, MBF2) HIGH. After a reset, FFA is set HIGH after two
LOW-to-HIGH transitions of CLKA and FFB is set HIGH after
two LOW-to-HIGH transitions of CLKB. The device must be
reset after power up before data is written to its memory.
A LOW-to-HIGH transition on the RST input loads the
almost-full and almost-empty offset register (X) with the val-
ues selected by the flag-select (FS0, FS1) inputs. The values
that can be loaded into the registers are shown in Table 1.
CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, EFB
is HIGH, and either SIZ0 or SIZ1 is LOW (see Table 3).
The setup and hold time constraints to the port clocks
fortheportchipselects(CSA,CSB)andwrite/readselects(W/
RA,W/RB)areonlyforenablingwriteandreadoperationsand
are not related to high-impedance control of the data outputs.
IfaportenableisLOWduringaclockcycle,theportchipselect
and write/read select can change states during the setup and
hold time window of the cycle.
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through two
flip-flop stages. This is done to improve flag reliability by
reducing the probability of metastable events on the output
when CLKA and CLKB operate asynchronously to one an-
other. EFA, AEA, FFA, and AFA are synchronized to CLKA.
EFB, AEB, FFB, and AFB are synchronized to CLKB. Tables
4 and 5 show the relationship of each port flag to FIFO1 and
FIFO2.
FIFO WRITE/READ OPERATION
The state of port A data A0-A35 outputs is controlled by
the port A chip select (CSA) and the port A write/read select
(W/RA). The A0-A35 outputs are in the high-impedance state
when either CSA or W/RA is HIGH. The A0-A35 outputs are
activewhenboth CSAandW/RAareLOW. Dataisloadedinto
FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition
of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH,
MBA is LOW, and FFA is HIGH. Data is read from FIFO2 to
the A0-A35 outputs by a LOW-to-HIGH transition of CLKA
whenCSA isLOW, W/RAisLOW, ENAisHIGH, MBAisLOW,
and EFA is HIGH (see Table 2).
EMPTY FLAGS (
,
)
EFA EFB
The empty flag of a FIFO is synchronized to the port clock
that reads data from its array. When the empty flag is HIGH,
new data can be read to the FIFO output register. When the
empty flag is LOW, the FIFO is empty and attempted FIFO
reads are ignored. When reading FIFO1 with a byte or word
size on port B, EFBis set LOW when the fourth byte or second
word of the last long word is read.
The read pointer of a FIFO is incremented each time a
new word is clocked to the output register. The state machine
that controls an empty flag monitors a write-pointer and read-
pointer comparator that indicates when the FIFO SRAM
status is empty, empty+1, or empty+2. A word written to a
FIFO can be read to the FIFO output register in a minimum of
three cycles of the empty flag synchronizing clock. Therefore,
an empty flag is LOW if a word in memory is the next data to
be sent to the FIFO output register and two cycles of the port
The port B control signals are identical to those of port A.
The state of the port B data (B0-B35) outputs is controlled by
the port B chip select (CSB) and the port B write/read select
(W/RB). The B0-B35 outputs are in the high-impedance state
when either CSB or W/RB is HIGH. The B0-B35 outputs are
activewhenboth CSBandW/RBareLOW. Dataisloadedinto
FIFO2 from the B0-B35 inputs on a LOW-to-HIGH transition
ofCLKBwhenCSBisLOW, W/RBisHIGH, ENBisHIGH,EFB
is HIGH, and either SIZ0 or SIZ1 is LOW. Data is read from
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