IDT723614L20PQF中文资料应用文章市场行情现货热卖使用介绍-中国IC网-芯三七

CMOS SyncBiFIFO

IDT723614

WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

Integrated Device Technology, Inc.

• Microprocessor interface control logic

FEATURES:

• Free-running CLKA and CLKB can be asynchronous or

coincident (simultaneous reading and writing of data on a

single clock edge is permitted)

• Two independent clocked FIFOs (64 x 36 storage

capacity each) buffering data in opposite directions

• Mailbox bypass Register for each FIFO

• Dynamic Port B bus sizing of 36-bits (long word), 18-bits

(word), and 9-bits (byte)

• Selection of Big- or Little-Endian format for word and

byte bus sizes

• EFA, FFA, AEA, and AFA flags synchronized by CLKA

• EFB, FFB, AEB, and AFB flags synchronized by CLKB

• Passive parity checking on each port

• Parity generation can be selected for each port

• Low-power advanced BiCMOS technology

• Supports clock frequencies up to 67 MHz

• Fast access times of 10 ns

• Available in 132-pin plastic quad flat package (PQF) or

space-saving 120-pin thin quad flat package (TQFP)

• Industrial temperature range (-40°C to +85°C) is avail-

able, tested to military electrical specifications

• Three modes of byte-order swapping on port B

• Programmable Almost-Full and Almost-Empty Flags

FUNCTIONAL BLOCK DIAGRAM

CLKA

CSA

W/RA

ENA

Port-A

Control

Logic

MBF1

MBA

Parity

Gen/Check

PEFB

Mail 1

Register

PGB

64 x 36

SRAM

36

RST

Device

Control

ODD/

EVEN

Read

Pointer

Write

Pointer

EFB

AEB

Status Flag

Logic

FFA

AFA

FIFO1

36

FS0

FS1

Programmable Flag

Offset Register

B

0-B35

A

0

- A35

FIFO2

FFB

Status Flag

Logic

EFA

AEA

AFB

Write

Pointer

Read

Pointer

36

64 x 36

SRAM

PGA

Mail 2

Register

Parity

Gen/Check

PEFA

MBF2

CLKB

Port-B

Control

Logic

CSB

W/RB

ENB

BE

SIZ0

SIZ1

SW0

SW1

3146 drw 01

The IDT logo is a registered trademark and SyncBiFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

MAY 1997

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

1997 Integrated Device Technology, Inc

DSC-3146/4

1

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

DESCRIPTION:

with any bus size selection. Communication between each

port can bypass the FIFOs via two 36-bit mailbox registers.

Each mailbox register has a flag to signal when new mail has

beenstored. Parityischeckedpassivelyoneachportandmay

beignoredifnotdesired. Paritygenerationcanbeselectedfor

data read from each port. Two or more devices can be used

in parallel to create wider data paths.

The IDT723614 is a clocked FIFO, which means each port

employs a synchronous interface. All data transfers through a

port are gated to the LOW-to-HIGH transition of a continuous

(free-running) port clock by enable signals. The clocks for

each port are independent of one another and can be asyn-

The IDT723614 is a monolithic, high-speed, low-power

BiCMOS bidirectional clocked FIFO memory. It supports

clock frequencies up to 67MHz and has read access times as

fastas10ns.Twoindependent64x36dual-portSRAMFIFOs

on board the chip buffer data in opposite directions. Each

FIFO has flags to indicate empty and full conditions and two

programmable flags (almost-full and almost-empty) to indi-

cate when a selected number of words is stored in memory.

FIFO data on port B can be input and output in 36-bit, 18-bit,

and 9-bit formats with a choice of big- or little-endian configu-

rations. Three modes of byte-order swapping are possible

PIN CONFIGURATIONS

GND

AEA

EFA

A0

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

GND

AEB

EFB

B0

*

A1

B1

A2

B2

GND

A3

GND

B3

A4

B4

A5

B5

A6

B6

VCC

A7

VCC

B7

A8

A9

B8

B9

GND

A10

A11

VCC

A12

A13

A14

GND

A15

A16

A17

A18

A19

A20

GND

A21

A22

A23

GND

B10

B11

VCC

B12

B13

B14

GND

B15

B16

B17

B18

B19

B20

GND

B21

B22

B23

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

3146 drw 02

*

Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.

PQFP (PQ132-1, order code: PQF)

TOP VIEW

NOTES:

1. NC - No internal connection.

2. Uses Yamaichi socket IC51-1324-828.

2

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

chronous or coincident. The enables for each port are ar- writesdatatoitsarray. Theemptyflag(EFA, EFB)andalmost-

ranged to provide a simple bidirectional interface between empty (AEA, AEB) flag of a FIFO are two stage synchronized

microprocessors and/or buses controlled by a synchronous to the port clock that reads data from its array.

interface. The IDT723614 is characterized for operation from 0°C to

The full flag (FFA, FFB) and almost-full flag (AFA, AFB) of 70°C.

a FIFO are two-stage synchronized to the port clock that

PIN CONFIGURATIONS (CONT.)

A

23

22

21

1

B

22

21

GND

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

2

3

GND

4

B

20

19

18

17

16

15

14

13

12

11

10

A

20

19

18

17

16

15

14

13

12

11

10

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

GND

B

V

B

9

8

7

CC

6

5

4

3

A

9

8

7

V

CC

A

6

5

4

3

GND

B

2

1

0

A

2

1

0

EFB

AEB

AFB

EFA

AEA

3146 drw 03

TQFP (PN120-1, order code: PF)

TOP VIEW

3

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION

Symbol

Name

I/O

O

Description

A0-A35 Port A Data

36-bit bidirectional data port for side A.

AEA

AEB

AFA

AFB

Port A Almost-Empty

Programmable almost-empty flag synchronized to CLKA. It is LOW when

Flag

(Port A) the number of 36-bit words in FIFO2 is less than or equal to the value in

the offset register, X.

Port B Almost-Empty

Flag

O

Programmable almost-empty flag synchronized to CLKB. It is LOW when the

(Port B) number of 36-bit words in FIFO1 is less than or equal to the value in the

offset register, X.

Port A Almost-Full

Flag

O

Programmable almost-full flag synchronized to CLKA. It is LOW when the

(Port A) number of 36-bit empty locations in FIFO1 is less than or equal to the value

in the offset register, X.

Port B Almost-Full

Flag

O

Programmable almost-full flag synchronized to CLKB. It is LOW when the

(Port B) number of 36-bit empty locations in FIFO2 is less than or equal to the value

in the offset register, X.

B0-B35 Port B Data.

I/O

I

36-bit bidirectional data port for side B.

BE

Big-endian select

Selects the bytes on port B used during byte or word data transfer. A LOW

on BEselects the most significant bytes on B0-B35 for use, and a HIGH

selects the least significant bytes

CLKA Port A Clock

CLKB Port B Clock

I

CLKA is a continuous clock that synchronizes all data transfers through port A

and can be asynchronous or coincident to CLKB. EFA, FFA, AFA, and AEA

are synchronized to the LOW-to-HIGH transition of CLKA.

CLKB is a continuous clock that synchronizes all data transfers through port B

and can be asynchronous or coincident to CLKA. Port B byte swapping and

data port sizing operations are also synchronous to the LOW-to-HIGH transi-

tion of CLKB. EFB, FFB, AFB, and AEB are synchronized to the LOW-to-HIGH

transition of CLKB.

CSA

CSB

EFA

Port A Chip Select

I

CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or

write data on port A. The A0-A35 outputs are in the high-impedance state

when CSA is HIGH.

Port B Chip Select

Port A Empty Flag

CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or

write data on port B. The B0-B35 outputs are in the high-impedance state

when CSB is HIGH.

O

EFA is synchronized to the LOW-to-HIGH transition of CLKA. When EFA is

(Port A) LOW, FIFO2 is empty, and reads from its memory are disabled. Data can

be read from FIFO2 to the output register when EFA is HIGH. EFA is forced

LOW when the device is reset and is set HIGH by the second LOW-to-HIGH

transition of CLKA after data is loaded into empty FIFO2 memory.

EFB

Port B Empty Flag

O

EFB is synchronized to the LOW-to-HIGH transition of CLKB. When EFB is

(Port B) LOW, the FIFO1 is empty, and reads from its memory are disabled. Data can

be read from FIFO1 to the output register when EFB is HIGH. EFB is forced

LOW when the device is reset and is set HIGH by the second LOW-to-HIGH

transition of CLKB after data is loaded into empty FIFO1 memory.

ENA

ENB

FFA

Port A Enable

Port B Enable

Port A Full Flag

I

ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or

write data on port A.

I

ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or

write data on port B.

O

FFA is synchronized to the LOW-to-HIGH transition of CLKA. When FFA is

(Port A) LOW, FIFO1 is full, and writes to its memory are disabled. FFA is forced LOW

when the device is reset and is set HIGH by the second LOW-to-HIGH transi-

tion of CLKA after reset.

FFB

Port B Full Flag

O

FFB is synchronized to the LOW-to-HIGH transition of CLKB. When FFB is

(Port B) LOW, FIFO2 is full, and writes to its memory are disabled. FFB is forced LOW

when the device is reset and is set HIGH by the second LOW-to-HIGH transi-

tion of CLKB after reset.

4

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION (CONTINUED)

Symbol

Name

I/O

Description

`FS1, FS0 Flag-Offset Selects

I

The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which

selects one of four preset values for the almost-full flag and almost-empty flag

offset.

MBA

Port A Mailbox

Select

I

A HIGH level on MBA chooses a mailbox register for a port A read or write

operation. When the A0-A35 outputs are active, a HIGH level on MBA selects

data from the mail2 register for output, and a LOW level selects FIFO2 output

register data for output.

MBF1

Mail1 Register Flag

Mail2 Register Flag

O

MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the

mail1 register. Writes to the mail1 register are inhibited while MBF1 is set LOW.

MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port B read is

selected and both SIZ1 and SIZ0 are HIGH. MBF1 is set HIGH when the device

is reset.

MBF2

O

MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the

mail2 register. Writes to the mail2 register are inhibited while MBF2 is set LOW.

MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a port A read is

selected and MBA is HIGH. MBF2 is set HIGH when the device is reset.

ODD/

EVEN

Odd/Even Parity

Select

I

Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is

checked when ODD/EVEN is LOW. ODD/EVEN also selects the type of parity

generated for each port if parity generation is enabled for a readoperation.

PEFA

PEFB

Port A Parity Error

Flag

O

When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes are

(Port A) organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant

bit of each byte serving as the parity bit. The type of parity checked is deter

mined by the state of the ODD/EVEN input.

The parity trees used to check the A0-A35 inputs are shared by the mail2 register

to generate parity if parity generation is selected by PGA. Therefore, if a mail2

read parity generation is setup by having W/RA LOW, MBA HIGH, and PGA

HIGH, the PEFA flag is forced HIGH regardless of the A0-A35 inputs.

Port B Parity Error

Flag

O

When any valid byte applied to terminals B0-B35 fails parity, PEFB is LOW. Bytes

(Port B) are organized as B0-B8, B9-B17, B18-B26, B27-B35 with the most significant bit

of each byte serving as the parity bit. A byte is valid when it is used by the bus

size selected for Port B. The type of parity checked is determined by the state of

the ODD/EVEN input.

The parity trees used to check the B0-B35 inputs are sharedby the mail 1 register to

generate parity if parity generation isselected by PGB. Therefore, if a mail1 read

with parity generation is setup by having W/RB LOW, SIZ1 and SIZ0 HIGH, and

PGB HIGH, the PEFB flag is forced HIGH regardless of the state of the B0-B35

inputs.

PGA

PGB

RST

Port A Parity

Generation

I

Parity is generated for data reads from port A when PGA is HIGH. The type of

parity generated is selected by the state of the ODD/EVEN input. Bytes are

organized as A0-A8, A9-A17, A18-A26, and A27-A35. The generated parity

bits are output in the most significant bit of each byte.

Port B Parity

Generation

Parity is generated for data reads from port B when PGB is HIGH. The type

of parity generated is selected by the state of the ODD/EVEN input. Bytes are

organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity

bits are output in the most significant bit of each byte.

Reset

To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-

HIGH transitions of CLKB must occur while RSTis LOW. This sets the AFA,

AFB, MBF1, and MBF2 flags HIGH and the EFA, EFB, AEA, AEB, FFA, and

FFB flags LOW. The LOW-to-HIGH transition of RST latches the status of the

FS1 and FS0 inputs to select almost-full and almost-empty flag offsets

SIZ0, SIZ1 Port B bus size

selects

I

A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and BE, and

(Port B) the following LOW-to-HIGH transition of CLKB implements the latched states as a

port B bus size. Port B bus sizes can be long word, word, or byte. A high on both

SIZ0 and SIZ1 accesses the mailbox reegisters for a port B 36-bit write or read.

5

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION (CONTINUED)

Symbol

Name

I/O

Description

At the beginning of each long word transfer, one of four modes of byte-order

SW0, SW1 Port B byte swap

Select

I

(Port B) swapping is selected by SW0 and SW1. The four modes are no swap, byte

swap, word swap, and byte-word swap. Byte-order swapping is possible with

any bus-size selection.

W/RA

W/RB

Port A Write/Read

Select

I

A HIGH selects a write operation and a LOW selects a read operation on

port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the

high-impedance state when W/RA is HIGH.

Port B Write/Read

Select

I

A HIGH selects a write operation and a LOW selects a read operation on

port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the

high-impedance state when W/RB is HIGH.

SIGNAL DESCRIPTIONS

RESET

FIFO1 to the B0-B35 outputs by a LOW-to-HIGH transition of

The IDT723614 is reset by taking the reset (RST) input

LOW for at least four port A clock (CLKA) and four port B clock

(CLKB) LOW-to-HIGH transitions. The reset input can switch

asynchronously to the clocks. A device reset initializes the

internal read and write pointers of each FIFO and forces the

full flags (FFA, FFB) LOW, the empty flags (EFA, EFB) LOW,

the almost-empty flags (AEA, AEB) LOW and the almost-full

flags (AFA, AFB) HIGH. A reset also forces the mailbox flags

(MBF1, MBF2) HIGH. After a reset, FFA is set HIGH after two

LOW-to-HIGH transitions of CLKA and FFB is set HIGH after

two LOW-to-HIGH transitions of CLKB. The device must be

reset after power up before data is written to its memory.

A LOW-to-HIGH transition on the RST input loads the

almost-full and almost-empty offset register (X) with the val-

ues selected by the flag-select (FS0, FS1) inputs. The values

that can be loaded into the registers are shown in Table 1.

CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, EFB

is HIGH, and either SIZ0 or SIZ1 is LOW (see Table 3).

The setup and hold time constraints to the port clocks

fortheportchipselects(CSA,CSB)andwrite/readselects(W/

RA,W/RB)areonlyforenablingwriteandreadoperationsand

are not related to high-impedance control of the data outputs.

IfaportenableisLOWduringaclockcycle,theportchipselect

and write/read select can change states during the setup and

hold time window of the cycle.

SYNCHRONIZED FIFO FLAGS

Each FIFO is synchronized to its port clock through two

flip-flop stages. This is done to improve flag reliability by

reducing the probability of metastable events on the output

when CLKA and CLKB operate asynchronously to one an-

other. EFA, AEA, FFA, and AFA are synchronized to CLKA.

EFB, AEB, FFB, and AFB are synchronized to CLKB. Tables

4 and 5 show the relationship of each port flag to FIFO1 and

FIFO2.

FIFO WRITE/READ OPERATION

The state of port A data A0-A35 outputs is controlled by

the port A chip select (CSA) and the port A write/read select

(W/RA). The A0-A35 outputs are in the high-impedance state

when either CSA or W/RA is HIGH. The A0-A35 outputs are

activewhenboth CSAandW/RAareLOW. Dataisloadedinto

FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition

of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH,

MBA is LOW, and FFA is HIGH. Data is read from FIFO2 to

the A0-A35 outputs by a LOW-to-HIGH transition of CLKA

whenCSA isLOW, W/RAisLOW, ENAisHIGH, MBAisLOW,

and EFA is HIGH (see Table 2).

EMPTY FLAGS (

,

)

EFA EFB

The empty flag of a FIFO is synchronized to the port clock

that reads data from its array. When the empty flag is HIGH,

new data can be read to the FIFO output register. When the

empty flag is LOW, the FIFO is empty and attempted FIFO

reads are ignored. When reading FIFO1 with a byte or word

size on port B, EFBis set LOW when the fourth byte or second

word of the last long word is read.

The read pointer of a FIFO is incremented each time a

new word is clocked to the output register. The state machine

that controls an empty flag monitors a write-pointer and read-

pointer comparator that indicates when the FIFO SRAM

status is empty, empty+1, or empty+2. A word written to a

FIFO can be read to the FIFO output register in a minimum of

three cycles of the empty flag synchronizing clock. Therefore,

an empty flag is LOW if a word in memory is the next data to

be sent to the FIFO output register and two cycles of the port

The port B control signals are identical to those of port A.

The state of the port B data (B0-B35) outputs is controlled by

the port B chip select (CSB) and the port B write/read select

(W/RB). The B0-B35 outputs are in the high-impedance state

when either CSB or W/RB is HIGH. The B0-B35 outputs are

activewhenboth CSBandW/RBareLOW. Dataisloadedinto

FIFO2 from the B0-B35 inputs on a LOW-to-HIGH transition

ofCLKBwhenCSBisLOW, W/RBisHIGH, ENBisHIGH,EFB

is HIGH, and either SIZ0 or SIZ1 is LOW. Data is read from

6

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

clockthatreadsdatafromtheFIFOhavenotelapsedsincethe FULL FLAG (

,

)

FFA FFB

time the word was written. The empty flag of the FIFO is set

The full flag of a FIFO is synchronized to the port clock

HIGH by the second LOW-to-HIGH transition of the synchro- that writes data to its array. When the full flag is HIGH, a

nizing clock, and the new data word can be read to the FIFO memory location is free in the SRAM to receive new data. No

output register in the following cycle.

memory locations are free when the full flag is LOW and

A LOW-to-HIGH transition on an empty flag synchroniz- attempted writes to the FIFO are ignored.

ing clock begins the first synchronization cycle of a write if the

Each time a word is written to a FIFO, the write pointer is

clocktransitionoccursattimetSKEW1 orgreaterafterthewrite. incremented. The state machine that controls a full flag

Otherwise, the subsequent clock cycle can be the first syn- monitors a write-pointer and read-pointer comparator that

chronization cycle (see Figure 13 and 14).

indicates when the FIFO SRAM status is full, full-1, or full-2.

From the time a word is read from a FIFO, the previous

memory location is ready to be written in a minimum of three

cyclesofthefullflagsynchronizingclock. Therefore,afullflag

is LOW if less than two cycles of the full flag synchronizing

clock have elapsed since the next memory write location has

been read. The second LOW-to-HIGH transition on the full

flag synchronization clock after the read sets the full flag

HIGH and the data can be written in the following clock cycle.

A LOW-to-HIGH transition on a full flag synchronizing

clock begins the first synchronization cycle of a read if the

clocktransitionoccursattimetSKEW1 orgreateraftertheread.

Otherwise, the subsequent clock cycle can be the first syn-

chronization cycle (see Figure 15 and 16).

TABLE 1: FLAG PROGRAMMING

ALMOST-FULL AND

FS1

FS0

ALMOST-EMPTY FLAG

OFFSET REGISTER (X)

RST

H

L

H

L

↑

16

12

8

H

L

4

TABLE 2: PORT-A ENABLE FUNCTION TABLE

W/ A

ENA

X

MBA

X

CLKA

A0-A35 Outputs

Port Functions

CSA

H

L

R

X

H

L

X

↑

In High-Impedance State

Active, FIFO2 Output Register

Active, Mail2 Register

None

L

X

L

H

L

FIFO1 Write

Mail1 Write

L

H

↑

L

X

↑

None

L

H

L

FIFO2 Read

None

L

H

X

↑

L

H

Active, Mail2 Register

Mail2 Read (Set MBF2 HIGH)

TABLE 3: PORT-B ENABLE FUNCTION TABLE

W/ B ENB

SIZ1, SIZ0

X

CLKB

B0-B35 Outputs

In High-Impedance State

Active, FIFO1 Output Register

Active, Mail1 Register

Port Functions

CSB

H

L

R

X

H

L

X

L

X

↑

None

X

L

H

L

One, both LOW

Both HIGH

One, both LOW

Both HIGH

FIFO2 Write

Mail2 Write

None

L

↑

L

X

↑

L

H

L

FIFO1 read

None

L

X

↑

L

H

Active, Mail1 Register

Mail1 Read (Set MBF1 HIGH)

7

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

ALMOST EMPTY FLAGS (

,

)

AEA AEB

more long words in memory and is HIGH when the FIFO

contains [64-(X+1)] or less long words.

The almost-empty flag of a FIFO is synchronized to the

port clock that reads data from its array. The state machine

that controls an almost-empty flag monitors a write-pointer

and a read-pointer comparator that indicates when the FIFO

SRAM status is almost empty, almost empty+1, or almost

empty+2. The almost-empty state is defined by the value of

the almost-full and almost-empty offset register (X). This

register is loaded with one of four preset values during a

devicereset(seeResetabove). Analmost-emptyflagisLOW

when the FIFO contains X or less long words in memory and

is HIGH when the FIFO contains (X+1) or more long words.

Two LOW-to-HIGH transitions of the almost-empty flag

synchronizing clock are required after a FIFO write for the

almost-empty flag to reflect the new level of fill. Therefore, the

almost-empty flag of a FIFO containing (X+1) or more long

words remains LOW if two cycles of the synchronizing clock

have not elapsed since the write that filled the memory to the

(X+1) level. An almost-empty flag is set HIGH by the second

LOW-to-HIGH transition of the synchronizing clock after the

FIFO write that fills memory to the (X+1) level. A LOW-to-

HIGH transition of an almost-empty flag synchronizing clock

beginsthefirstsynchronizationcycleifitoccursattimetSKEW2

orgreaterafterthewritethatfillstheFIFOto(X+1)longwords.

Otherwise, the subsequent synchronizing clock cycle can be

the first synchronization cycle (see Figure 17 and 18).

Two LOW-to-HIGH transitions of the almost-full flag

synchronizing clock are required after a FIFO read for the

almost-full flag to reflect the new level of fill. Therefore, the

almost-full flag of a FIFO containing [64-(X+1)] or less words

remainsLOWiftwocyclesofthesynchronizingclockhavenot

elapsed since the read that reduced the number of long words

in memory to [64-(X+1)]. An almost-full flag is set HIGH by the

second LOW-to-HIGH transition of the synchronizing clock

after the FIFO read that reduces the number of long words in

memory to [64-(X+1)]. A LOW-to-HIGH transition of an

almost-full flag synchronizing clock begins the first synchroni-

zation cycle if it occurs at time tSKEW2 or greater after the read

that reduces the number of long words in memory to [64-

(X+1)]. Otherwise, the subsequent synchronizing clock cycle

can be the first synchronization cycle (see Figure 19 and 20).

MAILBOX REGISTERS

EachFIFOhasa36-bitbypassregistertopasscommand

and control information between port A and port B without

putting it in queue. The mailbox-select (MBA, MBB) inputs

choose between a mail register and a FIFO for a port data

transferoperation. ALOW-to-HIGHtransitiononCLKAwrites

A0-A35 data to the mail1 register when a port A write is

selected by CSA, W/RA, and ENA with MBA HIGH. A LOW-

to-HIGH transition on CLKB writes B0-B35 data to the mail2

register when a port B write is selected by CSB, W/RB, and

ENB with both SIZ1 and SIZ0 HIGH. Writing data to a mail

register sets the corresponding flag (MBF1 or MBF2) LOW.

Attempted writes to a mail register are ignored while the mail

flag is LOW.

ALMOST FULL FLAGS (

,

)

AFA AFB

The almost-full flag of a FIFO is synchronized to the port

clock that writes data to its array. The state machine that

controls an almost-full flag monitors a write-pointer and read-

pointer comparator that indicates when the FIFO SRAM

status is almost full, almost full-1, or almost full-2. The almost-

full state is defined by the value of the almost-full and almost-

empty offset register (X). This register is loaded with one of

four preset values during a device reset (see Reset above).

An almost-full flag is LOW when the FIFO contains (64-X) or

When the port A data outputs (A0-A35) are active, the

data on the bus comes from the FIFO2 output register when

MBA is LOW and from the mail2 register when MBA is HIGH.

When the port B data outputs (B0-B35) are active, the data on

thebuscomesfromtheFIFO1outputregisterwheneitherone

TABLE 4: FIFO1 FLAG OPERATION

Synchronized Synchronized

TABLE 5: FIFO2 FLAG OPERATION

Synchronized Synchronized

Number of 36-Bit

Words in the FIFO1⁽¹⁾

to CLKB

EFB AEB

to CLKA

AFA FFA

Number of 36-Bit

Words in the FIFO2⁽¹⁾

to CLKA

EFA AEA

to CLKB

AFB FFB

0

1 to X

L

H

L

H

L

0

1 to X

L

H

L

H

L

H

L

H

(X+1) to [64-(X+1)]

(64-X) to 63

64

H

(X+1) to [64-(X+1)]

(64-X) to 63

64

H

L

NOTE:

1. X is the value in the almost-empty flag and almost-full flag offset register.

8

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE

(UNLESS OTHERWISE NOTED)⁽¹⁾

Symbol

VCC

VI⁽²⁾

Rating

Commercial

-0.5 to 7

-0.5 to VCC+0.5

±20

Unit

V

Supply Voltage Range

Input Voltage Range

Output Voltage Range

V

VO⁽²⁾

V

IIK

Input Clamp Current, (VI < 0 or VI > VCC)

Output Clamp Current, (VO < 0 or VO > VCC)

Continuous Output Current, (VO = 0 to VCC)

Continuous Current Through VCC or GND

Operating Free Air Temperature Range

Storage Temperature Range

mA

°C

IOK

±50

IOUT

ICC

±50

±500

TA

0 to 70

TSTG

NOTES:

-65 to 150

1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and

functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

Symbol

VCC

VIH

Parameter

Min. Max. Unit

Supply Voltage

4.5

2

5.5

–

V

HIGH Level Input Voltage

LOW-Level Input Voltage

HIGH-Level Output Current

LOW-Level Output Current

VIL

–

0.8

-4

V

IOH

IOL

–

mA

°C

–

8

TA

Operating Free-air

Temperature

0

70

ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR

TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)

Parameter

VOH

Test Conditions

IOH = -4 mA

IOL = 8 mA

Min. Typ.⁽¹⁾

Max. Unit

VCC = 4.5V,

VCC = 4.5 V,

VCC = 5.5 V,

VI = 0,

2.4

V

VOL

0.5

±50

1

V

II

VI = VCC or 0

VO = VCC or 0

IO = 0 mA,

µA

mA

pF

IOZ

ICC

VI = VCC or GND

CIN

f = 1 MHz

4

8

COUT

VO = 0,

f = 1 MHZ

NOTE:

1 . All typical values are at VCC = 5 V, TA = 25°C.

9

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE

AND OPERATING FREE-AIR TEMPERATURE (See Figures 4 through 26)

IDT723614L15 IDT723614L20 IDT723614L30

Symbol

fS

Parameter

Min. Max. Min. Max.

Min. Max.

Unit

MHz

ns

Clock Frequency, CLKA or CLKB

Clock Cycle Time, CLKA or CLKB

Pulse Duration, CLKA and CLKB HIGH

Pulse Duration, CLKA and CLKB LOW

–

15

6

66.7

–

20

8

50

–

33.4

tCLK

–

30

12

6

–

tCLKH

tCLKL

tDS

–

ns

6

8

–

ns

Setup Time, A0-A35 before CLKA↑ and B0-B35

before CLKB↑

4

5

–

ns

tENS

Setup Time, CSA, W/RA, ENA and MBA before

5

–

5

–

6

–

ns

CLKA↑; CSB,W/RB and ENB before CLKB↑

tSZS

tSWS

tPGS

Setup Time, SIZ0, SIZ1,and BE before CLKB↑

Setup Time, SW0 and SW1 before CLKB↑

Setup Time, ODD/EVEN and PGA before

CLKA↑; ODD/EVEN and PGB before CLKB↑⁽¹⁾

4

5

4

–

5

7

5

–

6

8

6

–

ns

tRSTS

Setup Time, RST LOW before CLKA↑

or CLKB↑⁽²⁾

5

–

6

–

7

–

ns

tFSS

tDH

Setup Time, FS0 and FS1 before RST HIGH

5

1

–

6

1

–

7

1

–

ns

Hold Time, A0-A35 after CLKA↑ and B0-B35

after CLKB↑

tENH

Hold Time, CSA, W/RA, ENA and MBA after

1

–

1

–

1

–

ns

CLKA↑; CSB, W/RB, and ENB after CLKB↑

tSZH

tSWH

tPGH

Hold Time, SIZ0, SIZ1, and BE after CLKB↑

Hold Time, SW0 and SW1 after CLKB↑

2

0

–

2

0

–

2

0

–

ns

Hold Time, ODD/EVEN and PGA after CLKA↑;

ODD/EVEN and PGB after CLKB↑⁽¹⁾

tRSTH

tFSH

Hold Time, RST LOW after CLKA↑ or CLKB↑⁽²⁾

5

4

8

–

6

4

8

–

7

4

–

ns

Hold Time, FS0 and FS1 after RST HIGH

tSKEW1⁽³⁾Skew Time, between CLKA↑ and CLKB↑

10

for EFA, EFB, FFA, and FFB

tSKEW2⁽³⁾Skew Time, between CLKA↑ and CLKB↑

9

–

16

–

20

–

ns

for AEA, AEB, AFA, and AFB

NOTES:

1.

2.

3.

Only applies for a clock edge that does a FIFO read.

Requirement to count the clock edge as one of at least four needed to reset a FIFO.

Skew time is not a timimg constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and

CLKB cycle.

10

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE

AND OPERATING FREE-AIR TEMPERATURE, CL = 30pF (See Figures 4 through 26)

IDT723614L15 IDT723614L20 IDT723614L30

Symbol

Parameter

Min. Max. Min. Max.

Min. Max.

Unit

tA

Access Time, CLKA↑ to A0-A35 and CLKB↑

to B0-B35

2

1

10

9

2

1

12

2

1

15

ns

tWFF

tREF

tPAE

tPAF

tPMF

Propagation Delay Time, CLKA↑ to FFA and

CLKB↑ to FFB

ns

Propagation Delay Time, CLKA↑ to EFA and

and CLKB↑ to EFB

Propagation Delay Time, CLKA↑ to AEA and

CLKB↑ to AEB

Propagation Delay Time, CLKA↑ to AFA and

CLKB↑ to AFB

Propagation Delay Time, CLKA↑ to MBF1 LOW

or MBF2 HIGH and CLKB↑ to MBF2 LOW or

MBF1 HIGH

tPMR

Propagation Delay Time, CLKA↑ to B0-B35⁽¹⁾

and CLKB↑ to A0-A35⁽²⁾

3

11

3

13

3

15

ns

tPPE⁽³⁾

tMDV

Propagation delay time, CLKB↑ to PEFB

2

1

11

2

1

12

2

1

13

12

ns

Propagation Delay Time, MBA to A0-A35 valid

and SIZ1, SIZ0 to B0-B35 valid

11. 5

tPDPE

Propagation Delay Time, A0-A35 valid to PEFA

valid; B0-B35 valid to PEFB valid

3

2

10

11

3

2

11

12

3

2

13

14

ns

tPOPE

tPOPB⁽⁴⁾

Propagation Delay Time, ODD/EVEN to PEFA

and PEFB

Propagation Delay Time, ODD/EVEN to parity

bits (A8, A17, A26, A35) and (B8, B17, B26,

B35)

tPEPE

Propagation Delay Time, CSA, ENA,W/RA,

MBA, or PGA to PEFA; CSB, ENB, W/RB, SIZ1,

SIZ0, or PGB to PEFB

1

3

11

12

1

3

12

13

1

3

14

ns

tPEPB⁽⁴⁾

Propagation Delay Time, CSA, ENA, W/RA,

MBA, or PGA to parity bits (A8, A17, A26, A35);

CSB, ENB, W/RB,SIZ1, SIZ0, or PGB to parity

bits (B8, B17, B26, B35)

tRSF

tEN

Propagation Delay Time, RST to (MBF1, MBF2)

HIGH

1

2

15

10

1

2

20

12

1

2

30

14

ns

Enable Time, CSA and W/RA LOW to A0-A35

active and CSB LOW and W/RB HIGH to

B0-B35 active

tDIS

Disable Time, CSA or W/RA HIGH to A0-A35

at high impedance and CSB HIGH or W/RB

LOW to B0-B35 at high impedance

1

8

1

9

1

11

ns

NOTES:

1.

2.

3.

4.

Writing data to the mail1 register when the B0-B35 outputs are active and SIZ1, SIZ0 are HIGH.

Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.

Only applies when a new port B bus size is implemented by the rising CLKB edge.

Only applies when reading data from a mail register.

11

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

A35—A27

A26—A18

A17—A9

A8—A0

Write to FIFO1/

Read From FIFO2

BYTE ORDER ON PORT A:

D

A

B

C

B35—B27 B26—B18 B17—B9

B8—B0

Read from FIFO1/

Write to FIFO2

SIZ1 SIZ0

BE

D

A

B

C

X

L

(a) LONG WORD SIZE

B35—B27 B26—B18 B17—B9

B8—B0

SIZ1 SIZ0

BE

1st: Read from FIFO1/

Write to FIFO2

B

A

L

H

B35—B27 B26—B18 B17—B9

2nd: Read from FIFO1/

Write to FIFO2

C

D

(b) WORD SIZE — BIG ENDIAN

B35—B27 B26—B18 B17—B9

B8—B0

SIZ1 SIZ0

BE

1st: Read from FIFO1/

Write to FIFO2

C

D

H

L

H

B35—B27 B26—B18 B17—B9

B8—B0

2nd: Read from FIFO1/

Write to FIFO2

A

B

(c) WORD SIZE — LITTLE ENDIAN

B35—B27 B26—B18 B17—B9

B8—B0

SIZ1 SIZ0

BE

1st: Read from FIFO1/

Write to FIFO2

A

L

H

L

B35—B27 B26—B18 B17—B9

2nd: Read from FIFO1/

Write to FIFO2

B

B35—B27 B26—B18 B17—B9

B8—B0

3rd: Read from FIFO1/

Write to FIFO2

C

B35—B27 B26—B18 B17—B9

4th: Read from FIFO1/

Write to FIFO2

D

3146 drw fig 01

(d) BYTE SIZE — BIG ENDIAN

Figure 1. Dynamic Bus Sizing

12

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

B35—B27

B26—B18 B17—B9

B8—B0

SIZ1 SIZ0

BE

1st: Read from FIFO1/

Write to FIFO2

D

H

L

B35—B27

B26—B18 B17—B9

B8—B0

2nd: Read from FIFO1/

Write to FIFO2

C

B8—B0

B

3rd: Read from FIFO1/

Write to FIFO2

B35—B27

B26—B18 B17—B9

B8—B0

4th: Read from FIFO1/

Write to FIFO2

A

(d) BYTE SIZE — LITTLE ENDIAN

3146 drw fig 01a

Figure 1. Dynamic Bus Sizing (continued)

DESCRIPTION (CONTINUED)

or both SIZ1 and SIZ0 are LOW and from the mail2 register

when both SIZ1 and SIZ0 are HIGH.The mail1 register flag

(MBF1) is set HIGH by a rising CLKB edge when a port B read

is selected by CSB, W/RB, and ENB with both SIZ1 and SIZ0

HIGH. The mail2 register flag (MBF2) is set HIGH by a LOW-

to-HIGH transition on CLKA when port A read is selected by

CSA, W/RA, and ENA and MBA is HIGH. The data in the mail

register remains intact after it is read and changes only when

new data is written to the register.

byte or word size is implemented on port B, only the first one

or two bytes appear on the selected portion of the FIFO1

outputregister, withtherestofthelongwordstoredinauxiliary

registers. Inthiscase, subsequentFIFO1readswiththesame

bus-sizeimplementationoutputtherestofthelongwordtothe

FIFO1 output register in the order shown by Figure1.

Each FIFO1 read with a new bus-size implementation

automatically unloads data from the FIFO1 RAM to its output

register and auxiliary registers. Therefore, implementing a

new port B bus size and performing a FIFO1 read before all

bytesorwordsstoredintheauxiliaryregistershavebeenread

results in a loss of the unread long word data.

DYNAMIC BUS SIZING

The port B bus can be configured in a 36-bit long word,

18-bit word, or 9-bit byte format for data read from FIFO1 or

written to FIFO2. Word- and byte-size bus selections can

utilizethemostsignificantbytesofthebus(bigendian)orleast

significant bytes of the bus (little endian). Port B bus size can

be changed dynamically and synchronous to CLKB to com-

municate with peripherals of various bus widths.

When reading data from FIFO1 in byte or word format, the

unused B0-B35 outputs remain inactive but static, with the

unused FIFO1 output register bits holding the last data value

to decrease power consumption.

BUS-MATCHING FIFO2 WRITES

The levels applied to the port B bus size select (SIZ0,

SIZ1)inputsandthebig-endianselect(BE)inputarestoredon

each CLKB LOW-to-HIGH transition. The stored port B bus

sizeselectionisimplementedbythenextrisingedgeonCLKB

according to Figure 1.

Only 36-bit long-word data is written to or read from the

two FIFO memories on the IDT723614. Bus-matching opera-

tions are done after data is read from the FIFO1 RAM and

before data is written to the FIFO2 RAM. Port B bus sizing

does not apply to mail register operations.

Data is written to the FIFO2 RAM in 36-bit long word

increments. FIFO2 writes, with a long-word bus size, immedi-

ately store each long word in FIFO2 RAM. Data written to

FIFO2 with a byte or word bus size stores the initial bytes or

words in auxiliary registers. The CLKB rising edge that writes

the fourth byte or the second word of long word to FIFO2 also

stores the entire long word in FIFO2 RAM. The bytes are

arranged in the manner shown in Figure 1.

Each FIFO2 write with a new bus-size implementation

resets the state machine that controls the data flow from the

auxiliary registers to the FIFO2 RAM. Therefore, implement-

ing a new bus size and performing a FIFO2 write before bytes

or words stored in the auxiliary registers have been loaded to

FIFO2 RAM results in a loss of data.

BUS-MATCHING FIFO1 READS

Data is read from the FIFO1 RAM in 36-bit long word

increments. If a long word bus size is implemented, the entire

long word immediately shifts to the FIFO1 output register. If

13

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PORT-B MAIL REGISTER ACCESS

word read from FIFO1 or written to FIFO2 is maintained until

the entire long word is transferred, regardless of the SW0 and

SW1 states during subsequent writes or reads. Figure 3 is an

example of the byte-order swapping available for long words.

Performing a byte swap and bus size simultaneously for a

FIFO1 read first rearranges the bytes as shown in Figure 3,

then outputs the bytes as shown in Figure 1. Simultaneous

bus-sizing and byte-swapping operations for FIFO2 writes,

firstloadsthedataaccordingtoFigure1, thenswapsthebytes

as shown in Figure 3 when the long word is loaded to FIFO2

RAM.

In addition to selecting port-B bus sizes for FIFO reads

and writes, the port B bus size select (SIZ0, SIZ1) inputs also

access the mail registers. When both SIZ0 and SIZ1 are

HIGH, the mail1 register is accessed for a port B long word

read and the mail2 register is accessed for a port B long word

write. The mail register is accessed immediately and any bus-

sizing operation that may be underway is unaffected by the

mail register access. After the mail register access is com-

plete, the previous FIFO access can resume in the next CLKB

cycle. The logic diagram in Figure 2 shows the previous bus-

size selection is preserved when the mail registers are ac-

cessed from port B. A port B bus size is implemented on each

rising CLKB edge according to the states of SIZ0_Q, SIZ1_Q,

and BE_Q.

PARITY CHECKING

The port A inputs (A0-A35) and port B inputs (B0-B35)

each have four parity trees to check the parity of incoming (or

outgoing)data. Aparityfailureononeormorebytesoftheport

A data bus is reported by a LOW level on the port parity error

flag (PEFA). A parity failure on one or more bytes of the port

B data input that are valid for the bus-size implementation is

reported by a LOW level on the port B parity error flag

(PEFB).Odd or even parity checking can be selected, and the

parity error flags can be ignored if this feature is not desired.

Parity status is checked on each input bus according to

the level of the odd/even parity (ODD/EVEN) select input. A

parity error on one or more valid bytes of a port is reported by

a LOW level on the corresponding port parity error flag (PEFA,

PEFB) output. Port A bytes are arranged as A0-A8, A9-A17,

BYTE SWAPPING

The byte-order arrangement of data read from FIFO1 or

data written to FIFO2 can be changed synchronous to the

rising edge of CLKB. Byte-order swapping is not available for

mail register data. Four modes of byte-order swapping (in-

cluding no swap) can be done with any data port size selec-

tion. The order of the bytes are rearranged within the long

word, but the bit order within the bytes remains constant.

Byte arrangement is chosen by the port B swap select

(SW0, SW1) inputs on a CLKB rising edge that reads a new

longwordfromFIFO1orwritesanewlongwordtoFIFO2. The

byte order chosen on the first byte or first word of a new long

CLKB

MUX

G1

1

SIZ0 Q

SIZ1 Q

BE Q

•

D

Q

SIZ0

•

1

SIZ1

BE

•

3146 drw fig 02

Figure 2. Logic Diagrams for SIZ0, SIZ1, and

Register

BE

14

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

A35—A27

A26—A18

A17—A9

A8—A0

B

A

C

D

SW1 SW0

L

A

B

C

D

B35—B27

B26—B18

B17—B9

B8—B0

(a) NO SWAP

A35—A27

A26—A18

A17—A9

A8—A0

SW1 SW0

A

B

C

D

L

H

A

D

C

B

B35—B27

B26—B18

(b) BYTE SWAP

B17—B9

B8—B0

A35—A27

A26—A18

A17—A9

A8—A0

SW1 SW0

B

A

C

D

H

L

D

B

C

A

B35—B27

B26—B18

B17—B9

B8—B0

(c) WORD SWAP

A35—A27

A26—A18

A17—A9

A8—A0

SW1 SW0

A

B

C

D

H

B

A

D

C

B35—B27

B26—B18

B17—B9

B8—B0

(d) BYTE-WORD SWAP

3146 drw fig 03

Figure 3. Byte Swapping (Long Word Size Example)

15

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

A18-A26, and A27-A35. Port B bytes are arranged as B0-B8, each byte used as the parity bit. A write to a FIFO or mail

B9-B17, B18-B26, and B27-B35, and its valid bytes are those register stores the levels applied to all nine inputs of a byte

used in a port B bus-size implementation. When odd/even regardless of the state of the parity generate select (PGA,

parity is selected, a port parity error flag (PEFA, PEFB) is LOW PGB) inputs. When data is read from a port with parity

if any byte on the port has an odd/even number of LOW levels generation selected, the lower eight bits of each byte are used

applied to the bits.

to generate a parity bit according to the level on the ODD/

The four parity trees used to check the A0-A35 inputs are EVEN select. The generated parity bits are substituted for the

shared by the mail2 register when parity generation is se- levels originally written to the most significant bits of each byte

lectedforportAreads(PGA=HIGH). WhenaportAreadfrom as the word is read to the data outputs.

the mail2 register with parity generation is selected with CSA

Parity bits for FIFO data are generated after the data is

LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH, read from SRAM and before the data is written to the output

the port A parity error flag (PEFA) is held HIGH regardless of register. Therefore, the port A parity generate select (PGA)

the levels applied to the A0-A35 inputs. Likewise, the parity and odd/even parity select (ODD/EVEN) have setup and hold

trees used to check the B0-B35 inputs are shared by the mail1 time constraints to the port A clock (CLKA) and the port B

register when parity generation is selected for port B reads parity generate select (PGB) and ODD/EVEN have setup and

(PGB=HIGH). WhenaportBreadfromthemail1registerwith hold-timeconstraintstotheportBclock(CLKB). Thesetiming

parity generation is selected with CSB LOW, ENB HIGH, W/ constraints only apply for a rising clock edge used to read a

RB LOW, both SIZ0 and SIZ1 HIGH, and PGB HIGH, the port new long word to the FIFO output register.

B parity error flag (PEFB) is held HIGH regardless of the levels

applied to the B0-B35 inputs.

The circuit used to generate parity for the mail1 data is

shared by the port B bus (B0-B35) to check parity and the

circuit used to generate parity for the mail2 data is shared by

the port A bus (A0-A35) to check parity. The shared parity

PARITY GENERATION

A HIGH level on the port A parity generate select (PGA) trees of a port are used to generate parity bits for the data in

or port B parity generate select (PGB) enables the IDT723614 a mail register when the port chip select (CSA, CSB) is LOW,

to generate parity bits for port reads from a FIFO or mailbox enable (ENA, ENB) is HIGH, write/read select (W/RA, W/RB)

register. Port A bytes are arranged as A0-A8, A9-A17, A18- input is LOW, the mail register is selected (MBA is HIGH for

26, and A27-A35, with the most significant bit of each byte portA;bothSIZ0andSIZ1areHIGHforportB),andportparity

usedastheparitybit. PortBbytesarearrangedasB0-B8, B9- generate select (PGA, PGB) is HIGH. Generating parity for

B17, B18-B26, and B27-B35, with the most significant bit of mailregisterdatadoesnotchangethecontentsoftheregister.

16

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

CLKA

tRSTH

CLKB

tRSTS

tFSS

tFSH

RST

FS1,FS0

FFA

0,1

tWFF

tREF

EFA

tWFF

FFB

tREF

EFB

tRSF

MBF1,

MBF2

tPAE

AEA

tPAF

tPAE

AFA

AEB

AFB

tPAF

3146 drw 04

Figure 4. Device Reset Loading the X Register with the Value of Eight

17

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

t

CLK

tCLKH

tCLKL

CLKA

HIGH

FFA

t

ENH

tENS

CSA

t

ENS

tENH

W/RA

MBA

tENH

tENS

tENH

t

ENH

tENS

tENH

ENA

t

DH

tDS

(1)

W2⁽¹⁾

A0 - A35

No Operation

W1

ODD/

EVEN

t

PDPE

t

PDPE

Valid

PEFA

3146 drw 05

NOTE:

1. Written to FIFO1.

Figure 5. Port-A Write Cycle Timing for FIFO1

18

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

CLKB

FFB

HIGH

t ENS

CSB

t ENS

W/RB

tENS

tENH

t ENS

tSWS

tENH

tSWH

ENB

SW1,

SW0

tSZS

tSZH

BE

SIZ1,

SIZ0

(0,0)

tPPE

NOT (1,1)⁽¹⁾

tDS

tDH

B0-B35

ODD/

EVEN

tPDPE

PEFB

VALID

3146 drw 06

NOTE:

1. SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register

DATA SWAP TABLE FOR LONG-WORD WRITES TO FIFO2

SWAP MODE

SW1 SW0

DATA WRITTEN TO FIFO2

DATA READ FROM FIFO2

B35-27

B26-18

B17-B9

B8-B0

A35-27

A26-A18

A17-A9

A8-A0

L

H

L

A

D

C

B

C

D

A

C

B

A

D

A

B

C

A

B

C

D

H

Figure 6. Port-B Long-Word Write Cycle Timing for FIFO2

19

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

CLKB

FFB

HIGH

tENH

tENS

CSB

tENS

W/RB

tENS

tENH

tSWH

tENS

tSWS

ENB

SW1, SW0

tSZS

tSZH

tSZS

tSZH

BE

tSZS

tDS

tSZH

tDH

NOT (1,1)⁽¹⁾

SIZ1, SIZ0

(0, 1)

Little

Endian

B0-B17

tDH

tDS

Big

Endian

B18-B35

ODD/EVEN

PEFB

tPPE

tPDPE

VALID

3146 drw 07

NOTES:

1. SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register.

2. PEFB indicates parity error for the following bytes: B35-B27 and B26-B18 for big-endian bus, and B17-B9 and B-8-B0 for little-endian bus.

DATA SWAP TABLE FOR WORD WRITES TO FIFO2

DATA WRITTEN TO FIFO2

SWAP

MODE

WRITE

NO.

DATA READ FROM FIFO2

BIG ENDIAN

B35-27 B26-18

LITTLE ENDIAN

SW1 SW0

B17-B9

B8-B0

A35-27

A26-A18

A17-A9

A8-A0

L

H

L

1

2

1

2

1

2

1

2

A

B

C

A

B

D

A

C

D

B

D

B

A

C

B

D

C

A

B

C

D

C

D

B

C

A

B

D

C

A

D

B

A

C

L

A

B

C

D

H

Figure 7. Port-B Word Write Cycle Timing for FIFO2

20

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

CLKB

FFB

HIGH

tENS

tENH

CSB

tENS

W/RB

ENB

tENH

tENS

tENH

tSWS

tSZS

tENH

tSZH

SW1,

SW0

tSZH

tSZS

BE

tSZH

tDH

tSZS

SIZ1,

SIZ0

(1,0)

Not (1,1)⁽¹⁾

tDS

Little

Endian

B0-

B8

Big

Endian

B27-

B35

ODD/EVEN

PEFB

tPDPE

tPPE

tPDPE

Valid

3146 drw 08

NOTES:

1.

2.

SIZ0 = HIGH amd SIZ1 = HIGH writes data to the mail2 register.

PEFB indicates parity error for the following bytes: B35—B27 for big-endian bus and B17—B9 for little-endian bus.

Figure 8. Port-B Byte Write Cycle Timing for FIFO2

21

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

DATA SWAP TABLE FOR BYTE WRITES TO FIFO2

DATA WRITTEN

TO FIFO2

SWAP MODE

WRITE

NO.

BIG

ENDIAN

LITTLE

ENDIAN

DATA READ FROM FIFO2

SW1

SW0

B35-B27

B8-80

D

A35-A27

A26-A18

A17-A9

A8-A0

1

2

3

4

1

2

3

4

1

2

3

4

1

2

3

4

A

B

C

D

C

B

A

C

D

A

B

A

D

C

A

B

C

D

L

B

A

B

L

H

L

A

B

C

D

C

D

B

A

H

D

C

D

A

B

C

D

H

A

B

Figure 8. Port-B Byte Write Cycle Timing for FIFO2 (continued)

22

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

CLKB

EFB

HIGH

CSB

W/RB

tENS

tENH

tENS

tSWS

tENH

ENB

No Operation

tSWH

SW1,

SW0

tSZS

tSZH

BE

SIZ1,

SIZ0

(1)

(0,0)

NOT (1,1)

tPGS

tPGH

tA

PGB,

ODD/

EVEN

tEN

tDIS

tA

Previous Data

W1

B0-B35

W2

3146 drw 09

NOTES:

1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.

2. Data read from FIFO1.

DATA SWAP TABLE FOR FIFO LONG-WORD READS FROM FIFO1

DATA WRITTEN TO FIFO1

A35-A27 A26-A18 A17-A9 A8-A0

SWAP MODE

DATA READ FROM FIFO1

B35-B27 B26-B18 B17-B9 B8-B0

SW1

SW0

A

B

C

D

L

H

L

A

D

C

B

C

D

A

C

B

A

D

A

B

C

H

Figure 9. Port-B Long-Word Read Cycle Timing for FIFO1

23

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

CLKB

EFB

HIGH

CSB

W/RB

tENS

tENH

tSWH

ENB

No Operation

tSWS

SW1,

SW0

tSZS

tSZH

BE

SIZ1,

SIZ0

(1)

(0,1)

NOT (1,1)

tPGS

tPGH

tA

PGB,

ODD/

EVEN

tEN

tDIS

tA

Little

Endian⁽²⁾

Previous Data

B0-B17

tA

tDIS

Big

Endian⁽²⁾

B18-B35

Previous Data

3146 drw 10

NOTES:

1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.

2. Unused word B0-B17 or B18-B35 holds last FIFO1 output register data for word-size reads.

DATA SWAP TABLE FOR WORD READS FROM FIFO1

DATA READ FROM FIFO1

DATA WRITTEN TO FIFO1

SWAP MODE READ

NO.

BIG ENDIAN

LITTLE ENDIAN

A35-A27 A26-A18 A17-A9

A8-A0

SW1

SW0

B35-B27 B26-B18

B17-B9

B8-B0

1

2

A

C

B

D

C

A

D

B

A

B

C

D

L

1

2

D

B

C

A

B

D

A

C

D

L

H

L

1

2

C

A

D

B

A

C

B

D

1

2

B

D

A

C

D

B

C

A

H

Figure 10. Port-B Word Read Cycle Timing for FIFO1

24

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

CLKB

EFB

HIGH

CSB

W/RB

tENH

tSWH

tENS

tSWS

ENB

No Operation

SW1,

SW0

tSZH

tSZS

BE

tSZH

Not (1,1)⁽¹⁾

SIZ1,

SIZ0

(1,0)

Not (1,1)⁽¹⁾

tPGH

Not (1,1) ⁽¹⁾

Not (1,1)⁽¹⁾

tPGS

PGB,

ODD/

EVEN

tEN

tA

tDIS

tDIS

tA

tA

tA

Previous Data

B0-B8

tA

B27-B35

Previous Data

NOTES:

3146 drw 11

1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.

2. Unused bytes hold last FIFO1 output regisger data for byte-size reads.

DATA SWAP TABLE FOR BYTE READS FROM FIFO1

DATA READ FROM FIFO 1

DATA WRITTEN TO FIFO 1

SWAP MODE

READ

NO.

BIG

ENDIAN

LITTLE

ENDIAN

A35-A27

A26-A18

A17-A9

A8-A0

SW1

SW0

B35-B27

B8-B0

1

2

3

4

A

B

C

D

C

B

A

B

C

D

L

H

L

1

2

3

4

D

C

B

A

B

C

D

A

B

C

D

L

H

1

2

3

4

C

D

A

B

A

D

C

1

2

3

4

B

A

D

C

D

A

B

H

Figure 11. Port-B Byte Read Cycle Timing for FIFO1

25

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

tCLK

tCLKH

tCLKL

CLKA

EFA

HIGH

CSA

W/RA

MBA

tENH

tA

tENH

tENS

ENA

No

tMDV

tA

Operation

tDIS

tEN

(1)

Word 2⁽¹⁾

A0 - A35

Previous Data

Word 1

tPGS

tPGH

PGA,

ODD/

EVEN

3146 drw 12

NOTE:

1. Read from FIFO2..

Figure 12. Port-A Read Cycle Timing for FIFO2

26

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

tCLK

tCLKL

tCLKH

CLKA

CSA

LOW

HIGH

WRA

MBA

tENS

tENH

ENA

HIGH

tDS

FFA

tDH

A0 - A35

W1

tCLK

tCLKH

(1)

tSKEW1

tCLKL

1

2

CLKB

EFB

tREF

FIFO1 Empty

LOW

CSB

W/RB

SIZ1,

SIZ0

LOW

tENS

tENH

ENB

tA

B0 -B35

W1

3146 drw 13

NOTES:

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time

between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than

shown.

2. Port-B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port-B size is word or byte, EFB is set LOW by the last word or

byte read from FIFO1, respectively.

Figure13.

Flag Timing and First Data Read when FIFO1 is Empty

EFB

27

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

tCLK

tCLKL

tCLKH

CLKB

CSB

LOW

WRB

HIGH tENS

tENH

SIZ1,

SIZ0

tENS

ENB

HIGH

tDS

FFB

tDH

B0 - B35

W1

tCLK

tCLKH

(1)

tSKEW1

tCLKL

1

2

CLKA

EFA

tREF

FIFO2 Empty

LOW

CSA

W/RA

MBA

tENS

tENH

ENA

tA

A0 -A35

W1

3146 drw 14

NOTES:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time

between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than

shown.

2. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte tSKEW1 is referenced to the rising

CLKB edge that writes the last word or byte of the long word, respectively.

Figure 14.

Flag Timing and First Data Read when FIFO2 is Empty

EFA

28

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

tCLK

tCLKH

tCLKL

CLKB

CSB

LOW

W/RB

SIZ1,

SIZ0

tENH

tENS

ENB

HIGH

EFB

tA

Previous Word in FIFO1 Output Register

Next Word From FIFO1

tCLK

B0 - B35

(1)

tSKEW1

tCLKH

tCLKL

1

2

CLKA

tWFF

FFA

FIFO1 Full

LOW

CSA

HIGH

WRA

MBA

tENH

tDH

tENS

ENA

tDS

A0 - A35

To FIFO1

3146 drw 15

NOTES:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time

between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.

2. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW1 is referenced from the rising

CLKB edge that reads the last word or byte of the long word, respectively.

Figure 15.

Flag Timing and First Available Write when FIFO1 is Full.

FFA

29

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

tCLK

tCLKH

tCLKL

CLKA

CSA

LOW

W/RA

MBA

LOW

t

ENH

t

ENS

ENA

HIGH

EFA

t

A

Previous Word in FIFO2 Output Register

Next Word From FIFO2

CLK

A0 - A35

(1)

tSKEW1

t

tCLKH

tCLKL

1

2

CLKB

tWFF

t

WFF

FFB

CSB

WRB

FIFO2 Full

LOW

HIGH

tENH

t

ENS

SIZ1,

SIZ0

t

ENS

t

ENH

ENB

tDS

t

DH

B0 - B35

To FIFO2

3146 drw 16

NOTES:

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time

between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown.

2. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, FFB is set LOW by the last word or

byte write of the long word, respectively.

Figure 16.

Flag Timing and First Available Write when FIFO2 is Full

FFB

30

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

CLKA

tENS

tENH

ENA

(1)

tSKEW2

1

2

CLKB

AEB

tPAE

X Long Word in FIFO1

(X+1) Long Words in FIFO1

tENS

tENH

ENB

3146 drw 17

NOTES:

1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time

between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.

2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW).

3. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, AEB is set LOW by the last word or

byte read of the long word, respectively.

Figure 17. Timing for

when FIFO1 is Almost Empty

AEB

CLKB

ENB

t

ENH

t

ENS

(1)

SKEW2

t

1

2

CLKA

AEA

tPAE

t

PAE

X Long Words in FIFO2

(X+1) Long Words in FIFO2

ENS

t

tENH

ENA

3146 drw 18

NOTES:

1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time

between the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.

2. FIFO2 Write (CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).

3. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced from the rising

CLKB edge that writes the last word or byte of the long word, respectively.

Figure 18. Timing for

when FIFO2 is Almost Empty

AEA

31

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

(1)

tSKEW2

1

2

CLKA

ENA

tENH

tPAF

tENS

tPAF

(64-X) Long Words in FIFO1

AFA

[64-(X+1)] Long Words in FIFO1

CLKB

ENB

tENS

tENH

3146 drw 19

NOTES:

1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time

between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKB cycle later than shown.

2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW).

3. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced from the last

word or byte read of the long word, respectively.

Figure 19. Timing for

when FIFO1 is Almost Full

AFA

(1)

tSKEW2

1

2

CLKB

ENB

tENH

tPAF

tENS

tPAF

(64-X) Long Words in FIFO2

AFB

[64-(X+1)] Long Words in FIFO2

CLKA

ENA

tENS

tENH

3146 drw 20

NOTES:

1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time

between the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKA cycle later than shown.

2. FIFO2 Write (CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).

3. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, AFB is set LOW by the last word or

byte read of the long word, respectively.

Figure 20. Timing for

when FIFO2 is Almost Full

AFB

32

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

CLKA

tENH

tENS

CSA

W/RA

MBA

ENA

tDH

tDS

W1

A0 - A35

CLKB

tPMF

MBF1

CSB

W/RB

SIZ1,

SIZ0

tENH

tENS

ENB

tMDV

tEN

tDIS

tPMR

B0 - B35

W1 (Remains valid in Mail1 Register after read)

FIFO1 Output Register

3146 drw 21

NOTE:

1. Port B parity generation off (PGB = LOW).

Figure 21. Timing for Mail1 Register and

Flag

MBF1

33

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

CLKB

tENH

tENS

CSB

W/RB

tSZS

tSZH

tDH

SIZ1,

SIZ0

ENB

B0 - B35

CLKA

tDS

W1

tPMF

MBF2

CSA

W/RA

MBA

ENA

tENH

tENS

tEN

tMDV

tDIS

tPMR

W1 (Remains valid in Mail2 Register after read)

A0 - A35

FIFO2 Output Register

3146 drw 22

NOTE:

1. Port-A parity generation off (PGA = LOW).

Figure 22. Timing for Mail2 Register and

Flag

MBF2

34

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

ODD/

EVEN

W/RA

MBA

PGA

tPEPE

tPOPE

tPEPE

Valid

PEFA

Valid

3146 drw 23

Figure 23. ODD/

. W/ A, MBA, and PGA to

Timing

PEFA

EVEN

R

ODD/

EVEN

W/RB

SIZ1,

SIZ0

PGB

tPEPE

tPOPE

tPEPE

Valid

PEFB

Valid

3146 drw 24

Figure 24. ODD/

. W/ B, SIZ1, SIZ0, and PGB to

EVEN

Timing

R

PEFB

35

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

ODD/

EVEN

LOW

CSA

W/RA

MBA

PGA

tPEPB

tMDV

tEN

tPOPB

tPEPB

A8, A17,

A26, A35

Generated Parity

Mail2 Data

Mail2

Data

3146 drw 25

NOTE:

1. ENA is HIGH.

Figure 25. Parity Generation Timing when Reading from the Mail2 Register

ODD/

EVEN

LOW

CSB

W/RB

SIZ1,

SIZ0

PGB

tPEPB

tEN

tMDV

tPOPB

tPEPB

B8, B17,

B26, B35

Generated Parity

Mail1 Data

Mail1

Data

NOTE:

3146drw 26

1. ENB is HIGH.

Figure 26. Parity Generation Timing when Reading from the Mail1 Register

36

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

TYPICAL CHARACTERISTICS

SUPPLY CURRENT

vs

CLOCK FREQUENCY

400

V

CC = 5.5 V

V

CC = 5.5 V

350

300

= 1/2

f

data

s

T

°

= 25 C

A

V

CC = 5 V

C

= 0 pF

L

V

CC = 4.5 V

250

200

150

100

50

0

10

20

30

40

50

60

70

80

f

– Clock Frequency – MHz

s

3146 drw 27

Figure 27

CALCULATING POWER DISSIPATION

The ICC(f) current for the graph in Figure 27 was taken while simultaneously reading and writing the FIFO on the

IDT723614 with CLKA and CLKB set to fs. All data inputs and data outputs change state during each clock cycle to

consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero-capacitance load.

Once the capacitive lead per data-output channel is known, the power dissipation can be calculated with the equation

below.

With ICC(f) taken from Figure 28, the maximum power dissipation (PT) of the IDT723614 can be calculated by:

2

PT = VCC x ICC(f) + ∑(CL x VOH x fo)

where:

CL

fo

VOH

=

output capacitance load

switching frequency of an output

output high level voltage

When no reads or writes are occurring on the IDT723614, the power dissipated by a single clock (CLKA or CLKB)

input running at frequency fs is calculated by:

PT=VCC x fs x 0.290 mA/MHz

37

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PARAMETER MEASUREMENT INFORMATION

5 V

Ω

1.1 k

From Output

Under Test

30 pF⁽¹⁾

Ω

680

LOAD CIRCUIT

3 V

Timing

Input

1.5 V

High-Level

Input

1.5 V

GND

3 V

t

S

th

tW

3 V

Data,

Enable

Input

1.5 V

Low-Level

Input

1.5 V

GND

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATIONS

3 V

Output

Enable

1.5 V

t

PZL

GND

t

PLZ

3 V

≈

3 V

Input

1.5 V

Low-Level

Output

GND

V

OL

t

PD

tPZH

tPD

V

OH

V

OH

OV

In-Phase

Output

1.5 V

High-Level

Output

1.5 V

V

t

PHZ

OL

≈

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

3146 drw 28

NOTE:

1. Includes probe and jig capacitance.

Figure 28. Load Circuit and Voltage Waveforms

38

IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION

723614

Device Type Power

IDT

X

XX

Speed

X

Package

Process/

Temperature

Range

BLANK Commercial (0°C to +70°C)

PF

PQF

Thin Quad Flat Pack (TQFP, PN120-1)

Plastic Quad Flat Pack (PQFP, PQ132-1)

15

20

30

Commercial Only

Clock Cycle Time (tCLK)

Speed in Nanoseconds

L

Low Power

723614 64 x 36 x 2 SyncBiFIFO

3146 drw 29

39

型号:	IDT723614L20PQF
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	INTEGRATED DEVICE TECHNOLOGY INC
零件包装代码：	QFP
包装说明：	PLASTIC, QFP-132
针数：	132
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8542.32.00.71
风险等级：	5.91
Is Samacsys：	N
最长访问时间：	12 ns
其他特性：	MAIL BOX; PARITY GENERATOR/CHECKER
最大时钟频率 (fCLK)：	50 MHz
周期时间：	20 ns
JESD-30 代码：	S-PQFP-G132
JESD-609代码：	e0
长度：	24.13 mm
内存密度：	2304 bit
内存集成电路类型：	BI-DIRECTIONAL FIFO
内存宽度：	36
湿度敏感等级：	3
功能数量：	1
端子数量：	132
字数：	64 words
字数代码：	64
工作模式：	SYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	64X36
输出特性：	3-STATE
可输出：	YES
封装主体材料：	PLASTIC/EPOXY
封装代码：	BQFP
封装等效代码：	SPQFP132,1.1SQ
封装形状：	SQUARE
封装形式：	FLATPACK, BUMPER
并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	225
电源：	5 V
认证状态：	Not Qualified
座面最大高度：	4.57 mm
最大待机电流：	0.000001 A
子类别：	FIFOs
最大压摆率：	0.001 mA
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.635 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	20
宽度：	24.13 mm
Base Number Matches：	1

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