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IS41C16128
ISSI
Functional Description
Refresh Cycle
The IS41C16128 is a CMOS DRAM optimized for high-
speed bandwidth, low power applications. During READ
or WRITE cycles, each bit is uniquely addressed through
the 17 address bits. The row address is latched by the
Row Address Strobe (RAS). The column address is
latched by the Column Address Strobe (CAS). RAS is
usedtolatchthefirstninebitsandCASisusedtolatchthe
latter nine bits.
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory.
1. Byclockingeachofthe512rowaddresses(A0through
A8) with RASat least once every 8 ms. Any read, write,
read-modify-write or RAS-only cycle refreshes the ad-
dressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
TheIS41C16128hastwoCAScontrols,LCASandUCAS.
The LCAS and UCAS inputs internally generates a CAS
signalfunctioninginanidenticalmannertothesingleCAS
input on the other 128K x 16 DRAMs. The key difference
is that each CAS controls its corresponding I/O tristate
logic (in conjunction with OE and WE and RAS). LCAS
controls I/O0 through I/O7 and UCAS controls I/O8
through I/O15.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
The IS41C16128 CAS function is determined by the first
CAS (LCAS or UCAS) transitioning LOW and the last
transitioning back HIGH. The two CAS controls give the
IS41C16128 both BYTE READ and BYTE WRITE cycle
capabilities.
Extended Data Out Page Mode
EDOpagemodeoperationpermitsall256columnswithin
a selected row to be randomly accessed at a high data
rate.
In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. There-
fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the CAS
cycle time becomes shorter.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
InEDOpagemode,duetotheextendeddatafunction,the
CAScycle time can be shorter than in the fast page mode
if the timing margin is the same.
Read Cycle
The EDO page mode allows both read and write opera-
tions during one RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time speci-
fied by tAR. Data Out becomes valid only when tRAC, tAA,
tCAC and tOEA are all satisfied. As a result, the access time
is dependent on the timing relationships between these
parameters.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS signal).
Write Cycle
AwritecycleisinitiatedbythefallingedgeofCASandWE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs
last.
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
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Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
QQ：1902134819 复制
