J-Type Voltage Controlled Crystal Oscillator
Table 1. Pin Out Information for the CMOS output Option
6
5
4
Pin
Symbol
Function
1
2
VC
VCXO Control Voltage
TTL logic low disables output.
Tri-State1
TOP VIEW
TTL logic high, or no connect, enables output.
3
4
5
GND
Output
CMOS/TTL
select1,2
VCC
Case and Electrical Ground
1
VCXO Output
TTL logic low optimizes symmetry for CMOS.
TTL logic high, or NC, optimizes symmetry for TTL
2
3
6
Power Supply Voltage (5.0 V or 3.3 V ±10%)
1. Standard option. Tri-State can be connected to pin 5 and CMOS/TTL select would be on pin 2.
2. Output is HCMOS. For frequencies >12MHz, this option optimizes symmetry for either CMOS or TTL thresholds. Ground this pin
for frequencies < 12MHz.
Table 2. Electrical Performance @ 25°C for the CMOS output option
Parameter
Supply Voltage 1, +5 volt option
+3.3 volt option
Symbol
Minimum
4.5
Typical Maximum Units
5.0
3.3
5.5
3.6
V
V
3.0
Supply Current
10mA + 0.25mA per MHz, typical
Center Frequency, see ordering information
Operating Temperature, see ordering info
Absolute Pull Range over the operating
temperature range, aging and power supply
Vc= 0.5 to 4.5 or 0.3 to 3.0 V
see ordering information for options
Gain Transfer
FN
TOP
APR
1.024
77.760
MHz
°C
ppm
0/70, -40/85
±50 to ±100
KV
Positive
(Frequency vs. Control Voltage)
Output Level High2
VOH
VOL
tR/ tF
SYM
IL
0.8*Vcc
-
-
V
V
ns
%
uA
kHz
ps
ps
Output Level Low2
0.1*Vcc
5
Output Rise/Fall Time2
Duty Cycle3, see ordering info
Input Leakage
45/55 or 40/60
±1
-
Control Voltage Modulation Bandwidth
RMS Jitter, 77.760MHz
RMS Jitter, 77.760MHz, 12kHz to 20MHz
Maximum Control Voltage
Maximum Supply Voltage
BW
-
10
3
<0.5
0
VDD
7
V
Storage Temperature
Soldering Temp./Time
TS
TLS
-55
-
-
-
125
240/10
°C
°C/s
1. Power supply bypass is required and a 0.1uF in parallel with a 0.01uF high frequency capacitor is recommended.
2. Figure 1 defines these parameters. Figure 2 illustrates the load used to test devices.
3. Duty cycle is defined as on-time versus period at 1.4 V for TTL, and 2.5 V for CMOS (5volt supply) and at 1.65 V for CMOS (3.3
volt operation)
TF
TR
IDD
650
Ohm
80%
50%
20%
6
1
2
5
3
+
-
4
VDD
.01µF
.1µF
IC
VC
On Time
15pF
1.8k
Ohm
+
-
Period
Figure 1. Output Waveform
Figure 2. Output Test Conditions (25±5°C)
for 5 volt devices, 15pF cap only for 3.3V.
Vectron International 267 Lowell Rd. Hudson, NH 03051 Tel:1-88-VECTRON-1
e-mail vectron@vectron.com
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