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Micro PMU with 1.2 A Buck Regulator

and Two 300 mA LDOs

Data Sheet

ADP5040

FEATURES

GENERAL DESCRIPTION

Input voltage range: 2.3 V to 5.5 V

One 1.2 A buck regulator

Two 300 mA LDOs

20-lead, 4 mm × 4 mm LFCSP package

Overcurrent and thermal protection

Soft start

The ADP5040 combines one high performance buck regulator

and two low dropout regulators (LDO) in a small 20-lead

LFCSP to meet demanding performance and board space

requirements.

The high switching frequency of the buck regulator enables the use

of tiny multilayer external components and minimizes board space.

Undervoltage lockout

When the MODE pin is set to logic high, the buck regulator

operates in forced pulse width modulation (PWM) mode.

When the MODE pin is set to logic low, the buck regulator

operates in PWM mode when the load is around the nominal

value. When the load current falls below a predefined threshold

the regulator operates in power save mode (PSM) improving

the light-load efficiency. The low quiescent current, low

dropout voltage, and wide input voltage range of the ADP5040

LDOs extend the battery life of portable devices. The ADP5040

LDOs maintain a power supply rejection greater than 60 dB for

frequencies as high as 10 kHz while operating with a low headroom

voltage.

Buck key specifications

Output voltage range: 0.8 V to 3.8 V

Current mode topology for excellent transient response

3 MHz operating frequency

Peak efficiency up to 96%

Uses tiny multilayer inductors and capacitors

Mode pin selects forced PWM or auto PWM/PSM modes

100% duty cycle low dropout mode

LDOs key specifications

Output voltage range: 0.8 V to 5.2 V

Low V_INfrom 1.7 V to 5.5 V

Stable with 2.2 µF ceramic output capacitors

High PSRR

Low output noise

Each regulator in the ADP5040 is activated by a high level on

the respective enable pin. The output voltages of the regulators

are programmed though external resistor dividers to address a

variety of applications.

Low dropout voltage

−40°C to +125°C junction temperature range

FUNCTIONAL BLOCK DIAGRAM

VOUT1

R

= 30Ω

L1

1µH

FILT

AVIN

SW

V

AT

OUT1

1.2A

FB1

BUCK

AVIN

C6

10µF

R1

R2

VIN1

V

= 2.3V TO

5.5V

IN1

PGND

MODE

C5

4.7µF

EN_BK

ON

FPWM

R3

EN1

OFF

PSM/PWM

VOUT2

FB2

V

AT

LDO1

(DIGITAL)

OUT2

VIN2

V

= 1.7V

TO 5.5V

IN2

300mA

C1

1µF

C2

2.2µF

EN_LDO1

R4

ON

EN2

EN3

OFF

EN_LDO2

VOUT3

FB3

VIN3

V

AT

V

= 1.7V

TO 5.5V

OUT3

IN3

LDO2

(ANALOG)

300mA

C3

1µF

C4

2.2µF

R7

R3

AGND

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADP5040

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Power Management Unit........................................................... 25

Buck Section................................................................................ 26

LDO Section ............................................................................... 27

Applications Information.............................................................. 29

Buck External Component Selection....................................... 29

LDO External Component Selection ...................................... 30

Power Dissipation/Thermal Considerations ............................. 31

Application Diagram ................................................................. 33

PCB Layout Guidelines.................................................................. 34

Suggested Layout........................................................................ 34

Bill of Materials........................................................................... 35

Factory Programmable Options................................................... 36

Outline Dimensions....................................................................... 37

Ordering Guide .......................................................................... 37

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

General Specifications ................................................................. 3

Buck Specifications....................................................................... 3

LDO1, LDO2 Specifications ....................................................... 4

Input and Output Capacitor, Recommended Specifications.. 5

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Theory of Operation ...................................................................... 25

REVISION HISTORY

12/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 40

Data Sheet

ADP5040

SPECIFICATIONS

GENERAL SPECIFICATIONS

AVIN, VIN1 = 2.3 V to 5.5 V; AVIN, VIN1 ≥VIN2, VIN3; VIN2, VIN3 = 1.7 V to 5.5 V, T _J= −40°C to +125°C for minimum/maximum

specifications, and T_A= 25°C for typical specifications, unless otherwise noted.

Table 1.

Parameter

Symbol

Description

Min

Typ

Max

Unit

AVIN UNDERVOLTAGE LOCKOUT

Input Voltage Rising

Option 0

UVLO_AVIN

UVLO_AVINRISE

2.275

3.9

V

Option 1

Input Voltage Falling

Option 0

Option 1

UVLO_AVINFALL

1.95

3.1

V

SHUTDOWN CURRENT

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

START-UP TIME¹

BUCK

I_GND-SD

TS_SD

TS_SD-HYS

ENx = GND

T_Jrising

0.1

150

20

2

µA

°C

t_START1

t_START2

250

85

µs

LDO1, LDO2

V_OUT2, V_OUT3= 3.3 V

Enx, MODE, INPUTS

Input Logic High

Input Logic Low

Input Leakage Current

V_IH

V_IL

V_I-LEAKAGE

2.5 V ≤ AVIN ≤ 5.5 V

ENx = AVIN or GND

1.2

V

µA

0.4

1

0.05

¹Start-up time is defined as the time from the moment EN1 = EN2 = EN3 transfers from 0 V to V_AVINto the moment VOUT1, VOUT2, and VOUT3 reache 90% of their

nominal level. Start-up times are shorter for individual channels if another channel is already enabled. See the Typical Performance Characteristics section for more

information.

BUCK SPECIFICATIONS

AVIN, VIN1 = 2.3 V to 5.5 V; V_OUT1= 1.8 V; L = 1 µH; C_IN= 10 µF; C_OUT= 10 µF; T_J= −40°C to +125°C for minimum/maximum

specifications, and T_A= 25°C for typical specifications, unless otherwise noted.¹

Table 2.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

INPUT CHARACTERISTICS

Input Voltage Range

OUTPUT CHARACTERISTICS

Output Voltage Accuracy

V_IN1

2.3

5.5

V

V_OUT1

PWM mode,

−3

+3

%

I_LOAD= 0 mA to 1200 mA

PWM mode

(ΔV_OUT1/V_OUT1)/ΔI_OUT1I_LOAD= mA to 1200 mA, PWM mode

Line Regulation

Load Regulation

(ΔV_OUT1/V_OUT1)/ΔV_IN1

−0.05

−0.1

%/V

%/A

V

VOLTAGE FEEDBACK

V_FB1

0.485 0.5

100

0.515

PWM TO POWER SAVE MODE

CURRENT THRESHOLD

I_{PSM_L}

mA

INPUT CURRENT CHARACTERISTICS

DC Operating Current

MODE = ground

I_LOAD= 0 mA, device not switching, all other

channels disabled

I_NOLOAD

I_SHTD

21

35

μA

Shutdown Current

EN1 = 0 V, T_A= T_J= −40°C to +125°C

0.2

1.0

Rev. 0 | Page 3 of 40

ADP5040

Data Sheet

Parameter

Symbol

R_PFET

Test Conditions/Comments

Min

Typ

Max

Unit

SW CHARACTERISTICS

SW On Resistance

PFET, AVIN = VIN1 = 3.6 V

PFET, AVIN = VIN1 = 5 V

NFET, AVIN = VIN1 = 3.6 V

NFET, AVIN = VIN1 = 5 V

PFET switch peak current limit

EN1 = 0 V

180

140

170

150

240

190

235

210

2300 mA

Ω

mΩ

R_NFET

I_LIMIT

Current Limit

1600 1950

85

ACTIVE PULL-DOWN

OSCILLATOR FREQUENCY

F_OSC

2.5

3.0

3.5

MHz

¹All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

LDO1, LDO2 SPECIFICATIONS

V_IN2, V_IN3= (V_OUT2,V_OUT3+ 0.5 V) or 1.7 V (whichever is greater) to 5.5V; AVIN, VIN1 ≥ VIN2, VIN3; C_IN= 1 μF , C_OUT= 2.2 μF;

T_J= −40°C to +125°C for minimum/maximum specifications, and T_A= 25°C for typical specifications, unless otherwise noted. ¹

Table 3.

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

INPUT VOLTAGE RANGE

OPERATING SUPPLY CURRENT

Bias Current per LDO²

V_IN2, V_IN3

T_J= −40°C to +125°C

1.7

5.5

V

I_VIN2BIAS/I_VIN3BIAS

I_OUT3= I_OUT4= 0 μA

10

60

30

100

μA

I

_OUT2= I_OUT3= 10 mA

165

245

μA

I_OUT2= I_OUT3= 300 mA

Total System Input Current

LDO1 or LDO2 Only

LDO1 and LDO2 Only

I_IN

Includes all current into AVIN, VIN1, VIN2 and VIN3

I_OUT2= I_OUT3= 0 μA, all other channels disabled

I_OUT2= I_OUT3= 0 μA, buck disabled

53

74

μA

OUTPUT VOLTAGE ACCURACY

V_OUT2, V_OUT3

100 μA < I_OUT2< 300 mA, 100 μA < I_OUT3< 300 mA

V_IN2= (V_OUT2+ 0.5 V) to 5.5 V,

−3

+3

%

V_IN3= (V_OUT3+ 0.5 V) to 5.5 V

REFERENCE VOLTAGE

REGULATION

Line Regulation

V_FB2, V_FB3

0.485 0.500 0.515

−0.03 +0.03

V

(ΔV_OUT2/V_OUT2)/ΔV_IN2

(ΔV_OUT3/V_OUT3)/ΔV_IN3

V_IN2= (V_OUT2+ 0.5 V) to 5.5 V

%/V

V_IN3= (V_OUT3+ 0.5 V) to 5.5 V

I_OUT2= I_OUT3= 1 mA

I_OUT2= I_OUT3= 1 mA to 300 mA

Load Regulation³

(ΔV_OUT2/V_OUT2)/ΔI_OUT2

(ΔV_OUT3/V_OUT3)/ΔI_OUT3

0.002 0.0075 %/mA

DROPOUT VOLTAGE⁴

V_DROPOUT

V_OUT2= V_OUT3= 5.0 V, I_OUT2= I_OUT3= 300 mA

V_OUT2= V_OUT3= 3.3 V, I_OUT2= I_OUT3= 300 mA

V_OUT2= V_OUT3= 2.5 V, I_OUT2= I_OUT3= 300 mA

V_OUT2= V_OUT3= 1.8 V, I_OUT2= I_OUT3= 300 mA

EN2/EN3 = 0 V

72

86

mV

Ω

140

107

180

600

470

123

110

59

140

129

66

ACTIVE PULL-DOWN

CURRENT-LIMIT THRESHOLD⁵

OUTPUT NOISE

R_PDLDO

I_LIMIT

T_J= −40°C to +125°C

335

mA

OUT_LDO2NOISE

10 Hz to 100 kHz, V_IN3= 5 V, V_OUT3= 3.3 V

10 Hz to 100 kHz, V_IN3= 5 V, V_OUT3= 2.8 V

10 Hz to 100 kHz, V_IN3= 5 V, V_OUT3= 1.5 V

10 Hz to 100 kHz, V_IN2= 5 V, V_OUT2= 3.3 V

10 Hz to 100 kHz, V_IN2= 5 V, V_OUT2= 2.8 V

10 Hz to 100 kHz, V_IN2= 5 V, V_OUT2= 1.5 V

μV rms

OUT_LDO1NOISE

Rev. 0 | Page 4 of 40

Data Sheet

ADP5040

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

POWER SUPPLY REJECTION

RATIO

PSRR

1 kHz, V_IN2, V_IN3= 3.3 V, V_OUT2, V_OUT3= 2.8 V,

I_OUT= 100 mA

66

dB

100 kHz, V_IN2,V_IN3= 3.3 V, V_OUT2,V_OUT3= 2.8 V,

I_OUT= 100 mA

1 MHz, V_IN2, V_IN3= 3.3 V, V_OUT2, V_OUT3= 2.8 V,

I_OUT= 100 mA

57

60

dB

¹All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

²This is the input current into V_IN2and V_IN3, which is not delivered to the output load.

³Based on an end-point calculation using 1 mA and 300 mA loads.

⁴Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output

voltages above 1.7 V.

⁵Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

Table 4.

Parameter

Symbol

C_MIN1

Conditions

Min

4.7

Typ

Max

40

Unit

µF

INPUT CAPACITANCE (BUCK)¹

OUTPUT CAPACITANCE (BUCK)²

INPUT AND OUTPUT CAPACITANCE³(LDO1, LDO2)

CAPACITOR ESR

T_J= −40°C to +125°C

C_MIN2

7

40

µF

C_MIN34

R_ESR

0.70

0.001

µF

1

Ω

¹The minimum input capacitance should be greater than 4.7 µF over the full range of operating conditions. The full range of operating conditions in the application

must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, whereas

Y5V and Z5U capacitors are not recommended for use with the buck.

²The minimum output capacitance should be greater than 7 µF over the full range of operating conditions. The full range of operating conditions in the application

must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, whereas

Y5V and Z5U capacitors are not recommended for use with the buck.

³The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended,

whereas Y5V and Z5U capacitors are not recommended for use with LDOs.

Rev. 0 | Page 5 of 40

ADP5040

Data Sheet

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 5.

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Parameter

Rating

AVIN to AGND

VIN1 to AVIN

PGND to AGDN

−0.3 V to +6 V

−0.3 V to +0.3 V

Table 6. Thermal Resistance

Package Type

θ_JA

θ_JC

Unit

VIN2, VIN3, VOUTx, ENx, MODE, FBx, SW to −0.3 V to (AVIN + 0.3 V)

AGND

20-Lead, 0.5 mm pitch LFCSP

38

4.2

°C/W

SW to PGND

−0.3 V to (VIN1 + 0.3 V)

−65°C to +150°C

−40°C to +125°C

JEDEC J-STD-020

3000 V

Storage Temperature Range

Operating Junction Temperature Range

Soldering Conditions

ESD Human Body Model

ESD Charged Device Model

ESD Machine Model

ESD CAUTION

1500 V

200 V

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. 0 | Page 6 of 40

Data Sheet

ADP5040

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADP5040

TOP VIEW

(Not to Scale)

15 FB2

FB3

VOUT3

VIN3

1

2

3

4

5

14 VOUT2

13 VIN2

12 FB1

EN3

NC

11 VOUT1

NOTES

1. EXPOSED PAD MUST BE CONNECTED TO

SYSTEM GROUND PLANE.

Figure 2. Pin Configuration—View from Top of the Die

Table 7. Preliminary Pin Function Descriptions

Pin No.

Mnemonic Description

1

2

3

4

6

7

8

FB3

LDO2 Feedback Input.

LDO2 Output Voltage.

LDO2 Input Supply (1.7 V to 5.5 V).

Enable LDO2. EN3 = high: turn on LDO2; EN3 = low: turn off LDO2.

Housekeeping Input Supply (2.3 V to 5.5 V).

Buck Input Supply (2.3 V to 5.5 V).

VOUT3

VIN3

EN3

AVIN

VIN1

SW

Buck Switching Node.

9

PGND

EN1

VOUT1

FB1

VIN2

VOUT2

FB2

Dedicated Power Ground for Buck Regulator.

Enable Buck. EN1 = high: turn on buck; EN1 = low: turn off buck.

Buck Output Sensing Node.

Buck Feedback Input.

LDO1 Input Supply (1.7 V to 5.5 V).

10

11

12

13

14

15

16

17

LDO1 Output Voltage.

LDO1 Feedback Input.

EN2

MODE

Enable LDO1. EN2 = high: turn on LDO1; EN2 = low: turn off LDO1.

Buck Mode. Mode = high: buck regulator operates in fixed PWM mode; mode = low: buck regulator operates in

power save mode (PSM) at light load and in constant PWM at higher load.

5, 18, 19, 20 NC

EPAD

Not Connected.

0

Exposed Pad. ( AGND = Analog Ground). The exposed pad must be connected to the system ground plane.

Rev. 0 | Page 7 of 40

ADP5040

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

VIN1 = VIN2 = VIN3 = AVIN = 5.0 V, T_A= 25°C, unless otherwise noted.

SW

4

2

V

OUT1

2

V

OUT1

V

OUT2

3

4

EN

V

OUT3

1

3

I

IN

B

CH1 4.0V/DIV

1MΩ

20.0M A CH1

500M

20.0M

2.32V

50µs/DIV

2.0MS/s

500ns/pt

W

B

CH4 2.0V/DIV 1MΩ

CH2 2.0V/DIV 1MΩ

CH3 2.0V/DIV 1MΩ

500M

20.0M

500M

A CH2

1.88V

200µs/DIV

1.0MS/s

1.0µs/pt

CH2

CH3

3.0V/DIV

200mA/DIV 1MΩ

W

CH4 5.0V/DIV

1MΩ

500M

Figure 3. 3-Channel Start-Up Waveforms

Figure 6. Buck Startup, V_OUT1= 3.3 V, I_OUT2= 20 mA

V

OUT3

SW

4

2

4

2

V

OUT2

V

OUT1

V

OUT1

1

3

EN

1

3

I

IN

I

IN

B

CH1 2.0V/DIV

1MΩ

20.0M A CH1

20.0M

1.08V

200µs/DIV

5.0MS/s

200ns/pt

B

W

8.0V/DIV

2.0V/DIV

200mA/DIV 1MΩ

1MΩ

20.0M

500.0M

20.0M

500.0M

CH1

CH2

CH3

A CH1

1.12V

50µs/DIV

2.0MS/s

500ns/pt

W

B

CH2

CH3

2.0V/DIV

300mA/DIV 1MΩ

B

W

CH4 2.0V/DIV

1MΩ

20.0M

CH4 5.0V/DIV

1MΩ

Figure 4. Total Inrush Current, All Channels Started Simultaneously

Figure 7. Buck Startup, V_OUT1= 1.8 V, I_OUT= 20 mA

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

SW

4

2

V

OUT1

EN

1

3

I

IN

0.1

0

2.4

2.9

3.4

3.9

4.4

4.9

5.4

B

CH1 8.0V/DIV

1MΩ

200mA/DIV 1MΩ

20.0M A CH1

500.0M

20.0M

640mV 50µs/DIV

2.0MS/s

W

B

CH2

CH3

V

(V)

2.0V/DIV

IN

W

500ns/pt

CH4 5.0V/DIV

1MΩ

500.0M

Figure 8. Buck Startup, V_OUT1= 1.2 V, I_OUT= 20 mA

Figure 5. System Quiescent Current (Sum of All the Input Currents) vs.

Input Voltage

V_OUT1= 1.8 V, V_OUT2= V_OUT3= 3.3 V, (UVLO = 3.3 V)

Rev. 0 | Page 8 of 40

Data Sheet

ADP5040

1.24

1.23

1.22

1.21

1.20

1.19

1.18

3.90

3.88

3.86

3.84

3.82

3.80

3.78

3.76

3.74

3.72

–40°C

+25°C

+85°C

–40°C

+25°C

+85°C

3.70

0.01

0.1

1

0.1

1

OUTPUT CURRENT (A)

Figure 12. Buck Load Regulation Across Temperature, V_OUT1= 1.2 V,

Auto Mode

Figure 9. Buck Load Regulation Across Temperature, V_OUT1= 3.8 V,

Auto Mode

3.90

3.39

–40°C

+25°C

+85°C

–40°C

+25°C

+85°C

3.88

3.86

3.84

3.82

3.80

3.78

3.76

3.74

3.72

3.70

3.37

3.35

3.33

3.31

3.29

3.27

3.25

0.01

0.1

1

0.01

0.1

1

OUTPUT CURRENT (A)

Figure 13. Buck Load Regulation Across Temperature, V_OUT1= 3.8 V,

PWM Mode

Figure 10. Buck Load Regulation Across Temperature, V_OUT1= 3.3 V,

Auto Mode

3.32

1.820

–40°C

+25°C

+85°C

–40°C

+25°C

+85°C

1.815

1.810

3.31

3.30

3.29

3.28

1.805

1.800

1.795

1.790

1.785

1.780

3.27

3.26

3.25

0.01

0.1

1

0.01

0.1

1

OUTPUT CURRENT (A)

Figure 14. Buck Load Regulation Across Temperature, V_OUT1= 3.3 V,

PWM Mode

Figure 11. Buck Load Regulation Across Temperature, V_OUT1= 1.8 V,

Auto Mode

Rev. 0 | Page 9 of 40

ADP5040

Data Sheet

1.820

1.815

1.810

1.805

1.800

1.795

1.790

1.785

100

90

80

70

60

50

40

30

20

10

0

–40°C

+25°C

+85°C

V

= 4.5V

IN

V

= 5.5V

IN

1.780

0.01

0.1

1

0.001

0.01

0.1

1

OUTPUT CURRENT (A)

Figure 15. Buck Load Regulation Across Temperature,

V_OUT1= 1.8 V, PWM Mode

Figure 18. Buck Efficiency vs. Load Current, Across Input Voltage,

_OUT1= 3.8 V, PWM Mode

V

1.205

1.200

1.195

1.190

1.185

100

90

80

70

60

50

40

30

20

10

0

–40°C

+25°C

+85°C

V

= 3.6V

IN

V

= 4.5V

IN

V

= 5.5V

IN

1.180

0.01

0.1

1

0.0001

0.001

0.01

0.1

1

OUTPUT CURRENT (A)

Figure 16. Buck Load Regulation Across Temperature,

Figure 19. Buck Efficiency vs. Load Current, Across Input Voltage,

V_OUT1= 3.3 V, Auto Mode

V

_OUT1= 1.2 V, PWM Mode

100

90

80

70

60

50

40

30

20

10

0

V

= 3.6

IN

90

80

70

60

50

40

30

20

10

0

V

= 4.5

IN

V

= 4.5V

IN

V

= 5.5V

IN

V

= 5.5

IN

0.001

0.01

0.1

1

0.0001

0.001

0.01

0.1

1

OUTPUT CURRENT (A)

Figure 20. Buck Efficiency vs. Load Current, Across Input Voltage,

V_OUT1= 3.3 V, PWM Mode

Figure 17. Buck Efficiency vs. Load Current, Across Input Voltage,

V_OUT1= 3.8 V, Auto Mode

Rev. 0 | Page 10 of 40

Data Sheet

ADP5040

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V

= 2.4V

= 3.6V

= 4.5V

= 5.5V

V

= 2.4V

= 3.6V

= 4.5V

= 5.5V

IN

0.0001

0.001

0.01

0.1

1

0.001

0.01

0.1

1

OUTPUT CURRENT (A)

Figure 21. Buck Efficiency vs. Load Current, Across Input Voltage,

_OUT1= 1.8 V, Auto Mode

Figure 24. Buck Efficiency vs. Load Current, Across Input Voltage,

V

_OUT1= 1.2 V, PWM Mode

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V

= 2.4V

= 3.6V

= 4.5V

= 5.5V

IN

–40°C

+25°C

+85°C

0.001

0.01

0.1

1

0.0001

0.001

0.01

0.1

1

OUTPUT CURRENT (A)

Figure 22. Buck Efficiency vs. Load Current, Across Input Voltage,

V_OUT1= 1.8 V, PWM Mode

Figure 25. Buck Efficiency vs. Load Current, Across Temperature,

V_IN= 5.0 V, V_OUT1= 3.3 V, Auto Mode

100

90

80

70

60

50

40

30

100

90

80

70

60

50

40

30

V

= 2.4V

= 3.6V

= 4.5V

= 5.5V

IN

20

10

20

–40°C

+25°C

+85°C

10

0

0.0001

0.001

0.01

0.1

1

0.001

0.01

0.1

1

OUTPUT CURRENT (A)

Figure 23. Buck Efficiency vs. Load Current, Across Input Voltage,

V_OUT1= 1.2 V, Auto Mode

Figure 26. Buck Efficiency vs. Load Current, Across Temperature,

V_IN= 5.0 V, V_OUT1= 3.3 V, PWM Mode

Rev. 0 | Page 11 of 40

ADP5040

Data Sheet

100

90

80

70

60

50

40

30

20

10

100

90

80

70

60

50

40

30

20

10

0

–40°C

+25°C

+85°C

–40°C

+25°C

+85°C

0

0.0001

0.001

0.01

0.1

1

0.001

0.01

0.1

1

OUTPUT CURRENT (A)

Figure 27. Buck Efficiency vs. Load Current, Across Temperature,

_IN= 5.0 V, V_OUT1= 1.8 V, Auto Mode

Figure 30. Buck Efficiency vs. Load Current, Across Temperature,

_IN= 5.0 V, V_OUT1= 1.2 V, PWM Mode

V

100

90

80

70

60

50

40

30

20

10

0

2.5

V

= 3.3V

OUT

2.0

1.5

1.0

0.5

0

–40°C

+25°C

+85°C

0.001

0.01

0.1

1

3.4

3.9

4.4

4.9

5.4

OUTPUT CURRENT (A)

V

(V)

IN

Figure 28. Buck Efficiency vs. Load Current, Across Temperature,

V_IN= 5.0 V, V_OUT1= 1.8 V, PWM Mode

Figure 31. Buck DC Current Capability vs. Input Voltage

2.0

100

90

80

70

60

50

40

30

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

V

= 1.8V

OUT

20

–40°C

+25°C

+85°C

10

0

2.4

2.9

3.4

3.9

4.4

4.9

5.4

0.0001

0.001

0.01

0.1

1

V

(V)

OUTPUT CURRENT (A)

IN

Figure 29. Buck Efficiency vs. Load Current, Across Temperature,

_IN= 5.0 V, V_OUT1= 1.2 V, Auto Mode

Figure 32. Buck DC Current Capability vs. Input Voltage

V

Rev. 0 | Page 12 of 40

Data Sheet

ADP5040

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

V

OUT

V

= 1.2V

OUT

4

2

I

SW

3

0

2.4

B

CH2 200mA/DIV 1MΩ

20.0M A CH1

20.0M

640mV 5µs/DIV

W

2.9

3.4

3.9

4.4

4.9

5.4

500MS/s

2.0ns/pt

CH3

CH4

3.0V/DIV

40.0mV/DIV

1MΩ

V

(V)

IN

Figure 33. Buck DC Current Capability vs. Input Voltage

Figure 36. Typical Waveforms, V_OUT1= 1.8 V, I_OUT1= 30 mA, Auto Mode

2.94

2.92

2.90

2.88

2.86

2.84

2.82

2.80

V

OUT

4

2

I

SW

–40°C

+25°C

+85°C

3

B

0

0.2

0.4

0.6

0.8

1.0

1.2

CH2 200mA/DIV 1MΩ

CH3

CH4

20.0M A CH3

20.0M

1.14V

5µs/DIV

500MS/s

2.0ns/pt

W

3.0V/DIV

40.0mV/DIV

1MΩ

OUTPUT CURRENT (A)

Figure 34. Buck Switching Frequency vs. Output Current,

Across Temperature, V_OUT1= 1.8 V, PWM Mode

Figure 37. Typical Waveforms, V_OUT1= 1.2 V, I_OUT1= 30 mA, Auto Mode

V

OUT

4

2

V

4

2

OUT

I

SW

I

SW

3

B

CH2 200mA/DIV 1MΩ

20.0M A CH1

20.0M

640mV 5µs/DIV

500MS/s

CH2 200mA/DIV 1MΩ

20.0M A CH1

20.0M

640mV 200ns/DIV

500MS/s

W

CH3

CH4

3.0V/DIV

40.0mV/DIV

1MΩ

CH3

CH4

3.0V/DIV

10.0mV/DIV

1MΩ

2.0ns/pt

Figure 35. Typical Waveforms, V_OUT1= 3.3 V, I_OUT1= 30 mA, Auto Mode

Figure 38. Typical Waveforms, V_OUT1= 3.3 V, I_OUT1= 30 mA, PWM Mode

Rev. 0 | Page 13 of 40

ADP5040

Data Sheet

V

OUT

4

V

IN

I

OUT

SW

2

3

1

SW

3

B

CH1 3.0V/DIV

CH2 30.0mV/DIV

400M A CH3

B

20.0M

W

4.48V

200µs/DIV

1.0MS/s

1.0µs/pt

CH2 200mA/DIV 1MΩ

20.0M A CH1

20.0M

640mV 200ns/DIV

500MS/s

W

CH3

CH4

3.0V/DIV

20.0mV/DIV

1MΩ

2.0ns/pt

B

1.0V/DIV

1MΩ

20.0M

CH3

W

Figure 42. Buck Response to Line Transient, Input Voltage from 4.5 V to

5.0 V, V_OUT1= 1.8 V, I_OUT1= 5 mA, Auto Mode

Figure 39. Typical Waveforms, V_OUT1= 1.8 V, I_OUT1= 30 mA, PWM Mode

V

OUT

V

IN

4

2

I

OUT

SW

2

SW

3

1

SW

3

B

CH1 3.0V/DIV

400M A CH3

20.0M

4.48V

200µs/DIV

1.0MS/s

1.0µs/pt

B

W

CH2 200mA/DIV 1MΩ

20.0M A CH3

20.0M

1.14V

200ns/DIV

500MS/s

2.0ns/pt

W

B

CH2

CH3

50.0mV/DIV

1.0V/DIV

W

CH3

CH4

3.0V/DIV

40.0mV/DIV

1MΩ

B

1MΩ

W

Figure 43. Buck Response to Line Transient, Input Voltage from 4.5 V to

5.0 V, V_OUT1= 1.2 V, I_OUT1= 5 mA, Auto Mode

Figure 40. Typical Waveforms, V_OUT1= 1.2 V, I_OUT1= 30 mA, PWM Mode

V

IN

V

IN

OUT

2

SW

3

1

3

1

SW

B

CH1 3.0V/DIV

400M A CH3

20.0M

4.48V

200µs/DIV

1.0MS/s

1.0µs/pt

W

B

CH2

CH3

50.0mV/DIV

1.0V/DIV

W

B

1MΩ

CH1 3.0V/DIV

400M A CH3

20.0M

4.48V

200µs/DIV

1.0MS/s

1.0µs/pt

W

B

CH2

CH3

50.0mV/DIV

1.0V/DIV

W

B

1MΩ

W

Figure 44. Buck Response to Line Transient, Input Voltage from 4.5 V to

5.0 V, V_OUT1= 3.3 V, PWM Mode

Figure 41. Buck Response to Line Transient, Input Voltage from 4.5 V to

5.0 V, V_OUT1= 3.3 V, I_OUT1= 5 mA, Auto Mode

Rev. 0 | Page 14 of 40

Data Sheet

ADP5040

SW

V

IN

1

2

V

OUT

V

OUT

2

SW

3

1

I

OUT

3

B

1MΩ

100mV/DIV

300mA/DIV 1MΩ

20.0M

CH1 3.0V/DIV

400M A CH3

20.0M

4.48V

200µs/DIV

1.0MS/s

1.0µs/pt

CH1 4.0V/DIV

CH2

CH3

A CH3

150mA 500µs/DIV

W

B

20.0MS/s

50.0ns/pt

CH2

CH3

20.0mV/DIV

1.0V/DIV

W

B

1MΩ

W

Figure 45. Buck Response to Line Transient, Input Voltage from 4.5 V to

5.0 V, V_OUT1= 1.8 V, PWM Mode

Figure 48. Buck Response to Load Transient, I_OUT1= 50 mA to 500 mA,

V_OUT1= 3.3 V, Auto Mode

SW

V

IN

1

V

OUT

2

SW

3

1

I

OUT

3

B

1MΩ

100mV/DIV

300mA/DIV 1MΩ

20.0M

CH1 3.0V/DIV

20.0M A CH3

20.0M

4.48V

200µs/DIV

1.0MS/s

1.0µs/pt

CH1 4.0V/DIV

CH2

CH3

A CH3

150mA 500µs/DIV

20.0MS/s

W

B

CH2

CH3

50.0mV/DIV

1.0V/DIV

W

50.0ns/pt

1MΩ

Figure 46. Buck Response to Line Transient, Input Voltage from 4.5 V to

5.0 V, V_OUT1= 1.2 V, PWM Mode

Figure 49. Buck Response to Load Transient, I_OUT1= 20 mA to 200 mA,

V

_OUT1= 1.8 V, Auto Mode

SW

1

2

V

OUT

V

OUT

2

I

OUT

3

B

1MΩ

100mV/DIV

300mA/DIV 1MΩ

20.0M

1MΩ

100mV/DIV

300mA/DIV 1MΩ

20.0M

CH1 4.0V/DIV

CH2

CH3

A CH3

150mA 500µs/DIV

20.0MS/s

CH1 4.0V/DIV

CH2

CH3

A CH3

150mA

500µs/DIV

20.0MS/s

50.0ns/pt

W

B

W

B

50.0ns/pt

Figure 47. Buck Response to Load Transient, I_OUT1= 20 mA to 200 mA,

V_OUT1= 3.3 V, Auto Mode

Figure 50. Buck Response to Load Transient, I_OUT1= 50 mA to 500 mA,

V_OUT1= 1.8 V, Auto Mode

Rev. 0 | Page 15 of 40

ADP5040

Data Sheet

SW

1

2

V

OUT

V

OUT

2

I

OUT

3

B

1MΩ

50.0mV/DIV

100mA/DIV 1MΩ

20.0M

120M

1MΩ

50.0mV/DIV

300mA/DIV 1MΩ

20.0M

CH1 4.0V/DIV

CH2

CH3

A CH3

94.0mA 200µs/DIV

500kS/s

CH1 4.0V/DIV

CH2

CH3

A CH3

150mA 500µs/DIV

W

B

20.0MS/s

50.0ns/pt

W

B

2.0µs/pt

W

Figure 51. Buck Response to Load Transient, I_OUT1= 20 mA to 200 mA,

V_OUT1= 1.2 V, Auto Mode

Figure 54. Buck Response to Load Transient, I_OUT1= 50 mA to 500 mA,

V_OUT1= 3.3 V, PWM Mode

SW

1

V

OUT

V

OUT

2

I

OUT

3

B

20.0M

120M

4.0V/DIV

50.0mV/DIV

1MΩ

20.0M

CH1 4.0V/DIV

A CH3

92.0mA 200µs/DIV

500kS/s

CH1

CH2

CH3

A CH3

150mA 500µs/DIV

20.0MS/s

W

B

CH2

CH3

50.0mV/DIV

200mA/DIV 1MΩ

W

B

2.0µs/pt

50.0ns/pt

300mA/DIV 1MΩ

W

Figure 52. Buck Response to Load Transient, I_OUT1= 50 mA to 500 mA,

Figure 55. Buck Response to Load Transient, I_OUT1= 20 mA to 200 mA,

V

_OUT1= 1.2 V, Auto Mode

V

_OUT1= 1.8 V, PWM Mode

SW

1

2

1

2

V

OUT

I

OUT

3

B

1MΩ

50.0mV/DIV

300mA/DIV 1MΩ

20.0M

1MΩ

100mV/DIV

300mA/DIV 1MΩ

20.0M

CH1 4.0V/DIV

CH2

CH3

A CH3

150mA 500µs/DIV

20.0MS/s

CH1 4.0V/DIV

CH2

CH3

A CH3

150mA

500µs/DIV

20.0MS/s

50.0ns/pt

W

B

W

B

50.0ns/pt

Figure 53. Buck Response to Load Transient, I_OUT1= 20 mA to 200 mA,

V_OUT1= 3.3 V, PWM Mode

Figure 56. Buck Response to Load Transient, I_OUT1= 50 mA to 500 mA,

V_OUT1= 1.8 V, PWM Mode

Rev. 0 | Page 16 of 40

Data Sheet

ADP5040

1

SW

I

IN

V

OUT

2

V

OUT

I

OUT

EN

3

B

CH1 4.0V/DIV

20.0M A CH3

20.0M

120.0M

94.0mA 200µs/DIV

500kS/s

B

W

CH1 2.0V/DIV

1MΩ

20.0M A CH1

20.0M

1.72V

50.0µs/DIV

200MS/s

5.0ns/pt

W

CH2

CH3

50.0mV/DIV

100mA/DIV 1MΩ

CH2

CH3

2.0V/DIV

200mA/DIV

B

2.0ns/pt

W

Figure 57. Buck Response to Load Transient, I_OUT1= 20 mA to 200 mA,

V_OUT1= 1.2 V, PWM Mode

Figure 60. LDO1, LDO2 Startup, V_OUT= 3.3 V, I_OUT= 5 mA

1

I

IN

3

2

SW

V

OUT

2

V

OUT

I

EN

OUT

1

3

CH1 4.0V/DIV

20.0M A CH3

20.0M

92.0mA 200µs/DIV

500kS/s

B

CH1 2.0V/DIV

1MΩ

20.0M A CH1

20.0M

760mV 50.0µs/DIV

200MS/s

W

CH2

CH3

50.0mV/DIV

200mA/DIV 1MΩ

CH2

CH3

1.0V/DIV

200mA/DIV

B

2.0ns/pt

W

5.0ns/pt

Figure 58. Buck Response to Load Transient, I_OUT1= 50 mA to 500 mA,

Figure 61. LDO1, LDO2 Startup, V_OUT= 1.8 V, I_OUT= 5 mA

V

_OUT1= 1.2 V, PWM Mode

I

IN

I

IN

3

2

V

OUT

V

OUT

2

1

EN

1

B

CH1 2.0V/DIV

1MΩ

20.0M A CH1

20.0M

1.72V

50.0µs/DIV

200MS/s

5.0ns/pt

W

B

CH1 2.0V/DIV

1MΩ

20.0M A CH1

20.0M

1.72V

50.0µs/DIV

200MS/s

5.0ns/pt

B

W

CH2

CH3

2.0V/DIV

200mA/DIV

CH2

CH3

1.0V/DIV

200mA/DIV

Figure 59. LDO1, LDO2 Startup, V_OUT= 4.7 V, I_OUT= 5 mA

Figure 62. LDO1, LDO2 Startup, V_OUT= 1.2 V, I_OUT= 5 mA

Rev. 0 | Page 17 of 40

ADP5040

Data Sheet

1.220

1.215

1.210

1.205

1.200

1.195

1.190

1.185

3.6V

4.5V

5.5V

2.8V

4.758

4.708

4.658

5.5V

5.0V

4.608

0.001

1.180

0.01

0.1

0.001

0.01

0.1

OUTPUT CURRENT (A)

Figure 66. LDO1, LDO2 Load Regulation Across Input Voltage, V_OUT= 1.2 V

Figure 63. LDO1, LDO2 Load Regulation Across Input Voltage, V_OUT= 4.7 V

3.40

3.38

3.36

3.34

–40°C

+25°C

+85°C

3.38

3.36

3.34

3.32

3.30

3.28

3.26

3.24

3.22

3.20

3.32

5.5V

3.30

3.28

3.26

4.5V

3.6V

3.24

3.22

3.20

0.001

0.01

0.1

0.001

0.01

0.1

OUTPUT CURRENT (A)

Figure 67. LDO1, LDO2 Load Regulation Across Temperature, V_IN= 3.6 V,

_OUT= 3.3 V

Figure 64. LDO1, LDO2 Load Regulation Across Input Voltage, V_OUT= 3.3 V

V

1.800

3.6V

4.5V

1.800

1.795

1.790

1.785

1.780

1.775

–40°C

+25°C

+85°C

5.5V

2.8V

1.795

1.790

1.785

1.780

1.775

1.770

0.001

0.01

0.1

0.001

0.01

0.1

OUTPUT CURRENT (A)

Figure 65. LDO1, LDO2 Load Regulation Across Input Voltage, V_OUT= 1.8 V

Figure 68. LDO1, LDO2 Load Regulation Across Temperature, V_IN= 3.6 V,

_OUT= 1.8 V

V

Rev. 0 | Page 18 of 40

Data Sheet

ADP5040

1.820

1.815

1.810

1.805

1.800

1.795

1.790

1.220

1.215

1.210

1.205

1.200

1.195

1.190

1.185

–40°C

+25°C

+85°C

100µA

1mA

10mA

100mA

200mA

1.180

0.001

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0.01

0.1

INPUT VOLTAGE (V)

OUTPUT CURRENT (A)

Figure 72. LDO1, LDO2 Line Regulation Across Input Voltage, V_OUT= 1.8 V

Figure 69. LDO1, LDO2 Load Regulation Across Temperature, V_IN= 3.6 V,

V_OUT= 1.2 V

1.201

4.75

100µA

1mA

10mA

100mA

200mA

100µA

1mA

10mA

100mA

200mA

1.200

1.199

1.198

1.197

1.196

1.195

1.194

1.193

1.192

4.73

4.71

4.69

4.67

4.65

2.5

3.0

3.5

4.0

4.5

5.0

5.5

5.0

5.1

5.2

5.3

5.4

5.5

INPUT VOLTAGE (V)

Figure 70. LDO1, LDO2 Line Regulation Across Input Voltage, V_OUT= 4.7 V

Figure 73. LDO1, LDO2 Line Regulation Across Input Voltage, V_OUT= 1.2 V

3.310

200

180

100µA

1mA

3.305

3.300

3.295

3.290

3.285

3.280

10mA

100mA

200mA

160

140

120

100

80

60

40

20

0

3.6

3.9

4.2

4.5

4.8

5.1

5.4

0

0.05

0.10

0.15

0.20

0.25

0.30

INPUT VOLTAGE (V)

OUTPUT CURRENT (A)

Figure 71. LDO1, LDO2 Line Regulation Across Input Voltage, V_OUT= 3.3 V

Figure 74. LDO1, LDO2 Ground Current vs. Output Current, V_OUT= 3.3 V

Rev. 0 | Page 19 of 40

ADP5040

Data Sheet

200

180

160

140

120

100

80

V

OUT

2

0.000001A

0.0001A

0.001A

0.01A

60

40

I

OUT

0.1A

3

20

0.15A

0.3A

0

3.8

B

CH2 30.0mV/DIV

CH3

20.0M A CH3

120M

42.0mA 200µs/DIV

W

4.3

4.8

5.3

B

500kS/s

2.0µs/pt

50.0mA/DIV 1MΩ

W

INPUT VOLTAGE (V)

Figure 78. LDO1, LDO2 Response to Load Transient, I_OUTfrom 1 mA to

80 mA, V_OUT= 3.3 V

Figure 75. LDO1, LDO2 Ground Current vs. Input Voltage, Across Output

Load (A), V_OUT= 3.3 V

V

OUT

2

V

OUT

2

I

OUT

I

OUT

3

B

CH2 50.0mV/DIV

CH3

20.0M A CH3

120M

89.6mA 200µs/DIV

500kS/s

CH2 30.0mV/DIV

CH3

20.0M A CH3

20.0M

27.2mA 200µs/DIV

5.0MS/s

W

B

80.0mA/DIV

1MΩ

80.0mA/DIV 1MΩ

W

2.0µs/pt

200ns/pt

Figure 79. LDO1, LDO2 Response to Load Transient, I_OUTfrom 10 mA to

200 mA, V_OUT= 3.3 V

Figure 76. LDO1, LDO2 Response to Load Transient, I_OUTfrom 1 mA to

80 mA, V_OUT= 4.7 V

V

OUT

2

V

OUT

2

I

OUT

I

OUT

3

B

CH2 30.0mV/DIV

CH3

20.0M A CH3

120M

89.6mA 200µs/DIV

500kS/s

CH2 30.0mV/DIV

CH3

20.0M A CH3

20.0M

27.2mA 200µs/DIV

5.0MS/s

W

B

80.0mA/DIV

1MΩ

80.0mA/DIV 1MΩ

W

2.0µs/pt

200ns/pt

Figure 80. LDO1, LDO2 Response to Load Transient, I_OUTfrom 1 mA to

80 mA, V_OUT= 1.8 V

Figure 77. LDO1, LDO2 Response to Load Transient, I_OUTfrom 10 mA to

200 mA, V_OUT= 4.7 V

Rev. 0 | Page 20 of 40

Data Sheet

ADP5040

V

IN

V

OUT

2

OUT

2

3

I

OUT

3

B

CH2 50.0mV/DIV

CH3

20.0M A CH3

120M

89.6mA 200µs/DIV

500kS/s

CH2 20.0mV/DIV

CH3

1MΩ

20.0M A CH3

20.0M

4.84V

200µs/DIV

1.0MS/s

1.0µs/pt

W

B

80.0mA/DIV 1MΩ

1.0V/DIV

W

2.0µs/pt

Figure 81. LDO1, LDO2 Response to Load Transient, I_OUTfrom 10 mA to

200 mA, V_OUT= 1.8 V

Figure 84. LDO1, LDO2 Response to Line Transient, Input Voltage from

4.5 V to 5.5 V, V_OUT= 3.3 V

V

OUT

V

IN

2

V

OUT

2

3

I

OUT

3

B

CH2 30.0mV/DIV

CH3

20.0M A CH3

20.0M

27.2mA 200µs/DIV

5.0MS/s

CH2 20.0mV/DIV

CH3

1MΩ

20.0M A CH3

20.0M

4.86V

500µs/DIV

1.0MS/s

1.0µs/pt

W

80.0mA/DIV 1MΩ

1.0V/DIV

200ns/pt

Figure 82. LDO1, LDO2 Response to Load Transient, I_OUTfrom 1 mA to

80 mA, V_OUT= 1.2 V

Figure 85. LDO1, LDO2 Response to Line Transient, Input Voltage from

4.5 V to 5.5 V, V_OUT= 1.8 V

V

OUT

2

V

IN

V

OUT

2

3

I

OUT

3

B

CH2 30.0mV/DIV

CH3

20.0M A CH3

20.0M

27.2mA 200µs/DIV

5.0MS/s

CH2 20.0mV/DIV

CH3

1MΩ

20.0M A CH3

20.0M

4.48V

200µs/DIV

1.0MS/s

1.0µs/pt

W

80.0mA/DIV 1MΩ

1.0V/DIV

200ns/pt

Figure 83. LDO1, LDO2 Response to Load Transient, I_OUTfrom 10 mA to

200 mA, V_OUT= 1.2 V

Figure 86. LDO1, LDO2 Response to Line Transient, Input Voltage from

4.5 V to 5.5 V, V_OUT= 1.2 V

Rev. 0 | Page 21 of 40

ADP5040

Data Sheet

V

IN

100

V

OUT

2

3

CH2; V

= 3.3V; V = 5V

IN

OUT

= 3.3V; V = 3.6V

IN

= 2.8V; V = 3.1V

IN

= 1.5V; V = 5V

IN

= 1.5V; V = 1.8V

IN

10

0.0001 0.001

B

CH2 20.0mV/DIV

CH3

20.0M A CH3

20.0M

4.02V

200µs/DIV

1.0MS/s

1.0µs/pt

0.01

0.1

1

10

100

1k

W

1.0V/DIV

1MΩ

LOAD (mA)

Figure 87. LDO1, LDO2 Response to Line Transient, Input Voltage from

3.3 V to 3.8 V, V_OUT= 1.8 V

Figure 90. LDO1 Output Noise vs. Load Current, Across Input and

Output Voltage

V

IN

100

OUT

2

3

CH3; V

= 3.3V; V = 5V

IN

OUT

= 3.3V; V = 3.6V

IN

= 2.8V; V = 3.1V

IN

= 1.5V; V = 5V

IN

= 1.5V; V = 1.8V

IN

10

B

0.0001 0.001

0.01

0.1

1

10

100

1k

CH2 20.0mV/DIV

CH3

20.0M A CH3

20.0M

4.84V

200µs/DIV

1.0MS/s

1.0µs/pt

W

1.0V/DIV

1MΩ

LOAD (mA)

Figure 88. LDO1, LDO2 Response to Line Transient, Input Voltage from

3.3 V to 3.8 V, V_OUT= 1.2 V

Figure 91. LDO2 Output Noise vs. Load Current, Across Input and Output

Voltage

0.7

100

V

= 3.3V, V

= 1.5V, V

= 2.8V, V

= 3.6V, I

= 1.8V, I

= 3.1V, I

= 300mA

OUT2

IN2

LOAD

0.6

V

= 3.3V

OUT

10

1.0

0.5

0.4

0.3

0.2

0.1

0

0.1

0.01

3.6

4.1

4.6

(V)

5.1

5.6

10

100

1k

10k

100k

1M

10M

V

IN

FREQUENCY (Hz)

Figure 92. LDO1 Noise Spectrum Across Output Voltage,

V_IN= V_OUT+ 0.3 V

Figure 89. LDO1, LDO2 Output Current Capability vs. Input Voltage

Rev. 0 | Page 22 of 40

Data Sheet

ADP5040

–10

–20

100

V

= 3.3V, V

= 1.5V, V

= 2.8V, V

= 3.6V, I

= 1.8V, I

= 3.1V, I

= 300mA

OUT3

IN3

LOAD

1mA

10mA

100mA

200mA

300mA

–30

–40

10

1

–50

–60

–70

–80

0.1

0.01

–90

–100

1

10

100

1k

10k

100k

1M

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 93. LDO2 Noise Spectrum Across Output Voltage,

V_IN= V_OUT+ 0.3 V

Figure 96. LDO2 PSRR Across Output Load,

_IN3= 3.1 V, V_OUT3= 2.8 V

V

100

–10

–20

V

= 3.3V, V

= 1.5V, V

= 3.6V, I

= 1.8V, I

= 300mA

1mA

OUT2

OUT3

OUT2

IN2

IN3

IN2

LOAD

10mA

100mA

200mA

–30

–40

10

–50

–60

–70

–80

1.0

0.1

V

= 1.5V, V

= 2.8V, V

= 1.8V, I

= 3.1V, I

= 300mA

OUT3

OUT2

OUT3

IN3

IN2

IN3

LOAD

–90

0.01

–100

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 94. LDO1 vs. LDO2 Noise Spectrum

Figure 97. LDO2 PSRR Across Output Load,

V_IN3= 5.0 V, V_OUT3= 3.3 V

–10

–20

–10

–20

1mA

10mA

100mA

200mA

300mA

10mA

100mA

200mA

300mA

–30

–40

–30

–40

–50

–60

–70

–80

–50

–60

–70

–80

–90

–100

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 95. LDO2 PSRR Across Output Load,

_IN3= 3.3 V, V_OUT3= 2.8 V

Figure 98. LDO2 PSRR Across Output Load,

V_IN3= 3.6 V, V_OUT3= 3.3 V

V

Rev. 0 | Page 23 of 40

ADP5040

Data Sheet

–10

–20

1mA

10mA

100mA

200mA

10mA

100mA

200mA

300mA

–20

–30

–40

–30

300mA

–40

–50

–60

–70

–80

–50

–60

–70

–80

–90

–100

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 100. LDO1 PSRR Across Output Load,

V_IN2= 1.8 V, V_OUT2= 1.5 V

Figure 99. LDO1 PSRR Across Output Load,

V_IN2= 5.0 V, V_OUT2= 1.5 V

Rev. 0 | Page 24 of 40

Data Sheet

ADP5040

THEORY OF OPERATION

VOUT1 FB1

85Ω

ENBK

AVIN

VIN1

VDDA

GM ERROR

AMP

ENBK

ENLDO1

ENLDO2

MODE

EN1

PWM

COMP

ENABLE

& MODE

CONTROL

EN2

SOFT START

MODE

EN3

PSM

COMP

SEL

I

LIMIT

OPMODE_FUSES

PWM/

PSM

LOW

CURRENT

CONTROL

BUCK1

SW

OSCILLATOR

SYSTEM

UNDERVOLTAGE

LOCK OUT

DRIVER

AND

ANTISHOOT

THROUGH

600Ω

PGND

ENLDO2

THERMAL

SHUTDOWN

AGND

LDO2

CONTROL

LDO1

CONTROL

VDDA

600Ω

ENLDO1

ADP5040

VIN2

FB2 VOUT2

VIN3

FB3 VOUT3

Figure 101. Functional Block Diagram

The buck regulator can operate in forced PWM mode if the

MODE pin is at a logic high level. In forced PWM mode, the

switching frequency of the buck is always constant and does not

change with the load current. If the MODE pin is at a logic low

level, the switching regulator operates in auto PWM/PSM mode.

In this mode, the regulator operates at fixed PWM frequency

when the load current is above the power saving current threshold.

When the load current falls below the power save current

threshold, the regulator enters power saving mode, where the

switching occurs in bursts. The burst repetition rate is a

function of the current load and the output capacitor value.

This operating mode reduces the switching and quiescent

current losses.

POWER MANAGEMENT UNIT

The ADP5040 is a micro power management unit (micro PMU)

combing one step-down (buck) dc-to-dc regulator and two low

dropout linear regulators (LDOs). The high switching frequency

and tiny 20-pin LFCSP package allow for a small power

management solution.

The regulators are activated by a logic level high applied to the

respective EN pin. The EN1 pin controls the buck regulator, the

EN2 pin controls LDO1, and the EN3 pin controls LDO2. The

MODE pin controls the buck switching operation.

The regulator output voltages are set through external resistor

dividers.

When a regulator is turned on, the output voltage ramp is

controlled through a soft start circuit to avoid a large inrush

current due to the discharged output capacitors.

Rev. 0 | Page 25 of 40

ADP5040

Data Sheet

VOUT1

SW

Thermal Protection

VIN1

L1 – 1µH

In the event that the junction temperature rises above 150°C,

the thermal shutdown circuit turns off the buck and the LDOs.

Extreme junction temperatures can be the result of high current

operation, poor circuit board design, or high ambient temperature.

A 20°C hysteresis is included in the thermal shutdown circuit so

that when thermal shutdown occurs, the buck and the LDOs do

not return to normal operation until the on-chip temperature

drops below 130°C. When coming out of thermal shutdown, all

regulators start with soft start control.

VOUT1

BUCK

R1

R2

FB1

C5

10µF

AGND

Undervoltage Lockout

Figure 102. Buck External Output Voltage Setting

To protect against battery discharge, undervoltage lockout

(UVLO) circuitry is integrated in the ADP5040. If the input

voltage on AVIN drops below a typical 2.15 V UVLO threshold,

all channels shut down. In the buck channel, both the power

switch and the synchronous rectifier turn off. When the voltage

on AVIN rises above the UVLO threshold, the part is enabled

once more.

Control Scheme

The buck operates with a fixed frequency, current mode PWM

control architecture at medium to high loads for high efficiency,

but operation shifts to a power save mode (PSM) control

scheme at light loads to lower the regulation power losses.

When operating in fixed frequency PWM mode, the duty cycle

of the integrated switches is adjusted and regulates the output

voltage. When operating in PSM at light loads, the output

voltage is controlled in a hysteretic manner, with higher output

voltage ripple. During part of this time, the converter is able to

stop switching and enters an idle mode, which improves

conversion efficiency.

Alternatively, the user can select device models with a UVLO

set at a higher level, suitable for 5 V applications. For these

models, the device reaches the turn-off threshold when the

input supply drops to 3.65 V typical.

Enable/Shutdown

The ADP5040 has individual control pins for each regulator.

A logic level high applied to the ENx pin activates a regulator,

whereas a logic level low turns off a regulator.

PWM Mode

In PWM mode, the buck operates at a fixed frequency of 3 MHz,

set by an internal oscillator. At the start of each oscillator cycle,

the PFET switch is turned on, sending a positive voltage across

the inductor. Current in the inductor increases until the current

sense signal crosses the peak inductor current threshold that

turns off the PFET switch and turns on the NFET synchronous

rectifier. This sends a negative voltage across the inductor,

causing the inductor current to decrease. The synchronous

rectifier stays on for the rest of the cycle. The buck regulates the

output voltage by adjusting the peak inductor current threshold.

Active Pull-Down

The ADP5040 can be purchased with the active pull-down

option enabled. The pull-down resistors are connected between

each regulator output and AGND. The pull-downs are enabled,

when the regulators are turned off. The typical value of the pull-

down resistor is 600 Ω for the LDOs and 85 Ω for the buck.

BUCK SECTION

The buck uses a fixed frequency and high speed current mode

architecture. The buck operates with an input voltage of 2.3 V

to 5.5 V.

Power Save Mode (PSM)

The buck smoothly transitions to PSM operation when the load

current decreases below the PSM current threshold. When the

buck enters power save mode, an offset is introduced in the

PWM regulation level, which makes the output voltage rise.

When the output voltage reaches a level that is approximately

1.5% above the PWM regulation level, PWM operation is

turned off. At this point, both power switches are off, and the

buck enters an idle mode. The output capacitor discharges until

the output voltage falls to the PWM regulation voltage, at which

point the device drives the inductor to make the output voltage

rise again to the upper threshold. This process is repeated while

the load current is below the PSM current threshold.

The buck output voltage is set though external resistor dividers,

as shown in Figure 102. VOUT1 must be connected to the

output capacitor. VFB1 is internally set to 0.5 V. The output

voltage can be set from 0.8 V to 3.8 V.

Rev. 0 | Page 26 of 40

Data Sheet

ADP5040

The ADP5040 has a dedicated MODE pin controlling the PSM

and PWM operation. A high logic level applied to the MODE

pin forces the buck to operate in PWM mode. A logic level low

sets the buck to operate in auto PSM/PWM.

switch on 100% of the time, the output voltage drops below the

desired output voltage. At this limit, the buck transitions to a

mode where the PFET switch stays on 100% of the time. When

the input conditions change again and the required duty cycle

falls, the buck immediately restarts PWM regulation without

allowing overshoot on the output voltage.

PSM Current Threshold

The PSM current threshold is set to 100 mA. The buck employs

a scheme that enables this current to remain accurately con-

trolled, independent of input and output voltage levels. This

scheme also ensures that there is very little hysteresis between

the PSM current threshold for entry to, and exit from, the PSM

mode. The PSM current threshold is optimized for excellent

efficiency over all load currents.

LDO SECTION

The ADP5040 contains two LDOs with low quiescent current

that provide output currents up to 300 mA. The low 10 μA

typical quiescent current at no load makes the LDO ideal for

battery-operated portable equipment.

The LDOs operate with an input voltage range of 1.7 V to 5.5 V.

The wide operating range makes these LDOs suitable for

cascade configurations where the LDO supply voltage is

provided from the buck regulator.

Short-Circuit Protection

The buck includes frequency foldback to prevent current

runaway on a hard short at the output. When the voltage at the

feedback pin falls below half the internal reference voltage,

indicating the possibility of a hard short at the output, the

switching frequency is reduced to half the internal oscillator

frequency. The reduction in the switching frequency allows

more time for the inductor to discharge, preventing a runaway

of output current.

Each LDO output voltage is set though external resistor dividers

as shown in Figure 103. V_FB2and V_FB3are internally set to 0.5 V. The

output voltage can be set from 0.8 V to 5.2 V.

VOUT2, VOUT3

VIN2, VIN3

VOUT2,

VOUT3

LD01, LD02

C7

2.2µF

R

A

B

Soft Start

FB2, FB3

The buck has an internal soft start function that ramps the

output voltage in a controlled manner upon startup, thereby

limiting the inrush current. This prevents possible input voltage

drops when a battery or a high impedance power source is

connected to the input of the converter.

Figure 103. LDOs External Output Voltage Setting

Current Limit

The LDOs also provide high power supply rejection ratio (PSRR),

low output noise, and excellent line and load transient response

with small 1 µF ceramic input and output capacitors.

The buck has protection circuitry to limit the amount of

positive current flowing through the PFET switch and the

amount of negative current flowing through the synchronous

rectifier. The positive current limit on the power switch limits

the amount of current that can flow from the input to the

output. The negative current limit prevents the inductor

current from reversing direction and flowing out of the load.

LDO2 is optimized to supply analog circuits because it offers

better noise performance compared to LDO1. LDO1 should be

used in applications where noise performance is not critical.

100% Duty Operation

With a dropping input voltage or with an increase in load

current, the buck may reach a limit where, even with the PFET

Rev. 0 | Page 27 of 40

ADP5040

Data Sheet

NO POWER APPLIED TO AVIN.

ALL REGULATORS TURNED OFF

NO POWER

AVIN > VUVLO

AVIN < VUVLO

TRANSITION

STATE

POR

INTERNAL CIRCUIT BIASED

REGULATORS NOT ACTIVATED

END OF POR

STANDBY

AVIN < VUVLO

ALL ENx = LOW

ENx = HIGH

ACTIVE

ALL REGULATORS ACTIVATED

Figure 104. ADP5040 State Flow

Rev. 0 | Page 28 of 40

Data Sheet

ADP5040

APPLICATIONS INFORMATION

Ceramic capacitors are manufactured with a variety of dielec-

trics, each with a different behavior over temperature and

applied voltage. Capacitors must have a dielectric adequate

to ensure the minimum capacitance over the necessary

temperature range and dc bias conditions. X5R or X7R

dielectrics with a voltage rating of 6.3 V or 10 V are highly

recommended for best performance. Y5V and Z5U dielectrics

are not recommended for use with any dc-to-dc converter

because of their poor temperature and dc bias characteristics.

BUCK EXTERNAL COMPONENT SELECTION

Trade-offs between performance parameters such as efficiency

and transient response are made by varying the choice of

external components in the applications circuit, as shown in

Figure 1.

Feedback Resistors

Referring to Figure 102, the total combined resistance for R1

and R2 is not to exceed 400 kΩ.

Inductor

The worst-case capacitance accounting for capacitor variation

over temperature, component tolerance, and voltage is calcu-

lated using the following equation:

The high switching frequency of the ADP5040 buck allows for

the selection of small chip inductors. For best performance, use

inductor values between 0.7 μH and 3.0 μH. Suggested inductors

are shown in Table 8.

C

_EFF= C_OUT× (1 − TEMPCO) × (1 − TOL)

where:

The peak-to-peak inductor current ripple is calculated using

the following equation:

C

_EFFis the effective capacitance at the operating voltage.

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

V_OUT×(V_IN−V_OUT

)

I_RIPPLE

=

In this example, the worst-case temperature coefficient (TEMPCO)

over −40°C to +85°C is assumed to be 15% for an X5R dielectric.

The tolerance of the capacitor (TOL) is assumed to be 10%, and

V

_IN× f_SW×L

where:

_SWis the switching frequency.

L is the inductor value.

f

C

_OUTis 9.2481 μF at 1.8 V, as shown in Figure 105.

Substituting these values in the equation yields

_EFF= 9.24 μF × (1 − 0.15) × (1 − 0.1) = 7.07 μF

The minimum dc current rating of the inductor must be greater

than the inductor peak current. The inductor peak current is

calculated using the following equation:

C

To guarantee the performance of the buck, it is imperative

that the effects of dc bias, temperature, and tolerances on the

behavior of the capacitors be evaluated for each application.

12

I_RIPPLE

2

I_PEAK= I_LOAD(MAX)

+

Table 8. Suggested 1.0 μH Inductors

Dimensions I_SAT

DCR

(mΩ)

10

8

Vendor

Model

(mm)

(mA)

1400

2300

2000

5400

1800

1350

Murata

LQM2MPN1R0NG0B

LQM18FN1R0M00B

CBC322ST1R0MR

XFL4020-102ME

XPL2010-102ML

MDT2520-CN

2.0 × 1.6 × 0.9

3.2 × 2.5 × 1.5

3.2 × 2.5 × 2.5

4.0 × 4.0 × 2.1

1.9 × 2.0 × 1.0

2.5 × 2.0 × 1.2

85

54

71

11

89

85

Murata

Tayo Yuden

Coilcraft

Toko

6

4

Inductor conduction losses are caused by the flow of current

through the inductor, which has an associated internal dc

resistance (DCR). Larger sized inductors have smaller DCR,

which may decrease inductor conduction losses. Inductor core

losses are related to the magnetic permeability of the core material.

Because the buck is high switching frequency dc-to-dc converter,

shielded ferrite core material is recommended for its low core

losses and low EMI.

2

0

1

2

3

4

5

6

DC BIAS VOLTAGE (V)

Figure 105. Typical Capacitor Performance

The peak-to-peak output voltage ripple for the selected output

capacitor and inductor values is calculated using the following

equation:

Output Capacitor

I_RIPPLE

V_IN

²× L ×C_OUT

Higher output capacitor values reduce the output voltage ripple

and improve load transient response. When choosing the

capacitor value, it is also important to account for the loss of

capacitance due to output voltage dc bias.

V_RIPPLE

=

≈

8× f_SW×C_OUT

(

2π × f_SW

)

Rev. 0 | Page 29 of 40

ADP5040

Data Sheet

Capacitors with lower equivalent series resistance (ESR) are

preferred to guarantee low output voltage ripple, as shown in

the following equation:

To minimize supply noise, place the input capacitor as close

to the VIN pin of the buck as possible. As with the output

capacitor, a low ESR capacitor is recommended.

V_RIPPLE

I_RIPPLE

The effective capacitance needed for stability, which includes

temperature and dc bias effects, is a minimum of 3 µF and a

maximum of 10 µF. A list of suggested capacitors is shown in

Table 10.

ESR_COUT

≤

The effective capacitance needed for stability, which includes

temperature and dc bias effects, is a minimum of 7 µF and a

maximum of 40 µF.

Table 10. Suggested 4.7 μF Capacitors

Voltage

Case Rating

Size (V)

GRM188R60J475ME19D 0603 6.3

Table 9. Suggested 10 μF Capacitors

Voltage

Rating

(V)

Vendor

Type Model

X5R

Case

Size

Murata

Taiyo Yuden X5R

Panasonic X5R

Vendor

Murata

Type

X5R

Model

JMK107BJ475

ECJ-0EB0J475M

0603 6.3

0402 6.3

GRM188R60J106

JMK107BJ106MA-T

C1608JB0J106K

ECJ1VB0J106M

0603

6.3

Taiyo Yuden

TDK

LDO EXTERNAL COMPONENT SELECTION

Panasonic

Feedback Resistors

Referring to Figure 103 the maximum value of Rb is not to

exceed 200 kΩ.

The buck regulator requires 10 µF output capacitors to guaran-

tee stability and response to rapid load variations and to transition

in and out the PWM/PSM modes. In certain applications, where

the buck regulator powers a processor, the operating state is

known because it is controlled by software. In this condition,

the processor can drive the MODE pin according to the operating

state; consequently, it is possible to reduce the output capacitor

from 10 µF to 4.7 µF because the regulator does not expect a

large load variation when working in PSM mode (see Figure 106).

Output Capacitor

The ADP5040 LDOs are designed for operation with small,

space-saving ceramic capacitors, but they function with most

commonly used capacitors as long as care is taken with the ESR

value. The ESR of the output capacitor affects stability of the

LDO control loop. A minimum of 0.70 µF capacitance with an

ESR of 1 Ω or less is recommended to ensure stability of the

LDO. Transient response to changes in load current is also

affected by output capacitance. Using a larger value of output

capacitance improves the transient response of the LDO to large

changes in load current.

ADP5040

MICRO PMU

R

30Ω

FLT

AVIN

L1

1µH

PROCESSOR

VCORE

SW

VOUT1

VIN1

V

IN

2.3V TO 5.5V

R1

R2

C4

4.7µF

When operating at output currents higher than 200 mA a

minimum of 2.2 µF capacitance with an ESR of 1 Ω or less is

recommended to ensure stability of the LDO.

C1

10µF

FB1

VIN2

PGND

C2

1µF

VOUT2

R3

R4

VIN3

VDDIO

Table 11. Suggested 2.2 μF Capacitors

C5

2.2µF

C3

1µF

FB2

Voltage

Rating

(V)

Case

Size

Vendor

Murata

Type

X5R

Model

0402

10.0

6.3

GRM188B31A225K

C1608JB0J225KT

ECJ1VB0J225K

JMK107BJ225KK-T

MODE

ENx

TDK

GPIO1

3

GPIO[x:y]

Panasonic

Taiyo Yuden

6.3

VOUT3

R5

R6

VANALOG

C6

2.2µF

ANALOG

SUBSYSTEM

FB3

Input Bypass Capacitor

Connecting 1 µF capacitors from VIN2 and VIN3 to ground

reduces the circuit sensitivity to printed circuit board (PCB)

layout, especially when long input traces or high source impedance

is encountered. If greater than 1 µF of output capacitance is

required, increase the input capacitor to match it.

Figure 106. Processor System Power Management with PSM/PWM Control

Input Capacitor

A higher value input capacitor helps to reduce the input voltage

ripple and improve transient response. Maximum input

capacitor current is calculated using the following equation:

V_OUT(V_IN−V_OUT

)

I_CIN≥ I_LOAD(MAX)

V_IN

Rev. 0 | Page 30 of 40

Data Sheet

ADP5040

X5R dielectric. The tolerance of the capacitor (TOL) is assumed

to be 10%, and C_BIASis 0.94 μF at 1.8 V as shown in Figure 107.

Table 12. Suggested 1.0 μF Capacitors

Voltage

Rating

(V)

Case

Size

Substituting these values into the following equation yields:

Vendor

Murata

TDK

Type

X5R

Model

C_EFF= 0.94 μF × (1 – 0.15) × (1 – 0.1) = 0.72 μF

GRM155R61A105ME15

C1005JB0J105KT

ECJ0EB0J105K

0402

10.0

6.3

Therefore, the capacitor chosen in this example meets the

minimum capacitance requirement of the LDO over

temperature and tolerance at the chosen output voltage.

Panasonic

Taiyo Yuden X5R

LMK105BJ105MV-F

10.0

Input and Output Capacitor Properties

To guarantee the performance of the ADP5040, it is imperative

that the effects of dc bias, temperature, and tolerances on the

behavior of the capacitors be evaluated for each application.

Use any good quality ceramic capacitor with the ADP5040 as

long as it meets the minimum capacitance and maximum ESR

requirements. Ceramic capacitors are manufactured with a variety

of dielectrics, each with a different behavior over temperature

and applied voltage. Capacitors must have a dielectric adequate

to ensure the minimum capacitance over the necessary tempe-

rature range and dc bias conditions. X5R or X7R dielectrics

with a voltage rating of 6.3 V or 10 V are recommended for best

performance. Y5V and Z5U dielectrics are not recommended

for use with any LDO because of their poor temperature and dc

bias characteristics.

POWER DISSIPATION/THERMAL CONSIDERATIONS

The ADP5040 is a highly efficient micropower management

unit (micro PMU), and in most cases the power dissipated in

the device is not a concern. However, if the device operates at

high ambient temperatures and with maximum loading

conditions, the junction temperature can reach the maximum

allowable operating limit (125°C).

When the junction temperature exceeds 150°C, the ADP5040

turns off all the regulators, allowing the device to cool down.

Once the die temperature falls below 135°C, the ADP5040

resumes normal operation.

Figure 107 depicts the capacitance vs. voltage bias characteristic

of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a

capacitor is strongly influenced by the capacitor size and voltage

rating. In general, a capacitor in a larger package or higher voltage

rating exhibits better stability. The temperature variation of the

X5R dielectric is about 15% over the −40°C to +85°C tempera-

ture range and is not a function of package or voltage rating.

1.2

This section provides guidelines to calculate the power dissi-

pated in the device and to make sure the ADP5040 operates

below the maximum allowable junction temperature.

The efficiency for each regulator on the ADP5040 is given by

P_OUT

P_IN

η =

×100%

(1)

1.0

0.8

0.6

where:

η is efficiency.

P

_INis the input power.

_OUTis the output power.

Power loss is given by

_LOSS= P_IN− P_OUT

or

_LOSS= P_OUT× (1 − η)/η

0.4

0.2

0

P

(2a)

(2b)

P

0

1

2

3

4

5

6

Power dissipation can be calculated in several ways. The most

intuitive and practical way is to measure the power dissipated at

the input and all the outputs. The measurements should be

performed at the worst-case conditions (voltages, currents,

and temperature). The difference between input and output

power is dissipated in the device and the inductor. Use

Equation 4 to derive the power lost in the inductor, and from

this use Equation 3 to calculate the power dissipation in the

ADP5040 buck regulator.

DC BIAS VOLTAGE (V)

Figure 107. Capacitance vs. Voltage Characteristic

Use the following equation to determine the worst-case capa-

citance accounting for capacitor variation over temperature,

component tolerance, and voltage.

C

_EFF= C_BIAS× (1 − TEMPCO) × (1 − TOL)

where:

C_BIASis the effective capacitance at the operating voltage.

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

A second method to estimate the power dissipation uses the

efficiency curves provided for the buck regulator, whereas the

power lost on a LDO is calculated using Equation 12. When the

buck efficiency is known, use Equation 2b to derive the total

power lost in the buck regulator and inductor. Use Equation 4

In this example, the worst-case temperature coefficient

(TEMPCO) over −40°C to +85°C is assumed to be 15% for an

Rev. 0 | Page 31 of 40

ADP5040

Data Sheet

to derive the power lost in the inductor, and then calculate the

power dissipation in the buck converter using Equation 3. Add

the power dissipated in the buck and in the LDOs to find the

total dissipated power.

The power switch conductive losses are due to the output current,

I

_OUT1, flowing through the PMOSFET and the NMOSFET power

switches that have internal resistance, R_DSON-Pand R_DSON-N. The

amount of conductive power loss is found by:

2

Note that the buck efficiency curves are typical values and may

not be provided for all possible combinations of V_IN, V_OUT, and

I_OUT. To account for these variations, it is necessary to include a

safety margin when calculating the power dissipated in the buck.

P

_COND= [R_DSON-P× D + R_DSON-N× (1 – D)] × I_OUT1

(9)

For the ADP5040, at 125°C junction temperature and V_IN1

=

3.6 V, R _DSON-Pis approximately 0.2 Ω, and R_DSON-Nis approximately

0.16 Ω. At V_IN1= 2.3 V, these values change to 0.31 Ω and 0.21 Ω,

respectively, and at V_IN1= 5.5 V, the values are 0.16 Ω and

0.14 Ω, respectively.

A third way to estimate the power dissipation is analytical and

involves modeling the losses in the buck circuit provided by

Equation 8 to Equation 11 and the losses in the LDOs provided

by Equation 12.

Switching losses are associated with the current drawn by the

driver to turn on and turn off the power devices at the switching

frequency. The amount of switching power loss is given by:

Buck Regulator Power Dissipation

_SW= (C_GATE-P+ C_GATE-N) × V_IN1²× f_SW

(10)

The power loss of the buck regulator is approximated by

P

_LOSS= P_DBUCK+ P_L

(3)

(4)

where:

C

_GATE-Pis the PMOSFET gate capacitance.

_GATE-Nis the NMOSFET gate capacitance.

where:

P

_DBUCKis the power dissipation on the ADP5040 buck regulator.

P_Lis the inductor power losses.

For the ADP5040, the total of (C_GATE-P+ C_GATE-N) is approximately

150 pF.

The inductor losses are external to the device and they do not

have any effect on the die temperature.

The transition losses occur because the PMOSFET cannot be

turned on or off instantaneously, and the SW node takes some

time to slew from near ground to near V_OUT1(and from V_OUT1to

ground). The amount of transition loss is calculated by:

The inductor losses are estimated (without core losses) by

P_L≅ I_OUT1(RMS)²× DCR_L

where:

P

_TRAN= V_IN1× I_OUT1× (t_RISE+ t_FALL) × f_SW

(11)

DCR_Lis the inductor series resistance.

where t_RISEand t_FALLare the rise time and the fall time of the

switching node, SW. For the ADP5040, the rise and fall times of

SW are in the order of 5 ns.

I

_OUT1(RMS)is the rms load current of the buck regulator.

If the preceding equations and parameters are used for

estimating the converter efficiency, note that the equations do

not describe all of the converter losses, and the parameter

values given are typical numbers. The converter performance

also depends on the choice of passive components and board

layout; therefore, a sufficient safety margin should be included

in the estimate.

I_OUT1(RMS)= I_OUT1× 1+r/12

(5)

(6)

where r is the normalized inductor ripple current.

R ≈ V_OUT1× (1 − D)/(I_OUT1× L × f_SW

where:

L is inductance.

_SWis switching frequency.

D is duty cycle.

D = V_OUT1/V_IN1

The ADP5040 buck regulator power dissipation, P_DBUCK

)

LDO Regulator Power Dissipation

F

The power loss of a LDO regulator is given by:

P

_DLDO= [(V_IN– V_OUT) × I_LOAD] + (V_IN× I_GND

)

(12)

(7)

where:

,

I

V

_LOADis the load current of the LDO regulator.

_INand V_OUTare input and output voltages of the LDO,

includes the power switch conductive losses, the switch losses,

and the transition losses of each channel. There are other

sources of loss, but these are generally less significant at high

output load currents, where the thermal limit of the application

is. Equation 8 shows the calculation made to estimate the power

dissipation in the buck regulator.

respectively.

_GNDis the ground current of the LDO regulator.

I

Power dissipation due to the ground current is small and it

can be ignored.

P

_DBUCK= P_COND+ P_SW+ P_TRAN

(8)

The total power dissipation in the ADP5040 simplifies to:

P_D= {[P_DBUCK+ P_DLDO1+ P_DLDO2]}

(13)

Rev. 0 | Page 32 of 40

Data Sheet

ADP5040

Junction Temperature

If the case temperature can be measured, the junction temperature

is calculated by

In cases where the board temperature, T_A, is known, the

thermal resistance parameter, θ_JA, can be used to estimate the

junction temperature rise. T_Jis calculated from T_Aand P_Dusing

the formula

T_J= T_C+ (P_D× θ_JC)

where:

T_Cis the case temperature.

(15)

T_J= T_A+ (P_D× θ_JA)

(14)

θ_JCis the junction-to-case thermal resistance provided in Table 6.

The typical θ_JAvalue for the 20-lead, 4 mm × 4 mm LFCSP is

38°C/W (see Table 6). A very important factor to consider is

that θ_JAis based on a 4-layer, 4 inch × 3 inch, 2.5 oz copper, as

per JEDEC standard, and real applications may use different

sizes and layers. To remove heat from the device, it is important

to maximize the use of copper. Copper exposed to air dissipates

heat better than copper used in the inner layers. The exposed

pad (EP) should be connected to the ground plane with several

vias as shown in Figure 109.

When designing an application for a particular ambient

temperature range, calculate the expected ADP5040 power

dissipation (P_D) due to the losses of all channels by using

Equation 8 to Equation 13. From this power calculation, the

junction temperature, T_J, can be estimated using Equation 14.

The reliable operation of the buck regulator and the LDO

regulator can be achieved only if the estimated die junction

temperature of the ADP5040 (Equation 14) is less than 125°C.

Reliability and mean time between failures (MTBF) is highly

affected by increasing the junction temperature. Additional

information about product reliability can be found in the

Analog Devices, Inc., Reliability Handbook, which is available

at http://www.analog.com/reliability_handbook.

APPLICATION DIAGRAM

R

FILT

VOUT1

30Ω AVIN

11

L1

6

1µH

SW

V

AT

OUT1

8

1.2A

R1

FB1

BUCK

12

C4

10µF

R2

VIN1

C1

V

= 2.3V

TO 5.5V

PGND

IN1

7

9

EN_BK

4.7µF

FPWM

MODE

ON

17

14

PWM/PSM

EN1

10

13

OFF

VOUT2

V

AT

OUT2

VIN2

= 1.7V

TO 5.5V

IN2

300mA

LDO1

(DIGITAL)

C5

2.2µF

C2

1µF

R3

R4

FB2

15

EN_LDO1

ON

EN2

EN3

16

4

OFF

EN_LDO2

VOUT3

FB3

V

AT

OUT3

2

1

300mA

C6

2.2µF

R7

R8

VIN3

V

= 1.7V

TO 5.5V

IN3

LDO2

(ANALOG)

3

C3

1µF

EP

AGND

Figure 108. Application Diagram

Rev. 0 | Page 33 of 40

ADP5040

Data Sheet

PCB LAYOUT GUIDELINES

Poor layout can affect ADP5040 performance, causing electro-

magnetic interference (EMI) and electromagnetic compatibility

(EMC) problems, ground bounce, and voltage losses. Poor

layout can also affect regulation and stability. A good layout is

implemented using the following guidelines:

•

Maximize the size of ground metal on the component side

to help with thermal dissipation.

Use a ground plane with several vias connecting to the

component side ground to further reduce noise interference

on sensitive circuit nodes.

•

Place the inductor, input capacitor, and output capacitor

close to the IC using short tracks. These components carry

high switching frequencies, and large tracks act as antennas.

Route the output voltage path away from the inductor and

SW node to minimize noise and magnetic interference.

SUGGESTED LAYOUT

See Figure 109 for an example layout.

•

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

mm

VOUT3

PPL

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

GPL

C3 – 1µF

10V/XR5

0402

C4– 2.2µF

6.3V/XR5

0402

GPL

R

30Ω

0402

FILT

PPL

NC

AVIN

NC

VIN

SW

GPL

C5 – 4.7µF

10V/XR5 0603

AGND

L1 – 1µH

0603

GPL

MODE

EN2

PGND

EN1

ADP5040

VIAS LEGEND:

PPL = POWER PLANE (+4V)

GPL = GROUND PLANE

C6 – 10µF

6.3V/XR5

0603

C2 – 1µF

10V/XR5

0402

C5 – 2.2µF

6.3V/XR5

0402

TOP LAYER

2ND LAYER

VOUT1

PPL

VOUT2

mm

Figure 109. Evaluation Board Layout

Rev. 0 | Page 34 of 40

Data Sheet

ADP5040

BILL OF MATERIALS

Table 13.

Reference

Value

Part Number

Vendor

Package

0603

0402

0603

0402

2.0 × 1.6 × 0.9 (mm)

2.5 × 2.0 × 1.2 (mm)

1.9 × 2.0 × 1.0 (mm)

20-Lead LFCSP

C1

C2, C3

C4

C5, C6

L1

4.7 µF, X5R, 6.3 V

1 µF, X5R, 6.3 V

10 µF, X5R, 6.3 V

2.2 µF, X5R, 6.3 V

1 µH, 85 mΩ, 1400 mA

1 µH, 85 mΩ, 1350 mA

1 µH, 89 mΩ, 1800 mA

3-regulator micro PMU

JMK107BJ475

Taiyo-Yuden

Murata

Toko

Coilcraft

Analog Devices

LMK105BJ105MV-F

JMK107BJ106MA-T

JMK105BJ225MV-F

LQM2MPN1R0NG0B

MDT2520-CN

XPL2010-1102ML

ADP5040

IC1

Rev. 0 | Page 35 of 40

ADP5040

Data Sheet

FACTORY PROGRAMMABLE OPTIONS

Table 14. Regulator Output Discharge Resistor Options

Selection

0

1

All discharge resistors disabled

All discharge resistors enabled

Table 15. Under Voltage Lockout options

Selection

Min

1.95

3.10

Typ

2.15

3.65

Max

2.275

3.90

Unit

V

0

1

Rev. 0 | Page 36 of 40

Data Sheet

ADP5040

OUTLINE DIMENSIONS

4.10

4.00 SQ

3.90

0.30

0.25

0.20

PIN 1

INDICATOR

PIN 1

INDICATOR

16

15

20

0.50

BSC

1

EXPOSED

PAD

2.65

2.50 SQ

2.35

5

11

6

10

0.50

0.40

0.30

0.25 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.

Figure 110. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm Body, Very Very Thin Quad

(CP-20-10)

Dimensions shown in millimeters

ORDERING GUIDE

Package

Option

Model¹

UVLO Active Pull-Down

2.15 V Enabled on all channels

Temperature Range

Package Description

ADP5040ACPZ-1-R7

ADP5040CP-1-EVALZ

T_J= −40°C to +125°C

20-Lead LFCSP_WQ

Evaluation Board

CP-20-10

¹Z = RoHS Compliant Part.

Rev. 0 | Page 37 of 40

ADP5040

NOTES

Data Sheet

Rev. 0 | Page 38 of 40

Data Sheet

NOTES

ADP5040

Rev. 0 | Page 39 of 40

ADP5040

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D096665-0-12/11(0)

Rev. 0 | Page 40 of 40

型号:	JMK105BJ225MV-F
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	0402
包装说明：	CHIP
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8532.24.00.20
风险等级：	0.96
Samacsys Confidence：	3
Samacsys Status：	Released
Samacsys PartID：	267614
Samacsys Pin Count：	2
Samacsys Part Category：	Capacitor
Samacsys Package Category：	Capacitor Chip Non-polarised
Samacsys Footprint Name：	MK105(0402)
Samacsys Released Date：	2016-02-02 16:41:10
Is Samacsys：	N
电容：	2.2 µF
电容器类型：	CERAMIC CAPACITOR
介电材料：	CERAMIC
高度：	0.5 mm
JESD-609代码：	e3
长度：	1 mm
安装特点：	SURFACE MOUNT
多层：	Yes
负容差：	20%
端子数量：	2
最高工作温度：	85 °C
最低工作温度：	-55 °C
封装形状：	RECTANGULAR PACKAGE
封装形式：	SMT
包装方法：	TAPE, PAPER
正容差：	20%
额定（直流）电压（URdc）：	6.3 V
尺寸代码：	0402
表面贴装：	YES
温度特性代码：	X5R
温度系数：	15% ppm/ °C
端子面层：	Tin (Sn) - with Nickel (Ni) barrier
端子形状：	WRAPAROUND
宽度：	0.5 mm
Base Number Matches：	1

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