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产品型号K4S641632H-TC75的概述

芯片K4S641632H-TC75概述及详细参数分析一、芯片概述 K4S641632H-TC75是一款来自三星电子（Samsung Electronics）的动态随机存取存储器（DRAM），主要用于各种电子设备的数据存储。随着计算技术的发展，现代设备需要更高速度和更大容量的内存，以满足日益增长的数据处理需求。作为一款高性能的存储芯片，K4S641632H-TC75具备快速访问时间和低功耗特性，适用于诸如个人计算机、手机、嵌入式系统等多种应用领域。二、详细参数 K4S641632H-TC75的基本技术规格如下： - 类型：动态随机存取存储器（DRAM） - 密度：64Mb（32Mx2） - 接口：同步动态随机存取存储器（SDRAM）接口 - 工作电压：2.5V ± 0.2V - 工作频率：最大可达133MHz（7.5ns） - 内存结构：内置8个行地址和8个列地址，分为8个字节的存...

产品型号K4S641632H-TC75的Datasheet PDF文件预览

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

64Mb H-die SDRAM Specification

54 TSOP-II with Pb-Free

(RoHS compliant)

Revision 1.3

August 2004

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

Revision History

Revision 1.0 (September, 2003)

• Finalized

Revision 1.1 (October, 2003)

Deleted speed -7C and AC parameter notes 5.

Revision 1.2 (May, 2004)

• Added Note 5. sentense of tRDL parameter

Revision 1.3 (August, 2004)

• Corrected typo.

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

4M x 4Bit x 4 / 2M x 8Bit x 4 / 1M x 16Bit x 4 Banks Synchronous DRAM

FEATURES

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page)

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system

clock

• Burst read single-bit write operation

• DQM (x4,x8) & L(U)DQM (x16) for masking

• Auto & self refresh

• 64ms refresh period (4K cycle)

• Pb-free Package

• RoHS compliant

GENERAL DESCRIPTION

The K4S640432H / K4S640832H / K4S641632H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x

4,194,304 words by 4 bits, / 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG′s high perfor-

mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible

on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to

be useful for a variety of high bandwidth, high performance memory system applications.

Ordering Information

Part No.

Orgainization

16Mb x 4

Max Freq.

Interface

Package

K4S640432H-UC(L)75

K4S640832H-UC(L)75

K4S641632H-UC(L)60

K4S641632H-UC(L)70

K4S641632H-UC(L)75

133MHz(CL=3)

166MHz(CL=3)

143MHz(CL=3)

133MHz(CL=3)

8Mb x 8

LVTTL

54pin TSOP(II)

4Mb x 16

Organization

Row Address

Column Address

A0-A9

16Mx4

8Mx8

A0~A11

A0-A8

4Mx16

A0-A7

Row & Column address configuration

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

Package Physical Dimension

0~8°C

0.25

0.010

TYP

#54

#28

#27

+0.075

-0.035

+0.003

-0.001

0.125

0.005

22.62

MAX

0.891

22.22

± 0.10

0.21 ± 0.05

± 0.10

1.00

0.039

1.20

0.047

MAX

± 0.004

± 0.002

0.875

± 0.004

0.008

0.10

MAX

0.004

+0.10

0.05

0.002

MIN

0.30

0.80

0.0315

0.71

-0.05

(

)

+0.004

0.028

0.012

-0.002

54Pin TSOP(II) Package Dimension

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

FUNCTIONAL BLOCK DIAGRAM

LWE

Data Input Register

LDQM

Bank Select

4M x 4 / 2M x 8 / 1M x 16

DQi

CLK

ADD

Column Decoder

Latency & Burst Length

LCKE

Programming Register

LWCBR

LRAS

LCBR

LWE

LCAS

LDQM

Timing Register

CLK

CKE

RAS

CAS

L(U)DQM

Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

PIN CONFIGURATION (Top view)

x16

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

VDD

LDQM

CAS

RAS

BA0

BA1

VDD

DQ0

VDDQ

N.C

DQ1

VSSQ

N.C

DQ2

VDDQ

N.C

DQ3

VSSQ

N.C

VDD

N.C

CAS

RAS

BA0

BA1

VDD

N.C

VDDQ

N.C

DQ0

VSSQ

N.C

VDDQ

N.C

DQ1

VSSQ

N.C

VDD

N.C

VSS

N.C

VSSQ

N.C

DQ3

VDDQ

N.C

VSSQ

N.C

DQ2

VDDQ

N.C

VSS

DQ7

VSSQ

N.C

DQ6

VDDQ

N.C

DQ5

VSSQ

N.C

DQ4

VDDQ

N.C

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

VSS

N.C/RFU N.C/RFU N.C/RFU

DQM

CLK

CKE

N.C

A11

DQM

CLK

CKE

N.C

A11

UDQM

CLK

CKE

N.C

A11

CAS

RAS

BA0

BA1

A10/AP A10/AP A10/AP

VDD

54Pin TSOP (II)

(400mil x 875mil)

(0.8 mm Pin pitch)

VSS

PIN FUNCTION DESCRIPTION

Name

System clock

Input Function

Active on the positive going edge to sample all inputs.

CLK

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Chip select

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

CKE

Clock enable

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA11,

A0 ~ A11

Address

Column address : (x4 : CA0 ~ CA9, x8 : CA0 ~ CA8 , x16 : CA0 ~ CA7)

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

BA0 ~ BA1

RAS

Bank select address

Row address strobe

Column address strobe

Write enable

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

CAS

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when DQM active.

DQM

Data input/output mask

DQ0 ~ X15

VDD/VSS

Data input/output

Data inputs/outputs are multiplexed on the same pins.

Power and ground for the input buffers and the core logic.

Power supply/ground

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

VDDQ/VSSQ

N.C/RFU

Data output power/ground

No connection

/reserved for future use

This pin is recommended to be left No Connection on the device.

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to VSS

Voltage on VDD supply relative to VSS

Storage temperature

Symbol

Value

-1.0 ~ 4.6

-55 ~ +150

Unit

VIN, VOUT

VDD, VDDQ

TSTG

°C

Power dissipation

Short circuit current

IOS

Note :

Permanent device damage may occur if "ASOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)

Parameter

Supply voltage

Symbol

VDD, VDDQ

VIH

Min

3.0

2.0

-0.3

2.4

Typ

3.3

3.0

Max

3.6

Unit

Note

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

VDD+0.3

0.8

VIL

VOH

IOH = -2mA

IOL = 2mA

VOL

0.4

ILI

-10

Notes :

1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.

3. Any input 0V ≤ VIN ≤ VDDQ.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)

Symbol

CCLK

CIN

Min

2.5

4.0

Max

4.0

5.0

6.5

Unit

Note

Clock

RAS, CAS, WE, CS, CKE, DQM

Address

CADD

COUT

DQ0 ~ DQ3

Notes :

1. -75 only specify a maximum value of 3.5pF

2. -75 only specify a maximum value of 3.8pF

3. -75 only specify a maximum value of 6.0pF

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C for x4, x8)

Version

Parameter

Symbol

Test Condition

Unit

Note

Burst length = 1

tRC ≥ tRC(min)

IO = 0 mA

Operating current

(One bank active)

ICC1

ICC2P CKE ≤ VIL(max), tCC = 10ns

Precharge standby current in

power-down mode

ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

ICC2N

Input signals are changed one time during 20ns

Precharge standby current in

non power-down mode

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

ICC2NS

Input signals are stable

ICC3P CKE ≤ VIL(max), tCC = 10ns

Active standby current in

power-down mode

ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

ICC3N

Active standby current in

non power-down mode

(One bank active)

Input signals are changed one time during 20ns

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable

ICC3NS

IO = 0 mA

Operating current

(Burst mode)

Page burst

4Banks Activated

ICC4

115

tCCD = 2CLKs

Refresh current

ICC5

ICC6

tRC ≥ tRC(min)

135

Self refresh current

CKE ≤ 0.2V

400

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

3. K4S6404(08)32H-TC**

4. K4S6404(08)32H-TL**

5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C for x16 only)

Version

Parameter

Symbol

Test Condition

Unit

Note

Burst length = 1

tRC ≥ tRC(min)

IO = 0 mA

Operating current

(One bank active)

ICC1

140

115

110

ICC2P CKE ≤ VIL(max), tCC = 10ns

Precharge standby current in

power-down mode

ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

ICC2N

Input signals are changed one time during 20ns

Precharge standby current in

non power-down mode

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

ICC2NS

Input signals are stable

ICC3P CKE ≤ VIL(max), tCC = 10ns

Active standby current in

power-down mode

ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

ICC3N

Active standby current in

non power-down mode

(One bank active)

Input signals are changed one time during 20ns

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable

ICC3NS

IO = 0 mA

Operating current

(Burst mode)

Page burst

4Banks Activated

tCCD = 2CLKs

ICC4

160

140

135

Refresh current

ICC5

ICC6

tRC ≥ tRC(min)

140

Self refresh current

CKE ≤ 0.2V

400

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

3. K4S641632H-TC**

4. K4S641632H-TL**

5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)

Parameter

AC input levels (Vih/Vil)

Value

2.4/0.4

1.4

Unit

Input timing measurement reference level

Input rise and fall time

tr/tf = 1/1

1.4

Output timing measurement reference level

Output load condition

See Fig. 2

3.3V

Vtt = 1.4V

1200Ω

50Ω

VOH (DC) = 2.4V, IOH = -2mA

VOL (DC) = 0.4V, IOL = 2mA

Output

Z0 = 50Ω

30pF

870Ω

(Fig. 1) DC output load circuit

(Fig. 2) AC output load circuit

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

Parameter

Symbol

Unit

Note

Row active to row active delay

RAS to CAS delay

tRRD(min)

tRCD(min)

tRP(min)

Row precharge time

tRAS(min)

tRAS(max)

tRC(min)

Row active time

100

Row cycle time

2,5

Last data in to row precharge

Last data in to Active delay

Last data in to new col. address delay

Last data in to burst stop

tRDL(min)

tDAL(min)

tCDL(min)

tBDL(min)

tCCD(min)

CLK

2 CLK + tRP

CLK

Col. address to col. address delay

CAS latency = 3

CAS latency = 2

Number of valid output data

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.

SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

Parameter

Symbol

tCC

Unit

Note

Min

Max

Min

Max

Min

7.5

Max

CAS latency=3

CLK cycle time

1000

CAS latency=2

CAS latency=3

CAS latency=2

CAS latency=3

CAS latency=2

5.4

CLK to valid

output delay

tSAC

1,2

2.5

Output data

hold time

tOH

CLK high pulse width

CLK low pulse width

Input setup time

tCH

tCL

2.5

1.5

2.5

1.5

0.8

tSS

tSH

tSLZ

Input hold time

CLK to output in Low-Z

CAS latency=3

CAS latency=2

5.4

CLK to output

in Hi-Z

tSHZ

Notes :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

DQ BUFFER OUTPUT DRIVE CHARACTERISTICS

Parameter

Symbol

Condition

Min

Typ

Max

Unit

Notes

Measure in linear

region : 1.2V ~ 1.8V

Output rise time

trh

1.37

4.37

3.8

5.6

Volts/ns

Measure in linear

region : 1.2V ~ 1.8V

Output fall time

Output rise time

Output fall time

tfh

trh

tfh

1.30

2.8

Volts/ns

Measure in linear

region : 1.2V ~ 1.8V

3.9

2.9

1,2

Measure in linear

region : 1.2V ~ 1.8V

2.0

5.0

Notes :

1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.

2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.

3. Measured into 50pF only, use these values to characterize to.

4. All measurements done with respect to VSS.

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

133MHz Pull-up

1.5

IBIS SPECIFICATION

0.5

2.5

3.5

IOH Characteristics (Pull-up)

-100

-200

-300

-400

-500

-600

133MHz

Min

I (mA)

-0.35

-3.75

-6.65

-13.75

-17.75

-20.55

-23.55

-26.2

-36.25

-46.5

133MHz

Max

I (mA)

Voltage

(V)

3.45

3.30

3.00

2.70

2.50

1.95

1.80

1.65

1.50

1.40

1.00

0.20

-1.68

-19.11

-51.87

-90.44

-107.31

-137.9

-158.34

-173.6

-188.79

-199.01

-241.15

-351.68

Voltage

IOH Min (133MHz)

IOH Max (133MHz)

133MHz Pull-down

IOL Characteristics (Pull-down)

250

200

150

100

133MHz

Max

I (mA)

155.82

153.72

148.40

146.02

141.75

136.08

131.39

105.84

93.66

75.25

49.14

Voltage

Min

(V)

I (mA)

43.92

3.45

3.30

3.00

1.95

1.80

1.65

1.50

1.40

1.00

0.85

0.65

0.40

43.36

41.20

40.56

39.60

38.40

37.28

30.08

26.64

21.52

14.16

0.5

1.5

2.5

3.5

Voltage

IOL Min (133MHz)

IOL Max (133MHz)

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

Minimum VDD clamp current

(Referenced to VDD)

VDD Clamp @ CLK, CKE, CS, DQM & DQ

VDD (V)

0.0

0.2

0.4

0.6

0.7

0.8

0.9

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

I (mA)

0.0

0.23

1.34

3.02

5.06

7.35

9.83

12.48

15.30

18.31

Voltage

I (mA)

Minimum VSS clamp current

-2 -1

VSS Clamp @ CLK, CKE, CS, DQM & DQ

-3

VSS (V)

-2.6

-2.4

-2.2

-2.0

-1.8

-1.6

-1.4

-1.2

-1.0

-0.9

-0.8

-0.7

-0.6

-0.4

-0.2

0.0

I (mA)

-57.23

-45.77

-38.26

-31.22

-24.58

-18.37

-12.56

-7.57

-3.37

-1.75

-0.58

-0.05

0.0

-10

-20

-30

-40

-50

-60

0.0

Voltage

I (mA)

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

SIMPLIFIED TRUTH TABLE

(V=Valid, X=Don′t care, H=Logic high, L=Logic low)

A11,

A9 ~ A0

Command

Mode register set

CKEn-1 CKEn

RAS

CAS

DQM BA0,1

A10/AP

Note

Refresh

OP code

1,2

Auto refresh

Entry

Exit

Self

refresh

Bank active & row addr.

Row address

Read &

column address

Auto precharge disable

Auto precharge enable

Auto precharge disable

Auto precharge enable

4,5

Column

address

Write &

column address

Column

address

4,5

Burst stop

Precharge

Bank selection

All banks

Entry

Exit

Clock suspend or

active power down

Entry

Precharge power down mode

Exit

DQM

No operation command

Notes :

1. OP Code : Operand code

A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.

If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Rev. 1.3 August 2004

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K4S641632H-TC75产品参数

型号:	K4S641632H-TC75
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	SAMSUNG SEMICONDUCTOR INC
零件包装代码：	TSOP2
包装说明：	TSOP2, TSOP54,.46,32
针数：	54
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.32.00.02
风险等级：	5.25
Is Samacsys：	N
访问模式：	FOUR BANK PAGE BURST
最长访问时间：	5.4 ns
其他特性：	AUTO/SELF REFRESH
最大时钟频率 (fCLK)：	133 MHz
I/O 类型：	COMMON
交错的突发长度：	1,2,4,8
JESD-30 代码：	R-PDSO-G54
长度：	22.22 mm
内存密度：	67108864 bit
内存集成电路类型：	SYNCHRONOUS DRAM
内存宽度：	16
湿度敏感等级：	3
功能数量：	1
端口数量：	1
端子数量：	54
字数：	4194304 words
字数代码：	4000000
工作模式：	SYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	4MX16
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP2
封装等效代码：	TSOP54,.46,32
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V
认证状态：	Not Qualified
刷新周期：	4096
座面最大高度：	1.2 mm
自我刷新：	YES
连续突发长度：	1,2,4,8,FP
最大待机电流：	0.001 A
子类别：	DRAMs
最大压摆率：	0.135 mA
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子形式：	GULL WING
端子节距：	0.8 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10.16 mm
Base Number Matches：	1

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