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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

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  • 深圳市美思瑞电子科技有限公司

     该会员已使用本站12年以上
  • K4T1G084QE-HCE6 现货库存
  • 数量9217 
  • 厂家SAMSUNG/三星 
  • 封装BGA 
  • 批号22+ 
  • 市场最低价!原厂原装假一罚十
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • K4T1G084QE-HCE6 现货库存
  • 数量7960 
  • 厂家SAMSUNG 
  • 封装 
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  • 假一罚万!专业内存、储存、闪存
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • K4T1G084QE-HCE6 现货库存
  • 数量7960 
  • 厂家SAMSUNG 
  • 封装 
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  • 假一罚万!专业内存、储存、闪存
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  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • K4T1G084QE-HCE6 现货库存
  • 数量3851 
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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
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  • 数量69850 
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  • 深圳市亿智腾科技有限公司

     该会员已使用本站8年以上
  • K4T1G084QE-HCE6 现货库存
  • 数量5000 
  • 厂家SAMSUNG 
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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
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  • 数量6980 
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  • 深圳市正纳电子有限公司

     该会员已使用本站15年以上
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  • 数量26700 
  • 厂家SAMSUNG(三星) 
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  • 深圳市硅诺电子科技有限公司

     该会员已使用本站8年以上
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  • 数量40086 
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  • 集好芯城

     该会员已使用本站13年以上
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  • 数量17435 
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  • 北京元坤伟业科技有限公司

     该会员已使用本站17年以上
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  • 数量5000 
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  • 百分百原装正品,现货库存
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  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
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  • 数量30000 
  • 厂家SAMSUNG 
  • 封装BGA 
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  • 深圳市华芯盛世科技有限公司

     该会员已使用本站13年以上
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  • 数量865000 
  • 厂家SAMSUNG/三星 
  • 封装19 
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
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  • 数量784 
  • 厂家SAMSUNG/三星 
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  • 深圳市美思瑞电子科技有限公司

     该会员已使用本站12年以上
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  • 数量12245 
  • 厂家SAMSUNG/三星 
  • 封装BGA 
  • 批号22+ 
  • 现货,原厂原装假一罚十!
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
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  • 数量13050 
  • 厂家SAMSUNG 
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  • 绝对原装正品现货/优势渠道商、原盘原包原盒
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  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站6年以上
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  • 数量6500 
  • 厂家SEC 
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  • 批号24+ 
  • 全新原装★真实库存★含13点增值税票!
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
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  • 数量392 
  • 厂家SEC 
  • 封装BGA 
  • 批号24+ 
  • 假一罚万,全新原装库存现货,可长期订货
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  • 首天国际(深圳)科技有限公司

     该会员已使用本站16年以上
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  • 数量128000 
  • 厂家SAMSUNG 
  • 封装BGA 
  • 批号2024+ 
  • 百分百原装正品,现货库存
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  • 深圳市意好科技有限公司

     该会员已使用本站15年以上
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  • 数量6730 
  • 厂家SAMSUNG 
  • 封装原厂 
  • 批号24+ 
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
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  • 数量12500 
  • 厂家SAMSUNG 
  • 封装BGA 
  • 批号2023+ 
  • 绝对原装全新正品现货/优势渠道商、原盘原包原盒
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  • 深圳市能元时代电子有限公司

     该会员已使用本站10年以上
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  • 数量23000 
  • 厂家SAMSUNG 
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  • 原装现货假一赔十,可含长期供货!
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  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
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  • 数量85000 
  • 厂家SAMSUNG/三星 
  • 封装19 
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  • 真实库存全新原装正品!代理此型号
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
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  • 数量15372 
  • 厂家Samsung 
  • 封装FBGA 
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  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
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  • 数量5503 
  • 厂家Samsung 
  • 封装BGA 
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  • 深圳市卓越微芯电子有限公司

     该会员已使用本站12年以上
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  • 数量5500 
  • 厂家Samsung 
  • 封装FBGA 
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  • 百分百原装正品 真实公司现货库存 本公司只做原装 可开13%增值税发票,支持样品,欢迎来电咨询!
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  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
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  • 数量3615 
  • 厂家SAMSUNG 
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  • 深圳市宗天技术开发有限公司

     该会员已使用本站10年以上
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  • 厂家SAMSUNG/三星 
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  • 深圳市赛矽电子有限公司

     该会员已使用本站13年以上
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  • 数量7840 
  • 厂家Samsung 
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  • 深圳市励创源科技有限公司

     该会员已使用本站2年以上
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  • 长荣电子

     该会员已使用本站14年以上
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  • 数量283 
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  • 深圳市西昂特科技有限公司

     该会员已使用本站13年以上
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  • 数量1000 
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  • 深圳市亿智腾科技有限公司

     该会员已使用本站8年以上
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  • 数量16680 
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  • 深圳市特拉特科技有限公司

     该会员已使用本站2年以上
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  • 数量9000 
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  • 深圳市隆鑫创展电子有限公司

     该会员已使用本站15年以上
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  • 深圳市全源通电子有限公司

     该会员已使用本站16年以上
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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
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  • 数量6980 
  • 厂家SAMSUNG 
  • 封装BGA 
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  • 深圳市凯信扬科技有限公司

     该会员已使用本站7年以上
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产品型号K4T1G084QE-HCE6的概述

K4T1G084QE-HCE6 芯片概述 K4T1G084QE-HCE6 是一款由三星电子(Samsung Electronics)制造的高性能DDR3 SDRAM(动态随机存储器)芯片。该芯片专为满足现代计算需求而设计,具备高带宽和低功耗的特点,广泛应用于各种电子设备中,如笔记本电脑、台式计算机、服务器、嵌入式系统等。它利用DDR(双倍数据速率)技术,通过在时钟信号的上升沿和下降沿传输数据,显著提升数据传输速率。 详细参数 K4T1G084QE-HCE6 具有以下重要参数: - 容量:1GB(Gigabyte) - 模块类型:DDR3 SDRAM - 数据总线宽度:X8、X16 选项 - 时钟频率:可以支持多种频率,常见于 1066 MT/s、1333 MT/s 和 1600 MT/s - 工作电压:1.5V - 封装类型:FBGA (Fine Ball Grid Array) - ...

产品型号K4T1G084QE-HCE6的Datasheet PDF文件预览

K4T1G044QE  
K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
1Gb E-die DDR2 SDRAM Specification  
60FBGA & 84FBGA with Lead-Free & Halogen-Free  
(RoHS compliant)  
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,  
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE  
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-  
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-  
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT  
GUARANTEE OR WARRANTY OF ANY KIND.  
1. For updates or additional information about Samsung products, contact your nearest Samsung office.  
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar  
applications where Product failure could result in loss of life or personal or physical harm, or any military or  
defense application, or any governmental procurement to which special terms or provisions may apply.  
* Samsung Electronics reserves the right to change products or specification without notice.  
1 of 45  
Rev. 1.1 December 2008  
K4T1G044QE  
K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
Table of Contents  
1.0 Ordering Information ................................................................................................................... 4  
2.0 Key Features ................................................................................................................................ 4  
3.0 Package Pinout/Mechanical Dimension & Addressing ............................................................ 5  
3.1 x4 package pinout (Top View) : 60ball FBGA Package ....................................................................... 5  
3.2 x8 package pinout (Top View) : 60ball FBGA Package........................................................................ 6  
3.3 x16 package pinout (Top View) : 84ball FBGA Package ..................................................................... 7  
3.4 FBGA Package Dimension (x4/x8) .................................................................................................. 8  
3.5 FBGA Package Dimension (x16) ..................................................................................................... 9  
4.0 Input/Output Functional Description ....................................................................................... 10  
5.0 DDR2 SDRAM Addressing ........................................................................................................ 11  
6.0 Absolute Maximum DC Ratings ................................................................................................ 12  
7.0 AC & DC Operating Conditions ................................................................................................ 12  
7.1 Recommended DC Operating Conditions (SSTL - 1.8) ..................................................................... 12  
7.2 Operating Temperature Condition ................................................................................................ 13  
7.3 Input DC Logic Level ................................................................................................................... 13  
7.4 Input AC Logic Level ................................................................................................................... 13  
7.5 AC Input Test Conditions ............................................................................................................ 13  
7.6 Differential input AC logic Level ................................................................................................... 14  
7.7 Differential AC output parameters ................................................................................................ 14  
8.0 ODT DC electrical characteristics ............................................................................................ 14  
9.0 OCD default characteristics ...................................................................................................... 15  
10.0 IDD Specification Parameters and Test Conditions ............................................................. 16  
11.0 DDR2 SDRAM IDD Spec Table ................................................................................................ 18  
12.0 Input/Output capacitance ........................................................................................................ 19  
13.0 Electrical Characteristics & AC Timing for DDR2-800/667 ................................................... 19  
13.1 Refresh Parameters by Device Density ........................................................................................ 19  
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ............................................. 19  
13.3 Timing Parameters by Speed Grade ............................................................................................ 20  
14.0 General notes, which may apply for all AC parameters....................................................... 22  
15.0 Specific Notes for dedicated AC parameters ........................................................................ 24  
2 of 45  
Rev. 1.1 December 2008  
K4T1G044QE  
K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
Revision History  
Revision  
1.0  
Month  
August  
Year  
2008  
2008  
2008  
History  
- Initial Release  
- Typo Correction  
1.01  
September  
December  
1.1  
- Updated AC/DC operating condition with the JEDEC update(JESD79-2E)  
3 of 45  
Rev. 1.1 December 2008  
K4T1G044QE  
K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
1.0 Ordering Information  
Org.  
DDR2-800 5-5-5  
DDR2-800 6-6-6  
DDR2-667 5-5-5  
Package  
256Mx4  
128Mx8  
64Mx16  
K4T1G044QE-HC(L)E7  
K4T1G084QE-HC(L)E7  
K4T1G164QE-HC(L)E7  
K4T1G044QE-HC(L)F7  
K4T1G084QE-HC(L)F7  
K4T1G164QE-HC(L)F7  
K4T1G044QE-HC(L)E6  
K4T1G084QE-HC(L)E6  
K4T1G164QE-HC(L)E6  
60 FBGA  
60 FBGA  
84 FBGA  
Note :  
1. Speed bin is in order of CL-tRCD-tRP.  
2. RoHS Compliant.  
3. “H” of Part number(12th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products.  
4. “C” of Part number(13th digit) stands normal, and “L” stands for Low power products.  
2.0 Key Features  
Speed  
CAS Latency  
tRCD(min)  
tRP(min)  
DDR2-800 5-5-5  
DDR2-800 6-6-6  
DDR2-667 5-5-5  
Units  
tCK  
ns  
5
6
5
12.5  
12.5  
57.5  
15  
15  
60  
15  
15  
60  
ns  
tRC(min)  
ns  
• JEDEC standard VDD = 1.8V ± 0.1V Power Supply  
• VDDQ = 1.8V ± 0.1V  
The 1Gb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x  
8banks, 16Mbit x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks  
device. This synchronous device achieves high speed double-  
data-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for  
general applications.  
• 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/  
pin  
The chip is designed to comply with the following key DDR2  
SDRAM features such as posted CAS with additive latency, write  
latency = read latency - 1, Off-Chip Driver(OCD) impedance  
adjustment and On Die Termination.  
• 8 Banks  
• Posted CAS  
• Programmable CAS Latency: 3, 4, 5, 6  
• Programmable Additive Latenc y: 0, 1, 2, 3, 4, 5  
• Write Latency(WL) = Read Latency(RL) -1  
• Burst Length: 4 , 8(Interleave/nibble sequential)  
• Programmable Sequential / Interleave Burst Mode  
• Bi-directional Differential Data-Strobe (Single-ended data-  
strobe is an optional feature)  
• Off-Chip Driver(OCD) Impedance Adjustment  
• On Die Termination  
All of the control and address inputs are synchronized with a pair  
of externally supplied differential clocks. Inputs are latched at the  
crosspoint of differential clocks (CK rising and CK falling). All I/Os  
are synchronized with a pair of bidirectional strobes (DQS and  
DQS) in a source synchronous fashion. The address bus is used  
to convey row, column, and bank address information in a RAS/  
CAS multiplexing style. For example, 1Gb(x8) device receive 14/  
10/3 addressing.  
The 1Gb DDR2 device operates with a single 1.8V ± 0.1V power  
supply and 1.8V ± 0.1V VDDQ  
.
• Special Function Support  
- 50ohm ODT  
The 1Gb DDR2 device is available in 60ball FBGA(x4/x8) and in  
84ball FBGA(x16).  
- High Temperature Self-Refresh rate enable  
• Average Refresh Period 7.8us at lower than TCASE 85°C,  
3.9us at 85°C < TCASE < 95 °C  
Note : The functionality described and the timing specifications included in  
this data sheet are for the DLL Enabled mode of operation.  
• All of products are Lead-Free, Halogen-Free, and RoHS com-  
pliant  
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device  
Operation & Timing Diagram”.  
4 of 45  
Rev. 1.1 December 2008  
K4T1G044QE  
K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
3.0 Package Pinout/Mechanical Dimension & Addressing  
3.1 x4 package pinout (Top View) : 60ball FBGA Package  
1
2
3
4
5
6
7
8
9
VDD  
VSS  
VSSQ  
VDDQ  
A
B
C
D
NC  
VSSQ  
DQS  
VSSQ  
NC  
VDDQ  
DM  
VDDQ  
DQS  
VDDQ  
NC  
VDDQ  
DQ1  
VSSQ  
VREF  
DQ0  
VSSQ  
NC  
VDDL  
DQ3  
VSS  
DQ2  
VSSDL  
NC  
VDD  
E
F
G
CK  
CK  
CS  
A0  
CKE  
BA0  
A10/AP  
WE  
BA1  
A1  
RAS  
CAS  
A2  
ODT0  
BA2  
VSS  
VDD  
VSS  
H
J
K
L
A3  
A7  
A5  
A9  
NC  
A6  
A11  
NC  
A4  
A8  
VDD  
A12  
A13  
Note : VDDL and VSSDL are power and ground for the DLL. It is recommended that they be isolated on the device from VDD,VD-  
DQ, VSS, and VSSQ  
.
1
2
3
4
5
6
7
8
9
Ball Locations (x4)  
A
B
C
D
E
F
G
H
J
Populated ball  
Ball not populated  
Top view  
(See the balls through package)  
K
L
5 of 45  
Rev. 1.1 December 2008  
K4T1G044QE  
K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
3.2 x8 package pinout (Top View) : 60ball FBGA Package  
1
2
3
4
5
6
7
8
9
VDD  
VSS  
VSSQ  
VDDQ  
A
B
C
D
NU/RDQS  
VSSQ  
DQS  
VSSQ  
DQ6  
VDDQ  
DM/RDQS  
VDDQ  
DQS  
VDDQ  
DQ7  
VDDQ  
DQ1  
VSSQ  
VREF  
DQ0  
VSSQ  
DQ4  
VDDL  
DQ3  
VSS  
DQ2  
VSSDL  
DQ5  
VDD  
E
F
G
CK  
CK  
CS  
A0  
CKE  
BA0  
A10/AP  
WE  
BA1  
A1  
RAS  
CAS  
A2  
ODT0  
BA2  
VSS  
VDD  
VSS  
H
J
K
L
A3  
A7  
A5  
A9  
NC  
A6  
A11  
NC  
A4  
A8  
VDD  
A12  
A13  
Note :  
1. Pins B3 and A2 have identical capacitances as pins B7 and A8.  
2. For a Read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS & DQS and  
input data masking function is disabled.  
3. The function of DM or RDQS/RDQS is enabled by EMRS command.  
4. VDDL and VSSDL are power and ground for the DLL. It is recommended that they be isolated on the device from VDD,VDDQ  
,
V
SS, and VSSQ  
.
1
2
3
4
5
6
7
8
9
Ball Locations (x8)  
A
B
C
D
E
F
G
H
J
Populated ball  
Ball not populated  
Top view  
(See the balls through package)  
K
L
6 of 45  
Rev. 1.1 December 2008  
K4T1G044QE  
K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
3.3 x16 package pinout (Top View) : 84ball FBGA Package  
1
2
3
4
5
6
7
8
9
VDD  
VSS  
VSSQ  
VDDQ  
A
B
C
D
E
F
NC  
VSSQ  
UDQS  
VSSQ  
DQ14  
VDDQ  
UDM  
VDDQ  
UDQS  
VDDQ  
DQ15  
VDDQ  
DQ9  
VSSQ  
DQ8  
VSSQ  
DQ12  
VDD  
DQ11  
VSS  
DQ10  
VSSQ  
DQ13  
VDDQ  
NC  
VSSQ  
LDQS  
VSSQ  
DQ6  
VDDQ  
LDM  
VDDQ  
LDQS  
VDDQ  
DQ7  
VDDQ  
G
H
DQ1  
VSSQ  
VREF  
DQ0  
VSSQ  
DQ4  
VDDL  
DQ3  
VSS  
DQ2  
VSSDL  
DQ5  
VDD  
J
K
L
CK  
CK  
CS  
A0  
CKE  
BA0  
A10/AP  
WE  
BA1  
A1  
RAS  
CAS  
A2  
ODT  
BA2  
VSS  
VDD  
VSS  
M
N
P
R
A3  
A7  
A5  
A9  
NC  
A6  
A11  
NC  
A4  
A8  
NC  
VDD  
A12  
Note : VDDL and VSSDL are power and ground for the DLL. It is recommended that they be isolated on the device from VDD  
DDQ, VSS, and VSSQ  
,
V
.
1
2
3
4
5
6
7
8
9
Ball Locations (x16)  
A
B
C
D
E
F
Populated ball  
Ball not populated  
G
H
J
K
L
Top view  
(See the balls through package)  
M
N
P
R
7 of 45  
Rev. 1.1 December 2008  
K4T1G044QE  
K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
3.4 FBGA Package Dimension (x4/x8)  
7.50 ± 0.10  
A
0.80 x 8 = 6. 40  
# A1 INDEX MARK  
3.20  
(Datum A)  
(Datum B)  
0.80  
7
1.60  
B
9
8
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
(0.95)  
MOLDING AREA  
(1.90)  
60-0.45 Solder ball  
(Post reflow 0.50 ± 0.05)  
0.2 M  
A B  
7.50 ± 0.10  
#A1  
0.35±0.05  
1.10±0.10  
8 of 45  
Rev. 1.1 December 2008  
K4T1G044QE  
K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
3.5 FBGA Package Dimension (x16)  
7.50 ± 0.10  
A
0.80 x 8 = 6. 40  
# A1 INDEX MARK  
3.20  
0.80  
7
1.60  
B
9
8
6
5
4
3
2
1
(Datum A)  
(Datum B)  
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
(0.95)  
MOLDING AREA  
(1.90)  
84-0.45 Solder ball  
(Post reflow 0.50 ± 0.05)  
0.2 M  
A B  
7.50 ± 0.10  
#A1  
0.35±0.05  
1.10±0.10  
9 of 45  
Rev. 1.1 December 2008  
K4T1G044QE  
K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
4.0 Input/Output Functional Description  
Symbol  
Type  
Function  
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the  
positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both  
directions of crossing).  
CK, CK  
Input  
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and out-  
put drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active  
Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry.  
CKE is asynchronous for self refresh exit. After VREF has become stable during the power on and initialization  
CKE  
CS  
Input  
Input  
sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF  
must be maintained to this input. CKE must be maintained high throughout read and write accesses. Input buffers,  
excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during  
self refresh.  
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on sys-  
tems with multiple Ranks. CS is considered part of the command code.  
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When  
enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM signal for x4/x8 configurations. For x16  
configuration ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal. The ODT pin will be  
ignored if the Extended Mode Register (EMRS(1)) is programmed to disable ODT.  
ODT  
RAS, CAS, WE  
DM  
Input  
Input  
Input  
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.  
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coinci-  
dent with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only,  
the DM loading matches the DQ and DQS loading. For x8 device, the function of DM or RDQS/RDQS is enabled by  
EMRS command.  
Bank Address Inputs: BA0, BA1 and BA2 define to which bank an Active, Read, Write or Precharge command is  
being applied. Bank address also determines if the mode register or extended mode register is to be accessed during  
a MRS or EMRS cycle.  
BA0 - BA2  
Input  
Input  
Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit for  
Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a  
Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If  
only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code dur-  
ing Mode Register Set commands.  
A0 - A13  
DQ  
Input/Out-  
put  
Data Input/ Output: Bi-directional data bus.  
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. For the  
x16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. For the x8, an RDQS  
option using DM pin can be enabled via the EMRS(1) to simplify read timing. The data strobes DQS, LDQS, UDQS,  
and RDQS may be used in single ended mode or paired with optional complementary signals DQS, LDQS, UDQS, and  
RDQS to provide differential pair signaling to the system during both reads and writes. An EMRS(1) control bit enables  
or disables all complementary data strobe signals.  
DQS, (DQS)  
In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1)  
x4 DQS/DQS  
(LDQS), (LDQS) Input/Out-  
(UDQS), (UDQS)  
(RDQS), (RDQS)  
put  
x8 DQS/DQS  
if EMRS(1)[A11] = 0  
x8 DQS/DQS, RDQS/RDQS,  
if EMRS(1)[A11] = 1  
x16 LDQS/LDQS and UDQS/UDQS  
"single-ended DQS signals" refers to any of the following with A10 = 1 of EMRS(1)  
x4 DQS  
x8 DQS if EMRS(1)[A11] = 0  
x8 DQS, RDQS, if EMRS(1)[A11] = 1  
x16 LDQS and UDQS  
NC  
No Connect: No internal electrical connection is present.  
V
DD / VDDQ  
Supply Power Supply: 1.8V +/- 0.1V, DQ Power Supply: 1.8V +/- 0.1V  
Supply Ground, DQ Ground  
VSS / VSSQ  
VDDL  
Supply DLL Power Supply: 1.8V +/- 0.1V  
Supply DLL Ground  
VSSDL  
VREF  
Supply Reference voltage  
10 of 45  
Rev. 1.1 December 2008  
K4T1G044QE  
K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
5.0 DDR2 SDRAM Addressing  
1Gb Addressing  
Configuration  
# of Bank  
256Mb x4  
8
128Mb x 8  
8
64Mb x16  
8
Bank Address  
Auto precharge  
Row Address  
Column Address  
BA0 ~ BA2  
A10/AP  
BA0 ~ BA2  
A10/AP  
A0 ~ A13  
A0 ~ A9  
BA0 ~ BA2  
A10/AP  
A0 ~ A12  
A0 ~ A9  
A0 ~ A13  
A0 ~ A9,A11  
* Reference information: The following tables are address mapping information for other densities.  
256Mb  
Configuration  
# of Bank  
64Mb x4  
4
32Mb x 8  
4
16Mb x16  
4
Bank Address  
Auto precharge  
Row Address  
Column Address  
BA0,BA1  
A10/AP  
BA0,BA1  
A10/AP  
A0 ~ A12  
A0 ~ A9  
BA0,BA1  
A10/AP  
A0 ~ A12  
A0 ~ A8  
A0 ~ A12  
A0 ~ A9,A11  
512Mb  
Configuration  
# of Bank  
128Mb x4  
4
64Mb x 8  
4
32Mb x16  
4
Bank Address  
Auto precharge  
Row Address  
Column Address  
BA0,BA1  
A10/AP  
BA0,BA1  
A10/AP  
A0 ~ A13  
A0 ~ A9  
BA0,BA1  
A10/AP  
A0 ~ A12  
A0 ~ A9  
A0 ~ A13  
A0 ~ A9,A11  
2Gb  
Configuration  
# of Bank  
512Mb x4  
8
256Mb x 8  
8
128Mb x16  
8
Bank Address  
Auto precharge  
Row Address  
Column Address  
BA0 ~ BA2  
A10/AP  
BA0 ~ BA2  
A10/AP  
A0 ~ A14  
A0 ~ A9  
BA0 ~ BA2  
A10/AP  
A0 ~ A13  
A0 ~ A9  
A0 ~ A14  
A0 ~ A9,A11  
4Gb  
Configuration  
# of Bank  
1 Gb x4  
8
512Mb x 8  
8
256Mb x16  
8
Bank Address  
Auto precharge  
Row Address  
Column Address  
BA0 ~ BA2  
A10/AP  
BA0 ~ BA2  
A10/AP  
A0 - A15  
A0 - A9  
BA0 ~ BA2  
A10/AP  
A0 - A14  
A0 - A9  
A0 - A15  
A0 - A9,A11  
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K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
6.0 Absolute Maximum DC Ratings  
Symbol  
VDD  
Parameter  
Rating  
Units  
V
Notes  
Voltage on VDD pin relative to VSS  
- 1.0 V ~ 2.3 V  
- 0.5 V ~ 2.3 V  
- 0.5 V ~ 2.3 V  
- 0.5 V ~ 2.3 V  
-55 to +100  
1
1
Voltage on VDDQ pin relative to VSS  
Voltage on VDDL pin relative to VSS  
Voltage on any pin relative to VSS  
Storage Temperature  
VDDQ  
VDDL  
V
V
1
V
IN, VOUT  
TSTG  
Note :  
V
1
°C  
1, 2  
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and  
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2  
standard.  
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ. When VDD and VDDQ and VDDL are less  
than 500mV, VREF may be equal to or less than 300mV.  
4. Voltage on any input or I/O may not exceed voltage on VDDQ  
.
7.0 AC & DC Operating Conditions  
7.1 Recommended DC Operating Conditions (SSTL - 1.8)  
Rating  
Typ.  
1.8  
Symbol  
Parameter  
Units  
Notes  
Min.  
1.7  
Max.  
1.9  
VDD  
VDDL  
VDDQ  
VREF  
VTT  
Supply Voltage  
V
V
Supply Voltage for DLL  
Supply Voltage for Output  
Input Reference Voltage  
Termination Voltage  
1.7  
1.8  
1.8  
1.9  
4
4
1.7  
1.9  
V
0.49*VDDQ  
VREF-0.04  
0.50*VDDQ  
VREF  
0.51*VDDQ  
VREF+0.04  
mV  
V
1,2  
3
Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal  
to VDD  
.
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5  
x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ  
2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC).  
3. VTT of transmitting device must track VREF of receiving device.  
.
4. AC parameters are measured with VDD, VDDQ and VDDL tied together.  
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K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
7.2 Operating Temperature Condition  
Symbol  
TOPER  
Parameter  
Operating Temperature  
Rating  
0 to 95  
Units  
°C  
Notes  
1, 2  
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to  
JESD51.2 standard.  
2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to  
self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.  
7.3 Input DC Logic Level  
Symbol  
Parameter  
Min.  
Max.  
Units  
Notes  
VIH(DC)  
VREF + 0.125  
VDDQ + 0.3  
V
DC input logic high  
DC input logic low  
VIL(DC)  
- 0.3  
VREF - 0.125  
V
7.4 Input AC Logic Level  
DDR2-667, DDR2-800  
Symbol  
Parameter  
Units  
Min.  
VREF + 0.200  
VSSQ - VPEAK  
Max.  
V
IH(AC)  
VDDQ + VPEAK  
V
V
AC input logic high  
AC input logic low  
VIL(AC)  
VREF - 0.200  
Note :  
1. For information related to VPEAK value, Refer to overshoot/undershoot specification in device operation and timing datasheet; maximum peak ampli-  
tude allowed for overshoot and undershoot.  
7.5 AC Input Test Conditions  
Symbol  
Condition  
Value  
Units  
Notes  
VREF  
Input reference voltage  
0.5 * VDDQ  
V
1
VSWING(MAX)  
SLEW  
Input signal maximum peak to peak swing  
Input signal minimum slew rate  
1.0  
1.0  
V
1
V/ns  
2, 3  
Note :  
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.  
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC)  
max for falling edges as shown in the below figure.  
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative  
transitions.  
V
V
V
V
DDQ  
(AC)min  
IH  
IH  
(DC)min  
V
SWING(MAX)  
REF  
V (DC)max  
IL  
V (AC)max  
IL  
V
SS  
delta TF  
V
delta TR  
Rising Slew =  
- V (AC)max  
IL  
V
(AC)min - V  
delta TR  
REF  
IH  
REF  
Falling Slew =  
delta TF  
< AC Input Test Signal Waveform >  
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K4T1G164QE  
DDR2 SDRAM  
7.6 Differential input AC logic Level  
Symbol  
ID(AC)  
VIX(AC)  
Parameter  
Min.  
0.5  
Max.  
VDDQ  
Units  
V
Notes  
1
V
AC differential input voltage  
AC differential cross point voltage  
0.5 * VDDQ - 0.175  
0.5 * VDDQ + 0.175  
V
2
Note :  
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS)  
and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to VIH (AC) - VIL(AC).  
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC)  
indicates the voltage at which differential input signals must cross.  
3. For information related to VPEAK value, Refer to overshoot/undershoot specification in device operation and timing datasheet; maximum peak ampli-  
tude allowed for overshoot and undershoot.  
V
DDQ  
V
TR  
Crossing point  
V
ID  
V
V
IX or OX  
V
CP  
V
SSQ  
< Differential signal levels >  
7.7 Differential AC output parameters  
Symbol  
Parameter  
Min.  
0.5 * VDDQ - 0.125  
Max.  
0.5 * VDDQ + 0.125  
Units  
V
Note  
1
V
OX(AC)  
AC differential cross point voltage  
Note :  
1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ  
.
V
OX(AC) indicates the voltage at which differential output signals must cross.  
8.0 ODT DC electrical characteristics  
PARAMETER/CONDITION  
Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm  
Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm  
Rtt effective impedance value for EMRS(A6,A2)=1,1; 50 ohm  
Deviation of VM with respect to VDDQ/2  
SYMBOL  
Rtt1(eff)  
Rtt2(eff)  
Rtt3(eff)  
delta VM  
MIN  
60  
NOM  
75  
MAX  
90  
UNITS  
ohm  
ohm  
ohm  
%
NOTES  
1
1
1
1
120  
40  
150  
50  
180  
60  
- 6  
+ 6  
Note : Test condition for Rtt measurements  
Measurement Definition for Rtt(eff): Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH (AC)) and I( VIL (AC)) respectively.  
IH (AC), VIL (AC)(DC), and VDDQ values defined in SSTL_18  
V
VIH (AC) - VIL (AC)  
Rtt(eff) =  
I(VIH (AC)) - I(VIL (AC))  
2 x VM  
- 1  
x 100%  
delta VM =  
VDDQ  
Measurement Definition for VM: Measure voltage (VM) at test pin (midpoint) with no load.  
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K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
9.0 OCD default characteristics  
Description  
Parameter  
Min  
Nom  
Max  
Unit  
Notes  
18ohm at norminal condition  
See full strength default driver characteristics  
on device operation specification  
Output impedance  
ohm  
1,2  
Output impedance step size for OCD calibration  
Pull-up and pull-down mismatch  
Output slew rate  
0
0
1.5  
4
ohm  
ohm  
V/ns  
6
1,2,3  
Sout  
1.5  
5
1,4,5,6,7,8  
Note :  
1. Absolute Specifications (0°C TCASE +95°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)  
2. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh must be less than 23.4 ohms for  
values of VOUT between VDDQ and VDDQ- 280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV;  
V
OUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV.  
3. Mismatch is absolute value between pull-up and pull-down, both are measured at same temperature and voltage.  
4. Slew rate measured from VIL(AC) to VIH(AC).  
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is  
guaranteed by design and characterization.  
6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the DRAM uncertainty.  
Output slew rate load :  
VTT  
25 ohm  
Output  
Reference  
Point  
(VOUT  
)
7. DRAM output slew rate specification applies to 667Mb/sec/pin and 800Mb/sec/pin speed bins.  
8. Timing skew due to DRAM output slew rate mismatch between DQS / DQS and associated DQ is included in tDQSQ and tQHS specification.  
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DDR2 SDRAM  
10.0 IDD Specification Parameters and Test Conditions  
(IDD values are for full operating range of Voltage and Temperature, Notes 1 - 5)  
Symbol  
Proposed Conditions  
Units  
Notes  
Operating one bank active-precharge current;  
IDD0  
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH between valid commands;  
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING  
mA  
Operating one bank active-read-precharge current;  
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =  
tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address businputs are SWITCHING; Data pattern  
is same as IDD4W  
IDD1  
mA  
Precharge power-down current;  
IDD2P  
IDD2Q  
IDD2N  
IDD3P  
IDD3N  
All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are  
FLOATING  
mA  
mA  
mA  
Precharge quiet standby current;  
t
All banks idle; tCK = CK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputsare STABLE; Data  
bus inputs are FLOATING  
Precharge standby current;  
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
Active power-down current;  
mA  
mA  
Fast PDN Exit MRS(12) = 0  
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus  
Slow PDN Exit MRS(12) = 1  
inputs are STABLE; Data bus inputs are FLOATING  
Active standby current;  
All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid  
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING  
mA  
mA  
Operating burst write current;  
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP  
= tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus  
inputs are SWITCHING  
IDD4W  
IDD4R  
Operating burst read current;  
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRAS-  
max(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCH-  
ING; Data pattern is same as IDD4W  
mA  
mA  
Burst auto refresh current;  
IDD5B  
IDD6  
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid com-  
mands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING  
Self refresh current;  
Normal  
mA  
mA  
CK and CK at 0V; CKE 0.2V; Other control and address bus inputs are  
FLOATING; Data bus inputs are FLOATING  
Low Power  
Operating bank interleave read current;  
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC  
= tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid  
commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the fol-  
lowing page for detailed timing conditions  
IDD7  
mA  
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K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
Note :  
1. IDD specifications are tested after the device is properly initialized  
2. Input slew rate is specified by AC Parametric Test Condition  
3. IDD parameters are specified with ODT disabled.  
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS  
bits 10 and 11.  
5. Definitions for IDD  
LOW is defined as VIN VIL(AC)max  
HIGH is defined as VIN VIH(AC)min  
STABLE is defined as inputs stable at a HIGH or LOW level  
FLOATING is defined as inputs at VREF = VDDQ/2  
SWITCHING is defined as:  
inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control  
signals, and  
inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including  
masks or strobes.  
For purposes of IDD testing, the following parameters are utilized  
DDR2-800  
DDR2-800  
DDR2-667  
Units  
Parameter  
CL(IDD)  
5-5-5  
6-6-6  
5-5-5  
5
6
5
tCK  
tRCD(IDD)  
12.5  
57.5  
15  
60  
15  
60  
ns  
ns  
tRC(IDD)  
tRRD(IDD)-x4/x8  
tRRD(IDD)-x16  
tCK(IDD)  
ns  
ns  
7.5  
7.5  
7.5  
10  
2.5  
10  
2.5  
10  
3
ns  
ns  
ns  
ns  
tRASmin(IDD)  
tRP(IDD)  
45  
45  
45  
12.5  
127.5  
15  
15  
tRFC(IDD)  
127.5  
127.5  
Detailed IDD7  
The detailed timings are shown below for IDD7.  
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect  
IDD7: Operating Current: All Bank Interleave Read operation  
All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) and tFAW(IDD) using a burst length of 4. Control and address bus  
inputs are STABLE during DESELECTs. IOUT = 0mA  
Timing Patterns for 8bank devices x4/ x8  
-DDR2-667 5/5/5 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D  
-DDR2-800 6/6/6 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D  
-DDR2-800 5/5/5 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D  
Timing Patterns for 8bank devices x16  
-DDR2-667 5/5/5 : A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D  
-DDR2-800 6/6/6 : A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D  
-DDR2-800 5/5/5 : A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D  
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K4T1G164QE  
11.0 DDR2 SDRAM IDD Spec Table  
DDR2 SDRAM  
128Mx4 (K4T1G044QE)  
Symbol  
Unit  
Notes  
Notes  
Notes  
800@CL=5  
CE7 LE7  
800@CL=6  
667@CL=5  
CE6 LE6  
CF7  
LF7  
IDD0  
IDD1  
52  
58  
52  
58  
50  
55  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IDD2P  
IDD2Q  
IDD2N  
IDD3P-F  
IDD3P-S  
IDD3N  
IDD4W  
IDD4R  
IDD5  
10  
5
10  
5
10  
5
23  
28  
26  
15  
37  
67  
85  
120  
23  
28  
26  
15  
37  
67  
85  
120  
23  
27  
25  
15  
35  
60  
75  
115  
IDD6  
10  
5
10  
5
10  
5
IDD7  
165  
165  
150  
128Mx8 (K4T1G084QE)  
800@CL=6  
Symbol  
Unit  
800@CL=5  
667@CL=5  
CE7  
LE7  
CF7  
LF7  
CE6  
LE6  
IDD0  
IDD1  
52  
58  
52  
58  
50  
55  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IDD2P  
IDD2Q  
IDD2N  
IDD3P-F  
IDD3P-S  
IDD3N  
IDD4W  
IDD4R  
IDD5  
10  
5
10  
5
10  
5
23  
28  
26  
15  
37  
72  
90  
120  
23  
28  
26  
15  
37  
72  
90  
120  
23  
27  
25  
15  
35  
65  
80  
115  
IDD6  
10  
5
10  
5
10  
5
IDD7  
170  
170  
155  
64Mx16 (K4T1G164QE)  
800@CL=6  
Symbol  
Unit  
800@CL=5  
CE7 LE7  
667@CL=5  
CE6 LE6  
CF7  
LF7  
IDD0  
IDD1  
65  
75  
65  
75  
60  
70  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IDD2P  
IDD2Q  
IDD2N  
IDD3P-F  
IDD3P-S  
IDD3N  
IDD4W  
IDD4R  
IDD5  
10  
5
10  
5
10  
5
25  
32  
25  
32  
25  
30  
28  
28  
27  
15  
15  
15  
40  
40  
37  
95  
95  
90  
125  
115  
125  
115  
115  
110  
IDD6  
10  
5
10  
5
10  
5
IDD7  
200  
200  
185  
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K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
12.0 Input/Output capacitance  
DDR2-667  
DDR2-800  
Units  
Parameter  
Symbol  
Min  
1.0  
x
Max  
2.0  
Min  
Max  
2.0  
Input capacitance, CK and CK  
CCK  
CDCK  
CI  
1.0  
x
pF  
pF  
pF  
pF  
pF  
pF  
Input capacitance delta, CK and CK  
0.25  
2.0  
0.25  
1.75  
0.25  
3.5  
Input capacitance, all other input-only pins  
Input capacitance delta, all other input-only pins  
Input/output capacitance, DQ, DM, DQS, DQS  
Input/output capacitance delta, DQ, DM, DQS, DQS  
1.0  
x
1.0  
x
CDI  
0.25  
3.5  
CIO  
2.5  
x
2.5  
x
CDIO  
0.5  
0.5  
13.0 Electrical Characteristics & AC Timing for DDR2-800/667  
(0 °C < TOPER < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)  
13.1 Refresh Parameters by Device Density  
Parameter  
Refresh to active/Refresh command time  
Symbol  
256Mb  
75  
512Mb  
1Gb  
127.5  
7.8  
2Gb  
195  
7.8  
4Gb  
327.5  
7.8  
Units  
ns  
tRFC  
tREFI  
105  
7.8  
3.9  
0 °C TCASE 85°C  
85 °C < TCASE 95°C  
7.8  
µs  
Average periodic refresh interval  
3.9  
3.9  
3.9  
3.9  
µs  
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin  
Speed  
Bin (CL - tRCD - tRP)  
Parameter  
tCK, CL=3  
tCK, CL=4  
tCK, CL=5  
tCK, CL=6  
tRCD  
DDR2-800(E7)  
DDR2-800(F7)  
DDR2-667(E6)  
5 - 5 - 5  
5-5-5  
6-6-6  
Units  
min  
max  
min  
max  
min  
max  
5
8
-
3.75  
3
-
5
3.75  
3
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
3.75  
2.5  
-
8
8
8
8
8
8
-
2.5  
15  
15  
60  
45  
8
-
-
12.5  
12.5  
57.5  
45  
-
-
15  
15  
60  
45  
-
tRP  
-
-
-
-
-
-
tRC  
tRAS  
70000  
70000  
70000  
19 of 45  
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K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
13.3 Timing Parameters by Speed Grade  
(For information related to the entries in this table, refer to both the general notes and the specific notes following this table.)  
DDR2-800  
DDR2-667  
Parameter  
Symbol  
Units  
Notes  
min  
max  
400  
min  
max  
450  
DQ output access time from CK/CK  
DQS output access time from CK/CK  
Average clock HIGH pulse width  
Average clock LOW pulse width  
tAC  
-400  
-350  
0.48  
0.48  
-450  
-400  
0.48  
0.48  
ps  
40  
40  
tDQSCK  
tCH(avg)  
tCL(avg)  
350  
400  
ps  
0.52  
0.52  
0.52  
0.52  
tCK(avg)  
tCK(avg)  
35,36  
35,36  
Min(tCL(abs),  
tCH(abs))  
Min(tCL(abs),  
tCH(abs))  
CK half pulse period  
tHP  
x
x
ps  
37  
Average clock period  
tCK(avg)  
tDH(base)  
tDS(base)  
tIPW  
2500  
8000  
3000  
8000  
ps  
ps  
35,36  
DQ and DM input hold time  
125  
x
175  
x
6,7,8,21,28,31  
6,7,8,20,28,31  
DQ and DM input setup time  
50  
x
100  
x
ps  
Control & Address input pulse width for each input  
DQ and DM input pulse width for each input  
Data-out high-impedance time from CK/CK  
DQS/DQS low-impedance time from CK/CK  
DQ low-impedance time from CK/CK  
DQS-DQ skew for DQS and associated DQ signals  
DQ hold skew factor  
0.6  
x
0.6  
x
tCK(avg)  
tCK(avg)  
ps  
tDIPW  
tHZ  
0.35  
x
0.35  
x
x
tAC(max)  
x
tAC(max)  
18,40  
18,40  
18,40  
13  
tLZ(DQS)  
tLZ(DQ)  
tDQSQ  
tQHS  
tAC(min)  
tAC(max)  
tAC(min)  
tAC(max)  
ps  
2* tAC(min)  
tAC(max)  
2* tAC(min)  
tAC(max)  
ps  
x
x
200  
300  
x
x
x
240  
340  
x
ps  
ps  
38  
DQ/DQS output hold time from DQS  
DQS latching rising transitions to associated clock edges  
DQS input HIGH pulse width  
tQH  
tHP - tQHS  
- 0.25  
0.35  
0.35  
0.2  
tHP - tQHS  
-0.25  
0.35  
0.35  
0.2  
ps  
39  
tDQSS  
tDQSH  
tDQSL  
tDSS  
0.25  
x
0.25  
x
tCK(avg)  
tCK(avg)  
tCK(avg)  
tCK(avg)  
tCK(avg)  
nCK  
30  
DQS input LOW pulse width  
x
x
DQS falling edge to CK setup time  
DQS falling edge hold time from CK  
Mode register set command cycle time  
MRS command to ODT update delay  
Write postamble  
x
x
30  
30  
tDSH  
0.2  
x
0.2  
x
tMRD  
2
x
2
x
tMOD  
0
12  
0.6  
x
0
12  
0.6  
x
ns  
32  
10  
tWPST  
tWPRE  
tIH(base)  
tIS(base)  
tRPRE  
tRPST  
0.4  
0.4  
tCK(avg)  
tCK(avg)  
ps  
Write preamble  
0.35  
250  
175  
0.9  
0.35  
275  
200  
0.9  
Address and control input hold time  
Address and control input setup time  
Read preamble  
x
x
5,7,9,23,29  
5,7,9,22,29  
19,41  
x
x
ps  
1.1  
0.6  
x
1.1  
0.6  
x
tCK(avg)  
tCK(avg)  
ns  
Read postamble  
0.4  
0.4  
19,42  
Activate to activate command period for 1KB page size products tRRD  
Activate to activate command period for 2KB page size products tRRD  
7.5  
7.5  
4,32  
10  
x
10  
x
ns  
4,32  
20 of 45  
Rev. 1.1 December 2008  
K4T1G044QE  
K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
DDR2-800  
DDR2-667  
Parameter  
Symbol  
Units  
Notes  
min  
max  
min  
max  
Four Activate Window for 1KB page size products  
Four Activate Window for 2KB page size products  
CAS to CAS command delay  
tFAW  
tFAW  
tCCD  
tWR  
35  
x
x
x
x
x
x
x
x
x
x
x
37.5  
x
x
x
x
x
x
x
x
x
x
x
ns  
ns  
32  
32  
45  
50  
2
2
nCK  
ns  
Write recovery time  
15  
15  
32  
33  
Auto precharge write recovery + precharge time  
Internal write to read command delay  
Internal read to precharge command delay  
Exit self refresh to a non-read command  
Exit self refresh to a read command  
tDAL  
WR + tnRP  
WR + tnRP  
nCK  
ns  
tWTR  
tRTP  
tXSNR  
tXSRD  
tXP  
7.5  
7.5  
24,32  
3,32  
32  
7.5  
7.5  
ns  
tRFC + 10  
tRFC + 10  
ns  
200  
2
200  
2
nCK  
nCK  
nCK  
Exit precharge power down to any command  
Exit active power down to read command  
tXARD  
2
2
1
Exit active power down to read command  
(slow exit, lower power)  
tXARDS  
8 - AL  
x
7 - AL  
x
nCK  
1,2  
CKE minimum pulse width (HIGH and LOW pulse width)  
tCKE  
3
2
x
3
2
x
nCK  
nCK  
ns  
27  
16  
ODT turn-on delay  
ODT turn-on  
tAOND  
tAON  
2
2
tAC(min)  
tAC(max)+0.7  
tAC(min)  
tAC(max)+0.7  
6,16,40  
2*tCK(avg)  
2*tCK(avg)  
ODT turn-on (Power-Down mode)  
tAONPD  
tAC(min)+2  
tAC(min)+2  
ns  
+tAC(max)+1  
+tAC(max)+1  
ODT turn-off delay  
ODT turn-off  
tAOFD  
tAOF  
2.5  
2.5  
2.5  
2.5  
nCK  
ns  
17,45  
tAC(min)  
tAC(max)+0.6  
tAC(min)  
tAC(max)+0.6  
17,43,45  
2.5*tCK(avg)+  
tAC(max)+1  
2.5*tCK(avg)+  
tAC(max)+1  
ODT turn-off (Power-Down mode)  
tAOFPD  
tAC(min)+2  
tAC(min)+2  
ns  
ODT to power down entry latency  
ODT power down exit latency  
OCD drive mode output delay  
tANPD  
tAXPD  
tOIT  
3
8
0
x
x
3
8
0
x
x
nCK  
nCK  
ns  
12  
12  
32  
15  
Minimum time clocks remains ON after CKE asynchronously  
drops LOW  
tIS+tCK(avg)  
+tIH  
tIS+tCK(avg)  
+tIH  
tDelay  
x
x
ns  
21 of 45  
Rev. 1.1 December 2008  
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DDR2 SDRAM  
14.0 General notes, which may apply for all AC parameters  
1. DDR2 SDRAM AC timing reference load  
Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise repre  
sentation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or other  
simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally  
a coaxial transmission line terminated at the tester electronics).  
VDDQ  
DQ  
DQS  
DQS Output  
DUT  
VTT = VDDQ/2  
RDQS  
RDQS  
25Ω  
Timing  
reference  
point  
Figure 1 - AC Timing Reference Load  
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential  
signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal.  
2. Slew Rate Measurement Levels  
a) Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals  
(e.g. DQS - DQS) output slew rate is measured between DQS - DQS = - 500 mV and DQS - DQS = + 500 mV. Output slew rate is guaranteed by  
design, but is not necessarily tested on each device.  
b) Input slew rate for single ended signals is measured from VREF(DC) to VIH(AC),min for rising edges and from VREF(DC) to VIL(AC),max for falling  
edges. For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = - 250 mV to CK - CK = + 500 mV (+ 250 mV to -  
500 mV for falling edges).  
c) VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential strobe.  
3. DDR2 SDRAM output slew rate test load  
Output slew rate is characterized under the test conditions as shown in Figure 2.  
VDDQ  
DUT  
DQ  
Output  
Test point  
DQS, DQS  
RDQS, RDQS  
VTT = VDDQ/2  
25Ω  
Figure 2 - Slew Rate Test Load  
22 of 45  
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DDR2 SDRAM  
4. Differential data strobe  
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit;  
timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode depen-  
dent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these  
timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design  
and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS  
through a 20 to 10 kresistor to insure proper operation.  
tDQSH  
tDQSL  
DQS  
DQS  
DQS  
DQS  
tWPRE  
tWPST  
VIH(DC)  
VIH(AC)  
DQ  
DM  
D
D
D
D
VIL(AC)  
VIL(DC)  
tDH  
tDS  
tDH  
tDS  
VIH(AC)  
VIH(DC)  
DMin  
DMin  
DMin  
DMin  
VIL(AC)  
VIL(DC)  
Figure 3 - Data Input (Write) Timing  
tCH  
tCL  
CK  
CK  
CK/CK  
DQS  
DQS  
DQS/DQS  
DQ  
tRPRE  
tRPST  
Q
Q
Q
Q
tDQSQ(max)  
tDQSQ(max)  
tQH  
tQH  
Figure 4 - Data Output (Read) Timing  
5. AC timings are for linear signal transitions. See Specific Notes on derating for other signal transitions.  
6. All voltages are referenced to VSS  
.
7. These parameters guarantee device behavior, but they are not necessarily tested on each device.  
They may be guaranteed by device design or tester correlation.  
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related  
specifications and device operation are guaranteed for the full voltage range specified.  
23 of 45  
Rev. 1.1 December 2008  
K4T1G044QE  
K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
15.0 Specific Notes for dedicated AC parameters  
1. User can choose which active power down exit timing to use via MRS (bit 12). tXARD is expected to be used for fast active power down exit timing.  
tXARDS is expected to be used for slow active power down exit timing.  
2. AL = Additive Latency.  
3. This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that the tRTP and tRAS(min) have been satisfied.  
4. A minimum of two clocks (2 x tCK or 2 x nCK) is required irrespective of operating frequency.  
5. Timings are specified with command/address input slew rate of 1.0 V/ns.  
6. Timings are specified with DQs, DM, and DQS’s (DQS/RDQS in single ended mode) input slew rate of 1.0V/ns.  
7. Timings are specified with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns in  
differential strobe mode and a slew rate of 1.0 V/ns in single ended mode.  
8. Data setup and hold time derating.  
Table 1 - DDR2-400/533 tDS/tDH derating with differential data strobe  
tDS, tDH Derating Values of DDR2-400, DDR2-533 (ALL units in ‘ps’, the note applies to entire Table)  
DQS,DQS Differential Slew Rate  
4.0 V/ns  
3.0 V/ns  
2.0 V/ns  
1.8 V/ns  
1.6 V/ns  
1.4V/ns  
1.2V/ns  
1.0V/ns  
0.8V/ns  
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH  
2.0  
1.5  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
125  
45  
21  
0
-
-
-
-
-
-
125  
83  
0
-11  
-
-
-
-
-
45  
21  
0
-14  
-
-
-
-
-
125  
83  
0
-11  
-25  
-
-
-
-
45  
21  
0
-14  
-31  
-
-
-
-
-
95  
12  
1
-13  
-31  
-
-
33  
12  
-2  
-19  
-42  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23  
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
83  
0
-
-
-
-
-
-
24  
13  
-1  
-19  
-43  
-
24  
10  
-7  
-30  
-59  
-
DQ  
Siew  
rate  
25  
11  
-7  
-31  
-74  
-
22  
5
-18  
-47  
-89  
-
-
17  
-6  
-35  
-77  
17  
-7  
-50  
6
-23  
-65  
-
5
-38  
-
V/ns  
-19  
-62  
-11  
-53  
-
-
-
-
-
-
-127 -140 -115 -128 -103 -116  
Table 2 - DDR2-667/800 tDS/tDH derating with differential data strobe  
tDS, tDH Derating Values for DDR2-667, DDR2-800 (ALL units in ‘ps’, the note applies to entire Table)  
DQS,DQS Differential Slew Rate  
4.0 V/ns  
3.0 V/ns  
2.0 V/ns  
1.8 V/ns  
1.6 V/ns  
1.4V/ns  
1.2V/ns  
1.0V/ns  
0.8V/ns  
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH  
2.0  
1.5  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
100  
45  
21  
0
-
-
-
-
-
-
100  
45  
21  
0
-14  
-
-
-
-
-
100  
67  
0
-5  
-13  
-
-
-
-
45  
21  
0
-14  
-31  
-
-
-
-
-
79  
12  
7
-1  
-10  
-
-
33  
12  
-2  
-19  
-42  
-
-
-
24  
19  
11  
2
-10  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
17  
-6  
-35  
-77  
-140  
-
-
-
-
-
38  
26  
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
67  
0
-
-
-
-
-
-
67  
0
-5  
-
-
-
24  
10  
-7  
-30  
-59  
-
DQ  
Slew  
rate  
31  
23  
14  
2
-24  
-
22  
5
-18  
-47  
-89  
-
-
35  
26  
14  
-12  
-52  
6
-
-
V/ns  
-23  
-65  
-128  
38  
12  
-28  
-11  
-53  
-116  
-
-
-
-
-
-
-
-40  
24 of 45  
Rev. 1.1 December 2008  
K4T1G044QE  
K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
Table 3 - DDR2-400/533 tDS1/tDH1 derating with single-ended data strobe  
tDS1, tDH1 Derating Values for DDR2-400, DDR2-533(All units in ‘ps’; the note applies to the entire table)  
DQS Single-ended Slew Rate  
2.0 V/ns  
1.5 V/ns  
1.0 V/ns  
0.9 V/ns  
0.8 V/ns  
0.7 V/ns  
0.6 V/ns  
0.5 V/ns  
0.4 V/ns  
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH  
1
188  
146  
63  
-
-
-
-
-
1
188  
167  
125  
-
-
-
-
-
-
1
167  
125  
42  
31  
-
-
-
-
-
1
146  
125  
83  
69  
-
-
-
-
-
1
125  
83  
0
-11  
-25  
-
-
-
-
1
63  
42  
0
-14  
-31  
-
-
-
-
1
-
1
-
43  
1
-13  
-30  
-53  
-
1
-
-
-7  
-18  
-32  
-50  
-74  
-
1
-
-
-13  
-27  
-44  
-67  
-96  
-
1
-
-
1
-
-
1
-
-
-
-
1
-
-
-
-
1
-
-
-
-
1
-
-
-
-
1
-
-
-
-
-
-
1
-
-
-
-
-
-
2.0  
1.5  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
81  
-2  
-13  
-27  
-45  
-
-
-
DQ  
Slew  
rate  
-29  
-43  
-61  
-85  
-45  
-62  
-85  
-60  
-78  
-86  
-
-
-109 -108 -152  
V/ns  
-114 -102 -138 -138 -181 -183 -246  
-
-
-
-
-128 -156 -145 -180 -175 -223 -226 -288  
-210 -243 -240 -286 -291 -351  
-
-
-
-
-
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value to the  
tDS and tDH derating value respectively. Example: tDS (total setup time) =tDS(base) +tDS.  
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min.  
Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max.  
If the actual signal is always earlier than the nominal slew rate line between shaded ’VREF(DC) to ac region’, use nominal slew rate for derating value  
(See Figure 5 for differential data strobe and Figure 6 for single-ended data strobe.) If the actual signal is later than the nominal slew rate line anywhere  
between shaded ’VREF(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see  
Figure 7 for differential data strobe and Figure 8 for single-ended data strobe)  
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC).  
Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If  
the actual signal is always later than the nominal slew rate line between shaded ’dc level to VREF(DC) region’, use nominal slew rate for derating value  
(see Figure 9 for differential data strobe and Figure 10 for single-ended data strobe) If the actual signal is earlier than the nominal slew rate line anywhere  
between shaded ’dc to VREF(DC) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(DC) level is used for derating value  
(see Figure 11 for differential data strobe and Figure 12 for single-ended data strobe)  
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(AC) at the time of the rising clock  
transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC).  
For slew rates in between the values listed in Tables 1, 2 and 3, the derating values may obtained by linear interpolation.  
These values are typically not subject to production test. They are verified by design and characterization.  
25 of 45  
Rev. 1.1 December 2008  
K4T1G044QE  
K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
DQS  
DQS  
tDH  
tDH  
tDS  
tDS  
VDDQ  
VIH(AC)min  
VREF to ac  
region  
V
IH(DC)min  
nominal  
slew rate  
VREF(DC)  
nominal slew  
rate  
VIL(DC)max  
VREF to ac  
region  
VIL(AC)max  
VSS  
tVAC  
TF  
TR  
V
REF(DC) - VIL(AC)max  
V
IH(AC)min - VREF(DC)  
Setup Slew Rate  
Rising Signal  
Setup Slew Rate  
=
=
Falling Signal  
TF  
TR  
Figure 5 - IIIustration of nominal slew rate for tDS (differential DQS,DQS)  
26 of 45  
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K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
VDDQ  
VIH(AC)min  
VIH(DC)min  
VREF(DC)  
VIL(DC)max  
VIL(AC)max  
VSS  
DQS  
Note1  
tDH  
tDS  
tDS  
tDH  
VDDQ  
VIH(AC)min  
VREF to ac  
region  
V
IH(DC)min  
nominal  
slew rate  
VREF(DC)  
nominal slew  
rate  
VIL(DC)max  
VREF to ac  
region  
VIL(AC)max  
VSS  
TF  
TR  
V
REF(DC) - V (AC)max  
VIH(AC)min - VREF(DC)  
Setup Slew Rate  
Rising Signal  
IL  
Setup Slew Rate  
=
=
Falling Signal  
TF  
TR  
Note : DQS signal must be monotonic between VIL(AC)max and VIH(AC)min.  
Figure 6 - IIIustration of nominal slew rate for tDS (single-ended DQS)  
27 of 45  
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K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
DQS  
DQS  
tDH  
tDH  
tDS  
tDS  
VDDQ  
nominal  
line  
VIH(AC)min  
V
REF to ac  
region  
V
IH(DC)min  
tangent  
line  
VREF(DC)  
tangent  
line  
VIL(DC)max  
VIL(AC)max  
VREF to ac  
region  
nominal  
line  
TR  
VSS  
tangent line[VIH(AC)min - VREF(DC)]  
Setup Slew Rate  
=
Rising Signal  
TF  
TR  
tangent line[VREF(DC) - VIL(AC)max]  
Setup Slew Rate  
=
Falling Signal  
TF  
Figure 7 - IIIustration of tangent line for tDS (differential DQS, DQS)  
28 of 45  
Rev. 1.1 December 2008  
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K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
VDDQ  
VIH(AC)min  
DQS  
V
IH(DC)min  
Note1  
VREF(DC)  
VIL(DC)max  
VIL(AC)max  
VSS  
tDH  
tDS  
tDS  
tDH  
VDDQ  
nominal  
line  
VIH(AC)min  
V
REF to ac  
region  
V
IH(DC)min  
tangent  
line  
VREF(DC)  
tangent  
line  
VIL(DC)max  
VIL(AC)max  
VREF to ac  
region  
nominal  
line  
TR  
VSS  
tangent line[VIH(AC)min - VREF(DC)]  
Setup Slew Rate  
=
Rising Signal  
TR  
TF  
tangent line[VREF(DC) - VIL(AC)max]  
Setup Slew Rate  
=
Falling Signal  
TF  
Note : DQS signal must be monotonic between VIL(DC)max and VIH(DC)min.  
Figure 8 - IIIustration of tangent line for tDS (single-ended DQS)  
29 of 45  
Rev. 1.1 December 2008  
K4T1G044QE  
K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
DQS  
DQS  
tDH  
tDH  
tDS  
tDS  
VDDQ  
VIH(AC)min  
V
IH(DC)min  
dc to VREF  
region  
nominal  
slew rate  
VREF(DC)  
nominal  
dc to VREF  
region  
slew rate  
VIL(DC)max  
VIL(AC)max  
VSS  
TF  
TR  
Hold Slew Rate  
VREF(DC) - VIL(DC)max  
Hold Slew Rate  
Rising Signal  
VIH(DC)min - VREF(DC)  
=
=
TR  
Falling Signal  
TF  
Figure 9 - IIIustration of nominal slew rate for tDH (differential DQS, DQS)  
30 of 45  
Rev. 1.1 December 2008  
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K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
VDDQ  
VIH(AC)min  
DQS  
V
IH(DC)min  
Note1  
VREF(DC)  
VIL(DC)max  
VIL(AC)max  
VSS  
tDH  
tDS  
tDS  
tDH  
VDDQ  
VIH(AC)min  
V
IH(DC)min  
dc to VREF  
region  
nominal  
slew rate  
VREF(DC)  
nominal  
dc to VREF  
region  
slew rate  
VIL(DC)max  
VIL(AC)max  
VSS  
TF  
TR  
Hold Slew Rate  
VREF(DC) - VIL(DC)max  
Hold Slew Rate  
Rising Signal  
VIH(DC)min - VREF(DC)  
=
=
TR  
Falling Signal  
TF  
Note : DQS signal must be monotonic between VIL(DC)max and VIH(DC)min.  
Figure 10 - IIIustration of nominal slew rate for tDH (single-ended DQS)  
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K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
DQS  
DQS  
tDH  
tDH  
tDS  
tDS  
VDDQ  
VIH(AC)min  
nominal  
line  
V
IH(DC)min  
dc to VREF  
region  
tangent  
line  
VREF(DC)  
tangent  
line  
dc to VREF  
region  
nominal  
line  
VIL(DC)max  
VIL(AC)max  
VSS  
TF  
TR  
tangent line [ VREF(DC) - VIL(DC)max ]  
Hold Slew Rate  
=
Rising Signal  
TR  
tangent line [ VIH(DC)min - VREF(DC) ]  
Hold Slew Rate  
=
Falling Signal  
TF  
Figure 11 - IIIustration of tangent line for tDH (differential DQS, DQS)  
32 of 45  
Rev. 1.1 December 2008  
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K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
VDDQ  
VIH(AC)min  
DQS  
V
IH(DC)min  
Note1  
VREF(DC)  
VIL(DC)max  
VIL(AC)max  
VSS  
tDH  
tDS  
tDS  
tDH  
VDDQ  
VIH(AC)min  
nominal  
line  
V
IH(DC)min  
dc to VREF  
region  
tangent  
line  
VREF(DC)  
tangent  
line  
dc to VREF  
region  
nominal  
line  
VIL(DC)max  
VIL(AC)max  
VSS  
TF  
TR  
tangent line [ VREF(DC) - VIL(DC)max ]  
Hold Slew Rate  
=
Rising Signal  
TR  
tangent line [ VIH(DC)min - VREF(DC) ]  
Hold Slew Rate  
=
Falling Signal  
TF  
Note : DQS signal must be monotonic between VIL(DC)max and VIH(DC)min.  
Figure 12 - IIIustration of tangent line for tDH (single-ended DQS)  
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DDR2 SDRAM  
9. tIS and tIH (input setup and hold) derating  
Table 4 - Derating values for DDR2-400, DDR2-533  
tIS, tIH Derating Values for DDR2-400, DDR2-533  
CK, CK Differential Slew Rate  
1.5 V/ns 1.0 V/ns  
2.0 V/ns  
Units  
Notes  
tIS  
+187  
+179  
+167  
+150  
+125  
+83  
tIH  
+94  
+89  
+83  
+75  
+45  
+21  
0
tIS  
+217  
+209  
+197  
+180  
+155  
+113  
+30  
tIH  
+124  
+119  
+113  
+105  
+75  
tIS  
+247  
+239  
+227  
+210  
+185  
+143  
+60  
tIH  
+154  
+149  
+143  
+135  
+105  
+81  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.25  
0.2  
0.15  
0.1  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+51  
0
+30  
+60  
-11  
-14  
+19  
+16  
+49  
+46  
Command/  
AddressSlew  
rate(V/ns)  
-25  
-31  
+5  
-1  
+35  
+29  
-43  
-54  
-13  
-24  
+17  
+6  
-67  
-83  
-37  
-53  
-7  
-23  
-110  
-175  
-285  
-350  
-525  
-800  
-1450  
-125  
-188  
-292  
-375  
-500  
-708  
-1125  
-80  
-95  
-50  
-65  
-145  
-255  
-320  
-495  
-770  
-1420  
-158  
-262  
-345  
-470  
-678  
-1095  
-115  
-225  
-290  
-465  
-740  
-1390  
-128  
-232  
-315  
-440  
-648  
-1065  
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DDR2 SDRAM  
Table 5 - Derating values for DDR2-667, DDR2-800  
tIS and tIH Derating Values for DDR2-667, DDR2-800  
CK, CK Differential Slew Rate  
1.5 V/ns 1.0 V/ns  
2.0 V/ns  
Units  
Notes  
tIS  
+150  
+143  
+133  
+120  
+100  
+67  
0
tIH  
+94  
+89  
+83  
+75  
+45  
+21  
0
tIS  
+180  
+173  
+163  
+150  
+130  
+97  
+30  
+25  
+17  
+8  
tIH  
+124  
+119  
+113  
+105  
+75  
tIS  
+210  
+203  
+193  
+180  
+160  
+127  
+60  
tIH  
+154  
+149  
+143  
+135  
+105  
+81  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.25  
0.2  
0.15  
0.1  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+51  
+30  
+60  
-5  
-14  
+16  
+55  
+46  
Command/  
Address Slew  
rate(V/ns)  
-13  
-31  
-1  
+47  
+29  
-22  
-54  
-24  
+38  
+6  
-34  
-83  
-4  
-53  
+26  
-23  
-60  
-125  
-188  
-292  
-375  
-500  
-708  
-1125  
-30  
-95  
0
-65  
-100  
-168  
-200  
-325  
-517  
-1000  
-70  
-158  
-262  
-345  
-470  
-678  
-1095  
-40  
-128  
-232  
-315  
-440  
-648  
-1065  
-138  
-170  
-295  
-487  
-970  
-108  
-140  
-265  
-457  
-940  
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value to the tIS  
and tIH derating value respectively. Example: tIS (total setup time) = tIS(base) + tIS  
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min.  
Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If  
the actual signal is always earlier than the nominal slew rate line between shaded ’VREF(DC) to ac region’, use nominal slew rate for derating value (see  
Figure 13). If the actual signal is later than the nominal slew rate line anywhere between shaded ’VREF(DC) to ac region’, the slew rate of a tangent line to  
the actual signal from the ac level to dc level is used for derating value (see Figure 14).  
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC).  
Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If  
the actual signal is always later than the nominal slewrate line between shaded ’dc to VREF(DC) region’, use nominal slew rate for derating value (see Fig-  
ure 15). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to VREF(DC) region’, the slew rate of a tangent line to  
the actual signal from the dc level to VREF(DC) level is used for derating value (see Figure 16).  
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(AC) at the time of the rising clock  
transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC).  
For slew rates in between the values listed in Tables 4 and 5, the derating values may obtained by linear interpolation.  
These values are typically not subject to production test. They are verified by design and characterization.  
35 of 45  
Rev. 1.1 December 2008  
K4T1G044QE  
K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
CK  
CK  
tIH  
tIH  
tIS  
tIS  
VDDQ  
VIH(AC)min  
VREF to ac  
region  
V
IH(DC)min  
nominal  
slew rate  
VREF(DC)  
nominal slew  
rate  
VIL(DC)max  
VREF to ac  
region  
VIL(AC)max  
VSS  
TF  
TR  
VREF(DC) - VIL(AC)max  
VIH(AC)min - VREF(DC)  
Setup Slew Rate  
Rising Signal  
Setup Slew Rate  
Falling Signal  
=
=
TF  
TR  
Figure 13 - IIIustration of nominal slew rate for tIS  
36 of 45  
Rev. 1.1 December 2008  
K4T1G044QE  
K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
CK  
CK  
tIH  
tIH  
tIS  
tIS  
VDDQ  
nominal  
line  
VIH(AC)min  
V
REF to ac  
region  
V
IH(DC)min  
tangent  
line  
VREF(DC)  
tangent  
line  
VIL(DC)max  
VREF to ac  
region  
VIL(AC)max  
nominal  
line  
TR  
VSS  
tangent line[VIH(AC)min - VREF(DC)]  
Setup Slew Rate  
=
Rising Signal  
TR  
TF  
tangent line[VREF(DC) - VIL(AC)max]  
Setup Slew Rate  
Falling Signal  
=
TF  
Figure 14 - IIIustration of tangent line for tIS  
37 of 45  
Rev. 1.1 December 2008  
K4T1G044QE  
K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
CK  
CK  
tIH  
tIH  
tIS  
tIS  
VDDQ  
VIH(AC)min  
V
IH(DC)min  
dc to VREF  
region  
nominal  
slew rate  
VREF(DC)  
nominal  
dc to VREF  
region  
slew rate  
VIL(DC)max  
VIL(AC)max  
VSS  
TF  
TR  
Hold Slew Rate  
VREF(DC) - VIL(DC)max  
Hold Slew Rate  
Rising Signal  
VIH(DC)min - VREF(DC)  
=
=
TR  
Falling Signal  
TF  
Figure 15 - IIIustration of nominal slew rate for tIH  
38 of 45  
Rev. 1.1 December 2008  
K4T1G044QE  
K4T1G084QE  
K4T1G164QE  
DDR2 SDRAM  
CK  
CK  
tIH  
tIH  
tIS  
tIS  
VDDQ  
VIH(AC)min  
nominal  
line  
V
IH(DC)min  
dc to VREF  
region  
tangent  
line  
VREF(DC)  
tangent  
line  
dc to VREF  
region  
nominal  
line  
VIL(DC)max  
VIL(AC)max  
VSS  
TF  
TR  
tangent line [ VREF(DC) - VIL(DC)max ]  
Hold Slew Rate  
Rising Signal  
=
TR  
tangent line [ VIH(DC)min - VREF(DC)]  
TF  
Hold Slew Rate  
=
Falling Signal  
Figure 16 - IIIustration of tangent line for tIH  
39 of 45  
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DDR2 SDRAM  
10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance  
(bus turnaround) will degrade accordingly.  
11. MIN ( tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as provided to the device (i.e. this value can be  
greater than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less the half period jitter ( tJIT(HP))  
of the clock source, and less the half period jitter due to crosstalk ( tJIT(crosstalk)) into the clock traces.  
12. tQH = tHP - tQHS, where :  
tHP = minimum half clock period for any given cycle and is defined by clock HIGH or clock LOW (tCH, tCL).  
tQHS accounts for:  
1) The pulse duration distortion of on-chip clock circuits; and  
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due  
to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers.  
13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate  
mismatch between DQS/ DQS and associated DQ in any given cycle.  
14. tDAL = WR + RU{ tRP[ns] / tCK[ns] }, where RU stands for round up.  
WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer.  
tCK refers to the application clock period.  
Example: For DDR533 at tCK = 3.75ns with WR programmed to 4 clocks.  
tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.  
15. The clock frequency is allowed to change during self refresh mode or precharge power-down mode.  
16. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resis-  
tance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is 10 ns (= 2 x 5 ns) after  
the clock edge that registered a first ODT HIGH if tCK = 5 ns. For DDR2-667/800, tAOND is 2 clock cycles after the clock edge that registered a first  
ODT HIGH counting the actual input clock edges.  
17. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are mea-  
sured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is 12.5 ns (= 2.5 x 5 ns) after the clock edge that regis-  
tered a first ODT LOW if tCK = 5 ns. For DDR2-667/800, if tCK(avg) = 3 ns is assumed, tAOFD is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock  
edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges.  
18. tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which  
specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . Figure 17 shows a method to calculate the point when device is no  
longer driving (tHZ), or beginsdriving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as  
long as the calculation is consistent. tLZ(DQ) refers to tLZ of the DQS and tLZ(DQS) refers to tLZ of the (U/L/R)DQS and (U/L/R)DQS each treated as  
single-ended signal.  
19. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST),  
or begins driving (tRPRE). Figure 17 shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving  
(tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent.  
VOH + x mV  
VOH + 2x mV  
VTT + 2x mV  
VTT + x mV  
tLZ  
tHZ  
tRPRE begin point  
tRPST end point  
V
V
OL + 2x mV  
OL + x mV  
V
TT - x mV  
T2  
T1  
T2  
VTT - 2x mV  
T1  
tHZ,tRPST end point = 2*T1-T2  
tLZ,tRPRE begin point = 2*T1-T2  
Figure 17 - Method for calculating transitions and endpoints  
40 of 45  
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DDR2 SDRAM  
20. Input waveform timing tDS with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(AC) level to the differential  
data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(AC) level to the differential data strobe crosspoint for a falling signal applied  
to the device under test. DQS, DQS signals must be monotonic between VIL(DC)max and VIH(DC)min. See Figure 18.  
21. Input waveform timing tDH with differential data strobe enabled MR[bit10]=0, is referenced from the differential data strobe crosspoint to the input signal crossing  
at the VIH(DC) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL(DC) level for a rising signal applied to  
the device under test. DQS, DQS signals must be monotonic between VIL(DC)max and VIH(DC)min. See Figure 18.  
DQS  
DQS  
tDH  
tDH  
tDS  
tDS  
VDDQ  
VIH(AC)min  
VIH(DC)min  
VREF(DC)  
VIL(DC)max  
VIL(AC)max  
VSS  
Figure 18 - Differential input waveform timing - tDS and tDH  
22. Input waveform timing is referenced from the input signal crossing at the VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device  
under test. See Figure 19.  
23. Input waveform timing is referenced from the input signal crossing at the VIL(DC) level for a rising signal and VIH(DC) for a falling signal applied to the device  
under test. See Figure 19.  
CK  
CK  
tIH  
tIH  
tIS  
tIS  
VDDQ  
VIH(AC)min  
VIH(DC)min  
VREF(DC)  
VIL(DC)max  
VIL(AC)max  
VSS  
Figure 19 - Differential input waveform timing - tIS and tIH  
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24. tWTR is at lease two clocks (2 x tCK or 2 x nCK) independent of operation frequency.  
25. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(AC) level to the  
single-ended data strobe crossing VIH/L(DC) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(AC) level to  
the single-ended data strobe crossing VIH/L(DC) at the start of its transition for a falling signal applied to the device under test. The DQS signal must  
be monotonic between VIL(DC)max and VIH(DC)min.  
26. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(DC) level to the  
single-ended data strobe crossing VIH/L(AC) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(DC) level to the  
single-ended data strobe crossing VIH/L(AC) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be  
monotonic between VIL(DC)max and VIH(DC)min.  
27. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire  
time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period  
of tIS + 2 x tCK + tIH.  
28. If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.  
29. These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respec-  
tive clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup  
and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is  
present or not.  
30. These parameters are measured from a data strobe signal ((L/U/R)DQS/DQS) crossing to its respective clock signal (CK/CK) crossing. The spec val-  
ues are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these  
parameters should be met whether clock jitter is present or not.  
31. These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/  
R)DQS/DQS) crossing.  
32. For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK(avg)}, which is in clock  
cycles, assuming all input clock jitter specifications are satisfied.  
For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means:  
For DDR2-667 5-5-5, of which tRP = 15ns, the device will support tnRP = RU{tRP / tCK(avg)} = 5, i.e. as long as the input clock jitter specifications  
are met, Precharge command at Tm and Active command at Tm+5 is valid even if (Tm+5 - Tm) is less than 15ns due to input clock jitter.  
33. tDAL [nCK] = WR [nCK] + tnRP [nCK] = WR + RU {tRP [ps] / tCK(avg) [ps] }, where WR is the value programmed in the mode register set.  
34. New units, ’tCK(avg)’ and ’nCK’, are introduced in DDR2-667 and DDR2-800. Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under  
operation. Unit ’nCK’ represents one clock cycle of the input clock, counting the actual clock edges.  
Note that in DDR2-400 and DDR2-533, ’tCK’ is used for both concepts.  
ex) tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm+2, even if (Tm+2 - Tm) is 2 x  
tCK(avg) + tERR(2per),min.  
35. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec parameters' and these  
parameters apply to DDR2-667 and DDR2-800 only. The jitter specified is a random jitter meeting a Gaussian distribution.  
DDR2-667  
Min  
DDR2-800  
Parameter  
Symbol  
units  
Notes  
Max  
125  
100  
250  
200  
175  
225  
250  
250  
350  
450  
125  
Min  
-100  
-80  
Max  
100  
80  
Clock period jitter  
tJIT(per)  
tJIT(per,lck)  
tJIT(cc)  
-125  
-100  
-250  
-200  
-175  
-225  
-250  
-250  
-350  
-450  
-125  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
35  
35  
35  
35  
35  
35  
35  
35  
35  
35  
35  
Clock period jitter during DLL locking period  
Cycle to cycle clock period jitter  
-200  
-160  
-150  
-175  
-200  
-200  
-300  
-450  
-100  
200  
160  
150  
175  
200  
200  
300  
450  
100  
Cycle to cycle clock period jitter during DLL locking period  
Cumulative error across 2 cycles  
tJIT(cc,lck)  
tERR(2per)  
tERR(3per)  
tERR(4per)  
tERR(5per)  
tERR(6-10per)  
tERR(11-50per)  
tJIT(duty)  
Cumulative error across 3 cycles  
Cumulative error across 4 cycles  
Cumulative error across 5 cycles  
Cumulative error across n cycles, n = 6 ... 10, inclusive  
Cumulative error across n cycles, n = 11 ... 50, inclusive  
Duty cycle jitter  
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Definitions :  
- tCK(avg)  
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window.  
N
/N  
tCK(avg) =  
where  
tCKj  
j = 1  
N = 200  
- tCH(avg) and tCL(avg)  
tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.  
N
/(N x tCK(avg))  
tCH(avg) =  
where  
tCHj  
j = 1  
N = 200  
tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.  
N
/(N x tCK(avg))  
tCL(avg) =  
where  
tCLj  
j = 1  
N = 200  
- tJIT(duty)  
tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH(avg). tCL jitter is the larg-  
est deviation of any single tCL from tCL(avg).  
tJIT(duty) = Min/max of {tJIT(CH), tJIT(CL)}  
where,  
tJIT(CH) = {tCHi- tCH(avg) where i=1 to 200}  
tJIT(CL) = {tCLi- tCL(avg) where i=1 to 200}  
- tJIT(per), tJIT(per,lck)  
tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg).  
tJIT(per) = Min/max of {tCKi- tCK(avg) where i=1 to 200}  
tJIT(per) defines the single period jitter when the DLL is already locked.  
tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.  
tJIT(per) and tJIT(per,lck) are not guaranteed through final production testing.  
- tJIT(cc), tJIT(cc,lck)  
tJIT(cc) is defined as the difference in clock period between two consecutive clock cycles : tJIT(cc) = Max of |tCKi+1 - tCKi|  
tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.  
tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.  
tJIT(cc) and tJIT(cc,lck) are not guaranteed through final production testing.  
- tERR(2per), tERR (3per), tERR (4per), tERR (5per), tERR (6-10per) and tERR (11-50per)  
tERR is defined as the cumulative error across multiple consecutive cycles from tCK(avg).  
i + n - 1  
- n x tCK(avg)  
tERR(nper) =  
tCKj  
j = 1  
n = 2  
for tERR(2per)  
n = 3  
n = 4  
n = 5  
for tERR(3per)  
for tERR(4per)  
for tERR(5per)  
for tERR(6-10per)  
where  
6 n 10  
11 n 50 for tERR(11-50per)  
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36. These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the  
absolute instantaneous timing holds at all times. (Min and max of SPEC values are to be used for calculations in the table below.)  
Parameter  
Symbol  
Min  
Max  
Units  
Absolute clock Period  
tCK(abs)  
tCK(avg)min + tJIT(per)min  
tCK(avg)max + tJIT(per)max  
ps  
tCH(avg)min x tCK(avg)min +  
tJIT(duty)min  
tCH(avg)max x tCK(avg)max +  
tJIT(duty)max  
Absolute clock HIGH pulse width  
Absolute clock LOW pulse width  
tCH(abs)  
tCL(abs)  
ps  
ps  
tCL(avg)min x tCK(avg)min +  
tJIT(duty)min  
tCL(avg)max x tCK(avg)max +  
tJIT(duty)max  
Example: For DDR2-667, tCH(abs),min = ( 0.48 x 3000 ps ) - 125 ps = 1315 ps  
37. tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used  
in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation;  
tHP = Min ( tCH(abs), tCL(abs) ),  
where,  
tCH(abs) is the minimum of the actual instantaneous clock HIGH time;  
tCL(abs) is the minimum of the actual instantaneous clock LOW time;  
38. tQHS accounts for:  
1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and  
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of  
each other, due to data pin skew, output pattern effects, and p-channel to n-channel variation of the output drivers  
39. tQH = tHP - tQHS, where:  
tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column.  
{The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}  
Examples:  
1) If the system provides tHP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975 ps minimum.  
2) If the system provides tHP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 ps minimum.  
40. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output derat-  
ings are relative to the SDRAM input clock.)  
For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per)min = - 272 ps and tERR(6-10per)max = + 293 ps, then tDQSCK-  
min(derated) = tDQSCKmin - tERR(6-10per)max = - 400 ps - 293 ps = - 693 ps and tDQSCKmax(derated) = tDQSCKmax - tERR(6-10per)min = 400  
ps + 272 ps = + 672 ps. Similarly, tLZ(DQ) for DDR2-667 derates to tLZ(DQ)min(derated) = - 900 ps - 293 ps = - 1193 ps and tLZ(DQ)max(derated) =  
450 ps + 272 ps = + 722 ps.  
41. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per) of the input clock. (output deratings are  
relative to the SDRAM input clock.)  
For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(per)min = - 72 ps and tJIT(per)max = + 93 ps, then tRPREmin(derated) =  
tRPREmin + tJIT(per)min = 0.9 x tCK(avg) - 72 ps = + 2178 ps and tRPREmax(derated) = tRPREmax + tJIT(per)max = 1.1 x tCK(avg) + 93 ps = +  
2843 ps.  
42. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(duty) of the input clock. (output deratings are  
relative to the SDRAM input clock.)  
For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(duty),min = - 72 ps and tJIT(duty)max = + 93 ps, then tRPSTmin(derated) =  
tRPSTmin + tJIT(duty)min = 0.4 x tCK(avg) - 72 ps = + 928 ps and tRPSTmax(derated) = tRPSTmax + tJIT(duty)max = 0.6 x tCK(avg) + 93 ps = +  
1592 ps.  
43. When the device is operated with input clock jitter, this parameter needs to be derated by { - tJIT(duty)max - tERR(6-10per)max } and { - tJIT(duty)min  
- tERR(6-10per)min } of the actual input clock. (output deratings are relative to the SDRAM input clock.)  
For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per)min = - 272 ps, tERR(6- 10per)max = + 293 ps, tJIT(duty)min = - 106  
ps and tJIT(duty)max = + 94 ps, then tAOFmin(derated) = tAOFmin + { - tJIT(duty)max - tERR(6-10per)max } = - 450 ps + { - 94 ps - 293 ps} = - 837  
ps and tAOFmax(derated) = tAOFmax + { - tJIT(duty)min - tERR(6-10per)min } = 1050 ps + { 106 ps + 272 ps } = + 1428 ps.  
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44. For tAOFD of DDR2-400/533, the 1/2 clock of tCK in the 2.5 x tCK assumes a tCH, input clock HIGH pulse width of 0.5 relative to tCK. tAOF,min and  
tAOF,max should each be derated by the same amount as the actual amount of tCH offset present at the DRAM input with respect to 0.5.  
For example, if an input clock has a worst case tCH of 0.45, the tAOFmin should be derated by subtracting 0.05 x tCK from it, whereas if an input clock  
has a worst case tCH of 0.55, the tAOFmax should be derated by adding 0.05 x tCK to it. Therefore, we have;  
tAOFmin(derated) = tAC,min - [0.5 - Min(0.5, tCHmin)] x tCK  
tAOFmax(derated) = tAC,max + 0.6 + [Max(0.5, tCHmax) - 0.5] x tCK  
or  
tAOFmin(derated) = Min(tACmin, tACmin - [0.5 - tCHmin] x tCK)  
tAOFmax(derated) = 0.6 + Max(tACmax, tACmax + [tCHmax - 0.5] x tCK)  
where tCHmin and tCHmax are the minimum and maximum of tCH actually measured at the DRAM input balls.  
45. For tAOFD of DDR2-667/800, the 1/2 clock of nCK in the 2.5 x nCK assumes a tCH(avg), average input clock HIGH pulse width of 0.5 relative to  
tCK(avg). tAOFmin and tAOFmax should each be derated by the same amount as the actual amount of tCH(avg) offset present at the DRAM input  
with respect to 0.5.  
For example, if an input clock has a worst case tCH(avg) of 0.48, the tAOFmin should be derated by subtracting 0.02 x tCK(avg) from it, whereas if an  
input clock has a worst case tCH(avg) of 0.52, the tAOFmax should be derated by adding 0.02 x tCK(avg) to it. Therefore, we have;  
tAOFmin(derated) = tACmin - [0.5 - Min(0.5, tCH(avg)min)] x tCK(avg)  
tAOFmax(derated) = tACmax + 0.6 + [Max(0.5, tCH(avg)max) - 0.5] x tCK(avg)  
tAOFmin(derated) = Min(tACmin, tACmin - [0.5 - tCH(avg)min] x tCK(avg))  
tAOFmax(derated) = 0.6 + Max(tACmax, tACmax + [tCH(avg)max - 0.5] x tCK(avg))  
where tCH(avg),min and tCH(avg),max are the minimum and maximum of tCH(avg) actually measured at the DRAM input balls.  
Note that these deratings are in addition to the tAOF derating per input clock jitter, i.e. tJIT(duty) and tERR(6-10per). However tAC values used in the  
equations shown above are from the timing parameter table and are not derated. Thus the final derated values for tAOF are;  
tAOFmin(derated_final) = tAOFmin(derated) + { - tJIT(duty)max - tERR(6-10per)max }  
tAOFmax(derated_final) = tAOFmax(derated) + { - tJIT(duty)min - tERR(6-10per)min }  
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