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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • K4X1G323PE-8GC6 现货库存
  • 数量69850 
  • 厂家SAMSUNG 
  • 封装TO-220F 
  • 批号22+ 
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  • 深圳市集创讯科技有限公司

     该会员已使用本站5年以上
  • K4X1G323PE-8GC6 现货库存
  • 数量12500 
  • 厂家SAMSUNG/三星 
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  • 批号24+ 
  • 原装进口正品现货,假一罚十价格优势
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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • K4X1G323PE-8GC6 现货库存
  • 数量6980 
  • 厂家SAMSUNG 
  • 封装BGA 
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  • 深圳市美思瑞电子科技有限公司

     该会员已使用本站12年以上
  • K4X1G323PE-8GC6 现货库存
  • 数量9217 
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  • 深圳市创德丰电子有限公司

     该会员已使用本站15年以上
  • K4X1G323PE-8GC6 现货库存
  • 数量12 
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  • 北京元坤伟业科技有限公司

     该会员已使用本站17年以上
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  • 数量5000 
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  • 深圳市昌和盛利电子有限公司

     该会员已使用本站11年以上
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  • 数量12335 
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  • 深圳市科庆电子有限公司

     该会员已使用本站16年以上
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  • 数量18092 
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  • 深圳市捷立辉科技有限公司

     该会员已使用本站10年以上
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  • 数量69896 
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
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  • 数量1120 
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  • 深圳市亿智腾科技有限公司

     该会员已使用本站8年以上
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
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  • 数量13050 
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     该会员已使用本站16年以上
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     该会员已使用本站13年以上
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  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
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  • 深圳市恒益昌科技有限公司

     该会员已使用本站6年以上
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  • 数量5680 
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站15年以上
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  • 数量12500 
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  • 首天国际(深圳)科技有限公司

     该会员已使用本站16年以上
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  • 数量128000 
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  • 深圳市赛尔通科技有限公司

     该会员已使用本站12年以上
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  • 数量32560 
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  • 深圳市卓越微芯电子有限公司

     该会员已使用本站12年以上
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  • 数量5500 
  • 厂家Samsung 
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  • 百分百原装正品 真实公司现货库存 本公司只做原装 可开13%增值税发票,支持样品,欢迎来电咨询!
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  • 深圳市瑞天芯科技有限公司

     该会员已使用本站7年以上
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  • 数量20000 
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  • 上海磐岳电子有限公司

     该会员已使用本站11年以上
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  • 数量5800 
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  • 深圳市中利达电子科技有限公司

     该会员已使用本站11年以上
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  • 数量10000 
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  • 深圳市集创讯科技有限公司

     该会员已使用本站5年以上
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  • 数量25000 
  • 厂家SAMSUNG/三星 
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  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
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  • 数量4321 
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  • 深圳市宏诺德电子科技有限公司

     该会员已使用本站8年以上
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  • 数量68000 
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     该会员已使用本站14年以上
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     该会员已使用本站15年以上
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     该会员已使用本站15年以上
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     该会员已使用本站12年以上
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  • 批号1043+ 
  • 一定原装房间现货
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  • K4X1G323PE-8GC6
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产品型号K4X1G323PE-8GC6的概述

K4X1G323PE-8GC6芯片概述 K4X1G323PE-8GC6是一款高性能的DDR3 SDRAM内存芯片,主要由韩国的Samsung Electronics公司生产。该芯片凭借其出色的性能、低功耗和高密度存储,广泛应用于各类计算机和移动设备中。DDR3(Double Data Rate 3)内存是当前主流的内存技术之一,相较于前代DDR2内存,它提供了更高的带宽和更快的数据传输速度。 K4X1G323PE-8GC6详细参数 K4X1G323PE-8GC6是一款1GB(1G x 32)容量的芯片,其主要规格如下: - 容量:1GB - 存储结构:x32 - 数据传输率:最大可达1600 Mbps - 工作电压:1.5V - 封装类型:FBGA - 引脚数量:78引脚 - 工作温度范围:-40 to +85°C - 制造工艺:采用先进的58nm技术 - 内存速度等级:DDR3-16...

产品型号K4X51163PC的Datasheet PDF文件预览

K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
32M x16 Mobile-DDR SDRAM  
FEATURES  
• 1.8V power supply, 1.8V I/O power  
• Double-data-rate architecture; two data transfers per clock cycle  
• Bidirectional data strobe(DQS)  
• Four banks operation  
• 1 /CS  
• 1 CKE  
• Differential clock inputs(CK and CK)  
MRS cycle with address key programs  
- CAS Latency ( 2, 3 )  
- Burst Length ( 2, 4, 8, 16 )  
- Burst Type (Sequential & Interleave)  
- Partial Self Refresh Type ( Full, 1/2, 1/4 Array )  
- Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 )  
• Internal Temperature Compensated Self Refresh  
• Deep Power Down Mode  
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK).  
• Data I/O transactions on both edges of data strobe, DM for masking.  
• Edge aligned data output, center aligned data input.  
• No DLL; CK to DQS is not synchronized.  
• LDM, UDM for write masking only.  
Auto refresh duty cycle  
- 7.8us for -25 to 85 °C  
Operating Frequency  
DDR266  
DDR222  
66Mhz  
Speed @CL2*1  
Speed @CL3*1  
83Mhz  
133Mhz  
111Mhz  
Note :  
1. CAS Latency  
Address configuration  
Organization  
Bank  
BA0,BA1  
Row  
Column  
32M x16  
A0 - A12  
A0 - A9  
- DM is internally loaded to match DQ and DQS identically.  
Ordering Information  
Part No.  
Max Freq.  
Interface  
LVCMOS  
Package  
K4X51163PC-L(F)E/GC3  
K4X51163PC-L(F)E/GCA  
133MHz(CL=3),83MHz(CL=2)  
111MHz(CL=3),66MHz(CL=2)  
60FBGA  
Pb (Pb Free)  
- L(F)E : 60FBGA Pb(Pb Free), Normal Power, Extended Temperature(-25 °C ~ 85 °C)  
- L(F)G : 60FBGA Pb(Pb Free), Low Power, Extended Temperature(-25 °C ~ 85 °C)  
- C3/CA : 133MHz(CL=3) / 111MHz(CL=3)  
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.  
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,  
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PRO-  
VIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.  
1. For updates or additional information about Samsung products, contact your nearest Samsung office.  
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could  
result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or pro-  
visions may apply.  
February 2006  
K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
FUNCTIONAL BLOCK DIAGRAM  
LWE  
LDM  
16  
CK, CK  
Data Input Register  
Serial to parallel  
Bank Select  
32  
4Mx32  
4Mx32  
4Mx32  
4Mx32  
32  
16  
X16  
DQi  
CK, CK  
ADD  
Column Decoder  
Latency & Burst Length  
Data Strobe  
Programming Register  
LWCBR  
LCKE  
LRAS LCBR  
LWE  
LCAS  
LDM  
Timing Register  
DM Input Register  
CK, CK  
CKE  
CS  
RAS  
CAS  
WE  
DM  
February 2006  
K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
Package Dimension and Pin Configuration  
*2  
*1  
< Top View  
>
< Bottom View  
>
E
1
60Ball(6x9) FBGA  
9
8
7
6
5
4
3
2
1
1
2
3
7
VDDQ  
DQ1  
DQ3  
DQ5  
DQ7  
N.C.  
WE  
8
9
A
B
C
D
E
F
A
B
C
D
E
F
VSS  
VDDQ  
VSSQ  
VDDQ  
VSSQ  
VSS  
CKE  
A9  
DQ15  
VSSQ  
DQ0  
DQ2  
DQ4  
DQ6  
LDQS  
LDM  
CAS  
BA0  
A0  
VDD  
VSSQ  
VDDQ  
VSSQ  
VDDQ  
VDD  
RAS  
BA1  
A1  
DQ13 DQ14  
DQ11 DQ12  
DQ9  
UDQS  
UDM  
CK  
DQ10  
DQ8  
N.C.  
CK  
G
H
J
G
H
J
A11  
A12  
A8  
CS  
A6  
A7  
A10/AP  
A2  
K
VSS  
A4  
A5  
A3  
VDD  
K
E
Ball Name  
CK, CK  
CS  
Ball Function  
System Differential Clock  
Chip Select  
*2: Top View  
CKE  
Clock Enable  
A0 ~ A12  
BA0 ~ BA1  
RAS  
Address  
Bank Select Address  
Row Address Strobe  
Column Address Strobe  
Write Enable  
A
A1  
CAS  
z
b
WE  
*1: Bottom View  
L(U)DM  
L(U)DQS  
DQ0 ~ 15  
VDD/VSS  
VDDQ/VSSQ  
Data Input Mask  
Data Strobe  
*2  
Data Input/Output  
Power Supply/Ground  
Data Output Power/Ground  
< Top View >  
#A1 Ball Origin Indicator  
[Unit:mm]  
Symbol  
Min  
Typ  
-
Max  
1.0  
-
A
-
A
0.25  
-
1
E
11.4  
11.5  
6.4  
10.0  
7.2  
0.80  
0.50  
-
11.6  
-
E
-
1
D
9.9  
10.1  
-
D
-
1
e
b
z
-
0.45  
-
-
0.55  
0.10  
February 2006  
K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
Input/Output Function Description  
SYMBOL  
CK, CK  
TYPE  
Input  
DESCRIPTION  
Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the  
crossing of the positive edge of CK and negative edge of CK. Internal clock signals are derived from  
CK/CK.  
CKE  
Input  
Input  
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input  
buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF  
REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is  
synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input  
buffers, excluding CK, CK and CKE , are disabled during power-down and self refresh mode which are  
contrived for low standby power consumption.  
CS  
Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder.  
All commands are masked when CS is registered HIGH. CS provides for external bank selection on  
systems with multiple banks. CS is considered part of the command code.  
RAS, CAS, WE Input  
Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.  
LDM,UDM  
Input  
Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled  
HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. DM  
pins include dummy loading internally, to matches the DQ and DQS loading. For the x16, LDM  
corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15.  
BA0, BA1  
A [n : 0]  
Input  
Input  
Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE  
command is being applied.  
Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO  
PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the  
respective bank. A10 sampled during a PRECHARGE command  
determines whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only  
one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the  
op-code during a MODE REGISTER SET command. BA0 and BA1 determines which mode register  
( mode register or extended mode register ) is loaded during the MODE REGISTER SET command.  
DQ  
I/O  
I/O  
Data Input/Output : Data bus  
LDQS,UDQS  
Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in write  
data. it is used to fetch write data. For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS  
corresponds to the data on DQ8-DQ15.  
NC  
-
No Connect : No internal electrical connection is present.  
DQ Power Supply : 1.7V to 1.95V.  
DQ Ground.  
VDDQ  
VSSQ  
VDD  
VSS  
Supply  
Supply  
Supply  
Supply  
Power Supply : 1.7V to 1.95V.  
Ground.  
February 2006  
K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
Functional Description  
DEEP  
POWER  
DOWN  
CKEH  
POWER  
ON  
POWER  
APPLIED  
PARTIAL  
SELF  
REFRESH  
SELF  
REFRESH  
DEEP  
POWER  
DOWN  
PRECHARGE  
ALL BANKS  
REFS  
REFSX  
REFA  
IDLE  
ALL BANKS  
PRECHARGED  
MRS  
AUTO  
EMRS  
MRS  
REFRESH  
CKEL  
CKEH  
ACT  
POWER  
DOWN  
CKEH  
POWER  
DOWN  
ROW  
BURST STOP  
ACTIVE  
CKEL  
WRITE  
READ  
WRITEA  
READA  
READ  
WRITE  
READ  
WRITEA  
READA  
READA  
PRE  
PRE  
WRITEA  
READA  
PRE  
PRE  
PRECHARGE  
PREALL  
Automatic Sequence  
Command Sequence  
Figure.1 State diagram  
February 2006  
K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
Mode Register Definition  
Mode Register Set(MRS)  
The mode register is designed to support the various operating modes of DDR SDRAM. It includes Cas latency, addressing mode,  
burst length, test mode and vendor specific options to make DDR SDRAM useful for variety of applications. The default value of the  
mode register is not defined, therefore the mode register must be written in the power up sequence of DDR SDRAM. The mode reg-  
ister is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with CKE already high prior to  
writing into the mode register). The states of address pins A0 ~ A12 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE  
going low are written in the mode register. Two clock cycles are required to complete the write operation in the mode register. Even if  
the power-up sequence is finished and some read or write operation is executed afterward, the mode register contents can be  
changed with the same command and two clock cycles. This command must be issued only when all banks are in the idle state. If  
mode register is changed, extended mode register automatically is reset and come into default state. So extended mode register  
must be set again. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2,  
addressing mode uses A3, Cas latency(read latency from column address) uses A4 ~ A6, A7 ~ A12 is used for test mode. BA0 and  
BA1 must be set to low for proper MRS operation.  
Address Bus  
BA1  
BA0  
A12 ~ A10/AP  
A9  
0
A8  
0
A7  
0
A6  
A5  
A4  
A3  
BT  
A2  
A1  
A0  
Mode Register  
0
0
RFU*  
CAS Latency  
Burst Length  
A3  
Burst Type  
Sequential  
Interleave  
0
1
A6  
0
A5  
0
A4  
0
CAS Latency  
Reserved  
Reserved  
2
A2  
0
A1  
0
A0  
Burst Length  
0
1
0
1
0
1
0
1
Reserved  
0
0
1
0
0
2
0
1
0
0
1
4
0
1
1
3
0
1
8
1
0
0
Reserved  
Reserved  
Reserved  
Reserved  
1
0
16  
1
0
1
1
0
Reserved  
Reserved  
Reserved  
1
1
0
1
1
1
1
1
1
1
Figure.2 Mode Register Set  
Note :  
RFU(Reserved for future use) should stay "0" during MRS cycle  
February 2006  
K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
Burst address ordering for burst length  
Starting  
Burst  
Address  
Sequential Mode  
Interleave Mode  
Length  
(A3, A2, A1, A0)  
xxx0  
xxx1  
xx00  
xx01  
xx10  
xx11  
x000  
x001  
x010  
x011  
x100  
x101  
x110  
x111  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
0, 1  
0, 1  
2
1, 0  
1, 0  
0, 1, 2, 3  
0, 1, 2, 3  
1, 2, 3, 0  
1, 0, 3, 2  
4
2, 3, 0, 1  
2, 3, 0, 1  
3, 0, 1, 2  
3, 2, 1, 0  
0, 1, 2, 3, 4, 5, 6, 7  
0, 1, 2, 3, 4, 5, 6, 7  
1, 2, 3, 4, 5, 6, 7, 0  
1, 0, 3, 2, 5, 4, 7, 6  
2, 3, 4, 5, 6, 7, 0, 1  
2, 3, 0, 1, 6, 7, 4, 5  
3, 4, 5, 6, 7, 0, 1, 2  
3, 2, 1, 0, 7, 6, 5, 4  
8
4, 5, 6, 7, 0, 1, 2, 3  
4, 5, 6, 7, 0, 1, 2, 3  
5, 6, 7, 0, 1, 2, 3, 4  
5, 4, 7, 6, 1, 0, 3, 2  
6, 7, 0, 1, 2, 3, 4, 5  
6, 7, 4, 5, 2, 3, 0, 1  
7, 0, 1, 2, 3, 4, 5, 6  
7, 6, 5, 4, 3, 2, 1, 0  
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15  
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0  
2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1  
3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2  
4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3  
5, 6, 7,8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4  
6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5  
7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6  
8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7  
9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7, 8  
10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9  
11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10  
12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11  
13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,12  
14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13  
15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14  
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15  
1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11,10,13,12,15,14  
2, 3, 0, 1, 6, 7, 4, 5,10,11, 8, 9, 14,15,12,13  
3, 2, 1, 0, 7, 6, 5, 4,11,10, 9, 8, 15,14,13,12  
4, 5, 6, 7, 0, 1, 2, 3,12,13,14,15, 8, 9, 10,11  
5, 4, 7, 6, 1, 0, 3, 2,13,12,15,14, 9, 8,11,10  
6, 7, 4, 5, 2, 3, 0, 1,14,15,12,13,10,11, 8, 9  
7, 6, 5, 4, 3, 2, 1, 0, 15,14,13,12,11,10, 9, 8  
8, 9,10,11,12,13,14,15, 0, 1, 2, 3, 4, 5, 6, 7  
9, 8, 11,10,13,12,15,14,1, 0, 3, 2, 5, 4, 7, 6  
10,11, 8, 9, 14,15,12,13, 2, 3, 0, 1, 6, 7, 4, 5  
11,10, 9, 8, 15,14,13,12, 3, 2, 1, 0, 7, 6, 5, 4  
12,13,14,15, 8, 9, 10,11, 4, 5, 6, 7, 0, 1, 2, 3  
13,12,15,14, 9, 8,11,10, 5, 4, 7, 6, 1, 0, 3, 2  
14,15,12,13,10,11, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1  
15,14,13,12,11,10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0  
16  
February 2006  
K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
Extended Mode Register Set(EMRS)  
The extended mode register is designed to support partial array self refresh or driver strength control. EMRS cycle is not mandatory  
and the EMRS command needs to be issued only when either PASR or DS is used. The default state without EMRS command  
issued is half driver strength, and Full array refreshed. The extended mode register is written by asserting low on CS, RAS, CAS,  
WE and high on BA1 ,low on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the  
extended mode register). The state of address pins A0 ~ A12 in the same cycle as CS, RAS, CAS and WE going low is written in the  
extended mode register. Two clock cycles are required to complete the write operation in the extended mode register. Even if the  
power-up sequence is finished and some read or write operations is executed afterward, the mode register contents can be changed  
with the same command and two clock cycles. But this command must be issued only when all banks are in the idle state. A0 - A2  
are used for partial array self refresh and A5 - A6 are used for driver strength control. "High" on BA1 and"Low" on BA0 are used for  
EMRS. All the other address pins except A0,A1,A2,A5,A6, BA1, BA0 must be set to low for proper EMRS operation. Refer to the  
table for specific codes.  
Extended MRS for PASR(Partial Array Self Refresh) &  
DS(Driver Strength Control)  
Address Bus  
A12 ~ A10/AP  
BA1  
BA0  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
0
DS  
RFU*  
PASR  
Mode Register  
1
0
RFU*  
0
0
DS  
Internal TCSR  
PASR  
A6  
A5  
Driver Strength  
Self refresh cycle is controlled  
automatically by internal tem-  
perature sensor and control cir-  
cuit according to the three  
temperature ranges ; 45 °C and  
85 °C  
A2  
0
A1  
A0  
0
Refreshed Area  
0
0
1
1
0
1
0
1
Full  
1/2  
1/4  
1/8  
0
0
1
1
0
0
1
1
Full Array  
1/2 of Full Array  
1/4 of Full Array  
Reserved  
0
1
0
0
0
1
1
0
Reserved  
1
1
Reserved  
1
0
Reserved  
1
1
Reserved  
Figure.3 Extended Mode Register Set  
Note :  
RFU(Reserved for future use) should stay "0" during EMRS cycle  
February 2006  
K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
Internal Temperature Compensated Self Refresh (TCSR)  
Note :  
1. In order to save power consumption, Mobile DDR SDRAM includes the internal temperature sensor and control units to control the  
self refresh cycle automatically according to the three temperature ranges ; 45 °C and 85 °C.  
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.  
3. It has +/- 5 °C tolerance.  
Self Refresh Current (IDD6)  
Temperature Range  
- E  
1/2 Array  
270  
- G  
1/2 Array  
220  
Unit  
Full Array  
300  
1/4 Array  
255  
Full Array  
250  
1/4 Array  
205  
*3  
45 °C  
uA  
85 °C  
600  
500  
450  
500  
400  
350  
Partial Array Self Refresh (PASR)  
Note :  
1. In order to save power consumption, Mobile-DDR SDRAM includes PASR option.  
2. Mobile-DDR SDRAM supports three kinds of PASR in self refresh mode; Full array, 1/2 Array, 1/4 Array.  
BA1=0 BA1=0  
BA0=0 BA0=1  
BA1=0 BA1=0  
BA0=0 BA0=1  
BA1=0 BA1=0  
BA0=0 BA0=1  
BA1=1 BA1=1  
BA0=0 BA0=1  
BA1=1 BA1=1  
BA0=0 BA0=1  
BA1=1 BA1=1  
BA0=0 BA0=1  
- 1/4 Array  
- Full Array  
- 1/2 Array  
Partial Self Refresh Area  
Figure.4 EMRS code and TCSR , PASR  
February 2006  
K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
Absolute maximum ratings  
Parameter  
Symbol  
, V  
OUT  
Value  
Unit  
Voltage on any pin relative to V  
V
-0.5 ~ 2.7  
-0.5 ~ 2.7  
-0.5 ~ 2.7  
-55 ~ +150  
1.0  
V
SS  
IN  
Voltage on V supply relative to V  
V
DD  
V
V
DD  
SS  
Voltage on V  
supply relative to V  
V
DDQ  
DDQ  
SS  
Storage temperature  
Power dissipation  
Short circuit current  
T
°C  
W
STG  
P
D
I
50  
mA  
OS  
Note :  
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.  
Functional operation should be restricted to recommend operation condition.  
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.  
DC Operating Conditions  
Recommended operating conditions(Voltage referenced to VSS=0V, Tc = -25°C to 85°C)  
Parameter  
Supply voltage(for device with a nominal VDD of 1.8V)  
I/O Supply voltage  
Symbol  
VDD  
Min  
Max  
Unit  
V
Note  
1.7  
1.95  
1
VDDQ  
VIH(DC)  
VIL(DC)  
VOH(DC)  
VOL(DC)  
II  
1.7  
1.95  
V
1
Input logic high voltage  
0.7 x VDDQ  
VDDQ+0.3  
V
2
Input logic low voltage  
-0.3  
0.3 x VDDQ  
V
2
Output logic high voltage  
Output logic low voltage  
0.9 x VDDQ  
-
V
IOH = -0.1mA  
IOL = 0.1mA  
-
0.1 x VDDQ  
V
Input leakage current  
-2  
-5  
2
5
uA  
uA  
Output leakage current  
IOZ  
Note :  
1. Under all conditions, VDDQ must be less than or equal to VDD.  
2. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation.  
February 2006  
K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
DC CHARACTERISTICS  
Recommended operating conditions (Voltage referenced to VSS = 0V, Tc = -25 to 85°C)  
Parameter  
Symbol  
Test Condition  
DDR266 DDR222 Unit  
Operating Current  
(One Bank Active)  
tRC = tRCmin ; tCK = tCKmin ; CKE is HIGH; CS is HIGH between valid commands;  
address inputs are SWITCHING; data bus inputs are STABLE  
IDD0  
80  
70  
mA  
all banks idle, CKE is LOW; CS is HIGH, tCK = t CKmin ; address and control inputs are  
SWITCHING; data bus inputs are STABLE  
0.3  
0.3  
IDD2P  
Precharge Standby Current in  
power-down mode  
mA  
all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control  
inputs are SWITCHING; data bus inputs are STABLE  
IDD2PS  
IDD2N  
all banks idle, CKE is HIGH; CS is HIGH, tCK = t CKmin ;address and control inputs are  
SWITCHING; data bus inputs are STABLE  
12  
8
10  
7
Precharge Standby Current  
in non power-down mode  
mA  
mA  
all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control  
inputs are SWITCHING; data bus inputs are STABLE  
IDD2NS  
IDD3P  
one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin ;address and control inputs are  
SWITCHING; data bus inputs are STABLE  
6
3
Active Standby Current  
in power-down mode  
one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;address and control  
inputs are SWITCHING; data bus inputs are STABLE  
IDD3PS  
IDD3N  
one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin ;address and control inputs  
are SWITCHING; data bus inputs are STABLE  
25  
20  
20  
15  
Active Standby Current  
in non power-down mode  
(One Bank Active)  
mA  
mA  
one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;  
address and control inputs are SWITCHING; data bus inputs are STABLE  
IDD3NS  
one bank active; BL = 4; CL = 3; tCK = tCKmin ; continuous read bursts; I OUT = 0 mA  
address inputs are SWITCHING; 50% data change each burst transfer  
IDD4R  
IDD4W  
IDD5  
115  
100  
150  
95  
90  
Operating Current  
(Burst Mode)  
one bank active; BL = 4; tCK = tCKmin ; continuous write bursts;address inputs are  
SWITCHING; 50% data change each burst transfer  
tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is HIGH;address and control inputs  
are SWITCHING; data bus inputs are STABLE  
Refresh Current  
135  
mA  
1
85  
TCSR  
°C  
CKE is LOW; tCK = tCKmin ;  
45*  
Extended Mode Register set to all 0’s;  
address and control inputs are STABLE; data bus inputs  
are STABLE  
300  
600  
500  
450  
500  
400  
350  
Full Array  
270  
255  
250  
220  
205  
-E  
1/2 Array  
1/4 Array  
Full Array  
1/2 Array  
1/4 Array  
Self Refresh Current  
IDD6  
uA  
uA  
-G  
2
Deep Power Down Current  
10  
IDD8*  
Address and control inputs are STABLE; data bus inputs are STABLE  
Note :  
1. It has +/- 5°C tolerance.  
2. DPD(Deep Power Down) function is an optional feature, and it will be enabled upon request.  
Please contact Samsung for more information.  
3. IDD specifications are tested after the device is properly intialized.  
4. Input slew rate is 1V/ns.  
5. Definitions for IDD: LOW is defined as V IN 0.1 * VDDQ ;  
HIGH is defined as V IN 0.9 * VDDQ ;  
STABLE is defined as inputs stable at a HIGH or LOW level ;  
SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles ;  
- data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.  
February 2006  
K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
AC Operating Conditions & Timming Specification  
Max  
Parameter/Condition  
Symbol  
Min  
Unit  
Note  
Input High (Logic 1) Voltage, all inputs  
Input Low (Logic 0) Voltage, all inputs  
Input Crossing Point Voltage, CK and CK inputs  
VIH(AC)  
VIL(AC)  
VIX(AC)  
0.8 x VDDQ  
-0.3  
VDDQ+0.3  
0.2 x VDDQ  
0.6 x VDDQ  
V
V
V
1
1
2
0.4 x VDDQ  
Note :  
1. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation.  
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.  
February 2006  
K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
AC Timming Parameters & Specifications  
DDR266  
DDR222  
Parameter  
Symbol  
Unit  
Note  
Min  
Max  
Min  
Max  
CL=2  
CL=3  
12.0  
7.5  
15.0  
Clock cycle time  
tCK  
ns  
9.0  
Row cycle time  
tRC  
tRAS  
tRCD  
tRP  
67.5  
45  
81  
ns  
ns  
ns  
ns  
ns  
ns  
-
Row active time  
RAS to CAS delay  
Row precharge time  
70,000  
54  
70,000  
22.5  
22.5  
15  
27  
27  
Row active to Row active delay  
Write recovery time  
tRRD  
tWR  
15  
15  
15  
Last data in to Active delay  
Last data in to Read command  
Col. address to Col. address delay  
tDAL  
tCDLR  
tCCD  
2tCK+tRP  
1
2tCK+tRP  
2
3
1
1
tCK  
1
tCK  
Clock high level width  
Clock low level width  
tCH  
tCL  
0.45  
0.45  
2
0.55  
0.55  
8
0.45  
0.45  
2.5  
0.55  
0.55  
8
tCK  
tCK  
CL=2  
CL=3  
CL=2  
CL=3  
DQ Output data access time from CK/  
CK  
tAC  
ns  
2
6
2.5  
6
2
8
2.5  
8
DQS Output data access time from  
CK/CK  
tDQSCK  
tDQSQ  
tRPRE  
ns  
ns  
2
6
2.5  
6
Data strobe edge to ouput data edge  
Read Preamble  
0.6  
1.1  
1.1  
0.6  
1.25  
0.7  
1.1  
1.1  
0.6  
1.25  
CL=2  
CL=3  
0.5  
0.9  
0.4  
0.75  
0
0.5  
0.9  
0.4  
0.75  
0
tCK  
Read Postamble  
tRPST  
tDQSS  
tWPRES  
tWPREH  
tDQSH  
tDQSL  
tDSS  
tDSH  
tDSC  
tIS  
tCK  
tCK  
ns  
CK to valid DQS-in  
DQS-in setup time  
4
DQS-in hold time  
0.25  
0.4  
0.4  
0.2  
0.2  
0.9  
1.3  
1.3  
2.6  
0.8  
0.25  
0.4  
0.4  
0.2  
0.2  
0.9  
1.5  
1.5  
3.0  
1.1  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
ns  
DQS-in high level width  
0.6  
0.6  
0.6  
0.6  
DQS-in low level width  
DQS falling edge to CK setup time  
DQS falling edge hold time from CK  
DQS-in cycle time  
1.1  
1.1  
Address and Control Input setup time  
Address and Control Input hold time  
Address & Control input pulse width  
DQ & DM setup time to DQS  
DQ & DM hold time to DQS  
1
1
tIH  
ns  
tIPW  
1
tDS  
ns  
ns  
5,6  
tDH  
0.8  
1.1  
5,6  
DQ & DM input pulse width  
tDIPW  
tLZ  
1.8  
1.0  
2.4  
1.0  
ns  
ns  
DQ & DQS low-impedence time from CK/CK  
DQ & DQS high-impedence time from CK/CK  
DQS write postamble time  
tHZ  
6.0  
0.6  
7.0  
0.6  
ns  
tWPST  
tWPRE  
0.4  
0.4  
tCK  
tCK  
DQS write preamble time  
0.25  
0.25  
February 2006  
K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
DDR222  
DDR266  
Max  
Parameter  
Symbol  
Unit  
Note  
Min  
Min  
Max  
Refresh interval time  
tREF  
64  
64  
ms  
tCK  
ns  
Mode register set cycle time  
Power down exit time  
tMRD  
2
2
tPDEX 1*tCK +tIS  
1*tCK +tIS  
CKE min. pulse width(high and low pulse width)  
Auto refresh cycle time  
tCKE  
tRFC  
tXSR  
2
2
tCK  
ns  
80  
90  
7
Exit self refresh to active command  
120  
120  
ns  
tHPmin -  
tQHS  
tHPmin -  
tQHS  
Data hold from DQS to earliest DQ edge  
Data hold skew factor  
tQH  
tQHS  
tHP  
ns  
ns  
ns  
0.75  
1.0  
tCLmin or  
tCHmin  
tCLmin or  
tCHmin  
Clock half period  
February 2006  
K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
Note :  
1. Input Setup/Hold Slew Rate Derating  
Input Setup/Hold Slew Rate  
tIS  
(ps)  
0
tIH  
(ps)  
0
(V/ns)  
1.0  
0.8  
+50  
+100  
+50  
+100  
0.6  
This derating table is used to increase t /t in the case where the input slew rate is below 1.0V/ns.  
IS IH  
2. Minimum 3CLK of tDAL(= tWR + tRP) is required because it need minimum 2CLK for tWR and minimum 1CLK for tRP.  
3. tAC(min) value is measured at the high Vdd(1.95V) and cold temperature(-25°C).  
tAC(max) value is measured at the low Vdd(1.7V) and hot temperature(85°C).  
tAC is measured in the device with half driver strength and under the AC output load condition (Fig.7 in next Page).  
4. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from  
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,  
DQS could be High at this time, depending on tDQSS.  
5. I/O Setup/Hold Slew Rate Derating  
I/O Setup/Hold Slew Rate  
tDS  
(ps)  
0
tDH  
(ps)  
0
(V/ns)  
1.0  
0.8  
+75  
+150  
+75  
+150  
0.6  
This derating table is used to increase t /t in the case where the I/O slew rate is below 1.0V/ns.  
DS DH  
6. I/O Delta Rise/Fall Rate(1/slew-rate) Derating  
Delta Rise/Fall Rate  
tDS  
(ps)  
0
tDH  
(ps)  
0
(ns/V)  
0
±0.25  
±0.5  
+50  
+100  
+50  
+100  
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate  
is calculated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 1.0V/ns and slew rate 2 =0.8V/ns, then the Delta Rise/Fall  
Rate =-0.25ns/V.  
7. Maximum burst refresh cycle : 8  
February 2006  
K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
AC Operating Test Conditions(VDD = 1.7V to 1.95V, Tc = -25 to 85°C)  
Parameter  
AC input levels (Vih/Vil)  
Value  
Unit  
0.8 x VDDQ / 0.2 x VDDQ  
0.5 x VDDQ  
V
V
Input timing measurement reference level  
Input signal minimum slew rate  
1.0  
V/ns  
V
Output timing measurement reference level  
Output load condition  
0.5 x VDDQ  
See Figure.7  
1.8V  
Vtt=0.5 x VDDQ  
13.9KΩ  
VOH (DC) = 0.9 x VDDQ , IOH = -0.1mA  
VOL (DC) = 0.1 x VDDQ , IOL = 0.1mA  
20pF  
Output  
50Ω  
10.6KΩ  
Output  
Z0=50Ω  
20pF  
Figure.6 DC Output Load Circuit  
Figure.7 AC Output Load Circuit  
Input/Output Capacitance(VDD=1.8, VDDQ=1.8V, TC = 25°C, f=1MHz)  
Parameter  
Symbol  
Min  
Max  
Unit  
Input capacitance  
(A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)  
CIN1  
1.5  
3.0  
pF  
Input capacitance( CK, CK )  
CIN2  
COUT  
CIN3  
1.5  
2.0  
2.0  
3.5  
4.5  
4.5  
pF  
pF  
pF  
Data & DQS input/output capacitance  
Input capacitance(DM)  
February 2006  
K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
AC Overshoot/Undershoot Specification for Address & Control Pins  
Parameter  
Specification  
0.9V  
Maximum peak Amplitude allowed for overshoot area  
Maximum peak Amplitude allowed for undershoot area  
Maximum overshoot area above VDD  
0.9V  
3V-ns  
Maximum undershoot area below VSS  
3V-ns  
Maximum Amplitude  
Overshoot Area  
VDD  
VSS  
Volts  
(V)  
Undershoot Area  
Maximum Amplitude  
Time (ns)  
Figure.8 AC Overshoot and Undershoot Definition for Address and Control Pins  
AC Overshoot/Undershoot Specification for CLK, DQ, DQS and DM Pins  
Parameter  
Specification  
0.9V  
Maximum peak Amplitude allowed for overshoot area  
Maximum peak Amplitude allowed for undershoot area  
Maximum overshoot area above VDDQ  
0.9V  
3V-ns  
Maximum undershoot area below VSSQ  
3V-ns  
Maximum Amplitude  
Overshoot Area  
VDDQ  
VSSQ  
Volts  
(V)  
Undershoot Area  
Maximum Amplitude  
Time (ns)  
Figure.9 AC Overshoot and Undershoot Definition for CLK, DQ, DQS and DM Pins  
February 2006  
K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
Command Truth Table(V=Valid, X=Dont Care, H=Logic High, L=Logic Low)  
A12,A11,  
A9 ~ A0  
COMMAND  
Mode Register Set  
CKEn-1 CKEn CS  
RAS  
CAS  
WE BA0,1 A10/AP  
Note  
Register  
Refresh  
H
H
X
H
L
L
L
L
L
L
OP CODE  
1, 2  
3
Auto Refresh  
L
L
H
X
X
Entry  
Exit  
3
Self  
Refresh  
L
H
L
H
X
L
H
X
H
H
X
H
3
L
H
H
H
X
X
3
Bank Active & Row Addr.  
V
V
Row Address  
Read &  
Auto Precharge Disable  
Auto Precharge Enable  
L
Column  
Address  
(A0~A9)  
4
4
L
L
H
H
L
L
H
L
Column Address  
H
Write &  
Auto Precharge Disable  
Auto Precharge Enable  
L
Column  
Address  
(A0~A9)  
4
H
X
V
Column Address  
H
4, 6  
Entry  
Exit  
H
L
L
H
X
L
H
L
H
X
H
H
X
H
L
X
L
Deep Power Down  
Burst Stop  
X
X
H
7
5
Bank Selection  
All Banks  
V
X
L
Precharge  
H
X
L
L
H
L
X
H
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry  
H
L
L
H
L
Active Power Down  
X
X
Exit  
X
H
L
Entry  
H
Precharge Power Down  
H
L
Exit  
L
H
H
H
X
DM  
X
X
8
9
9
H
L
X
H
X
H
No operation (NOP) : Not defined  
Note :  
1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)  
2.EMRS/ MRS can be issued only at all banks precharge state.  
A new command can be issued 2 clock cycles after EMRS or MRS.  
3. Auto refresh functions are same as the CBR refresh of DRAM.  
The automatical precharge without row precharge command is meant by "Auto".  
Auto/self refresh can be issued only at all banks precharge state.  
4. BA0 ~ BA1 : Bank select addresses.  
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.  
6. During burst write with auto precharge, new read/write command can not be issued.  
Another bank read/write command can be issued after the end of burst.  
New row active of the associated bank can be issued at tRP after the end of burst.  
7. Burst stop command is valid at every burst length.  
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).  
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.  
February 2006  
K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
Functional Truth Table  
Current State  
CS  
L
RAS CAS  
WE  
L
Address  
Command  
Action  
*2  
*2  
PRECHARGE  
STANDBY  
H
H
L
H
L
X
Burst Stop  
READ/WRITE  
Active  
ILLEGAL  
ILLEGAL  
L
X
BA, CA, A10  
BA, RA  
L
H
H
H
Bank Active, Latch RA  
*4  
L
L
L
BA, A10  
PRE/PREA  
ILLEGAL  
*5  
L
L
L
L
L
L
L
H
L
L
X
Refresh  
MRS  
AUTO-Refresh  
*5  
Op-Code, Mode-Add  
X
Mode Register Set  
ACTIVE  
H
H
Burst Stop  
NOP  
STANDBY  
Begin Read, Latch CA,  
Determine Auto-Precharge  
L
L
H
H
L
L
H
L
BA, CA, A10  
BA, CA, A10  
READ/READA  
Begin Write, Latch CA,  
Determine Auto-Precharge  
WRITE/WRITEA  
*2  
L
L
L
L
L
L
L
L
L
H
H
H
L
H
L
BA, RA  
Active  
Bank Active/ILLEGAL  
BA, A10  
PRE/PREA  
Refresh  
MRS  
Precharge/Precharge All  
ILLEGAL  
H
L
X
L
Op-Code, Mode-Add  
X
ILLEGAL  
READ  
H
L
Burst Stop  
Terminate Burst  
Terminate Burst, Latch CA,  
Begin New Read, Determine  
L
H
L
H
BA, CA, A10  
READ/READA  
*3  
Auto-Precharge  
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
L
BA, CA, A10  
BA, RA  
BA, A10  
X
WRITE/WRITEA  
Active  
ILLEGAL  
*2  
Bank Active/ILLEGAL  
PRE/PREA  
Refresh  
Terminate Burst, Precharge  
ILLEGAL  
H
L
L
Op-Code, Mode-Add MRS  
ILLEGAL  
February 2006  
K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
Functional truth table  
Current State  
CS  
RAS CAS WE  
Address  
Command  
Burst Stop  
Action  
ILLEGAL  
WRITE  
L
H
H
L
X
Terminate Burst With DM=High, Latch CA,  
*3  
L
L
H
L
H
BA, CA, A10  
BA, CA, A10  
READ/READA  
Begin Read, Determine Auto-Precharge  
Terminate Burst, Latch CA,  
Begin new Write, Determine Auto-Pre-  
H
L
L
WRITE/WRITEA  
*3  
charge  
*2  
L
L
L
L
H
H
H
L
BA, RA  
BA, A10  
X
Active  
Bank Active/ILLEGAL  
Terminate Burst With DM=High,  
Precharge  
PRE/PREA  
Refresh  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
ILLEGAL  
ILLEGAL  
ILLEGAL  
*6  
Op-Code, Mode-Add MRS  
READ with  
AUTO  
H
H
H
L
H
L
L
X
Burst Stop  
READ/READA  
H
L
BA, CA, A10  
BA, CA, A10  
BA, RA  
BA, A10  
X
*6  
PRECHARGE  
(READA)  
L
WRITE/WRITEA ILLEGAL  
H
H
L
H
L
Active  
*6  
L
PRE/PREA  
Refresh  
*6  
L
H
L
ILLEGAL  
ILLEGAL  
ILLEGAL  
*7  
L
L
Op-Code, Mode-Add MRS  
WRITE with  
AUTO  
H
H
H
L
H
L
L
X
Burst Stop  
READ/READA  
WRITE/WRITEA *7  
H
L
BA, CA, A10  
BA, CA, A10  
BA, RA  
BA, A10  
X
*7  
RECHARGE  
(WRITEA)  
L
H
H
L
H
L
Active  
*7  
L
PRE/PREA  
Refresh  
*7  
L
H
L
ILLEGAL  
ILLEGAL  
L
L
Op-Code, Mode-Add MRS  
February 2006  
K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
Functional truth table  
Current State  
CS  
L
RAS  
H
CAS  
H
WE  
L
Address  
Command  
Action  
*2  
PRECHARGING  
(DURING tRP)  
X
Burst Stop  
READ/WRITE  
Active  
ILLEGAL  
ILLEGAL  
*2  
*2  
L
H
L
X
BA, CA, A10  
BA, RA  
L
L
H
H
ILLEGAL  
*4  
L
L
L
L
L
L
H
L
L
H
L
BA, A10  
PRE/PREA  
Refresh  
MRS  
NOP (Idle after tRP)  
ILLEGAL  
X
L
L
Op-Code, Mode-Add  
X
ILLEGAL  
*2  
ROW  
ACTIVATING  
H
H
L
Burst Stop  
ILLEGAL  
*2  
L
L
H
L
L
X
H
BA, CA, A10  
READ/WRITE  
Active  
ILLEGAL  
(FROM ROW  
ACTIVE TO  
tRCD)  
*2  
H
BA, RA  
ILLEGAL  
*2  
BA, A10  
L
L
L
L
L
L
H
L
L
H
L
PRE/PREA  
Refresh  
MRS  
ILLEGAL  
X
ILLEGAL  
ILLEGAL  
L
L
Op-Code, Mode-Add  
X
*2  
WRITE  
RECOVERING  
H
H
L
Burst Stop  
ILLEGAL  
*2  
L
L
L
L
L
L
H
H
L
L
L
L
L
L
H
L
BA, CA, A10  
BA, CA, A10  
BA, RA  
READ  
ILLEGAL  
(DURING tWR  
OR tCDLR)  
WRITE  
Active  
WRITE  
*2  
H
H
L
H
L
ILLEGAL  
*2  
BA, A10  
PRE/PREA  
Refresh  
MRS  
ILLEGAL  
H
L
X
ILLEGAL  
ILLEGAL  
L
Op-Code, Mode-Add  
February 2006  
K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
Functional truth table  
Current State  
CS  
L
RAS  
H
H
L
CAS  
H
L
WE  
L
Address  
Command  
Action  
RE-  
FRESHING  
X
Burst Stop  
READ/WRITE  
Active  
ILLEGAL  
ILLEGAL  
ILLEGAL  
ILLEGAL  
ILLEGAL  
ILLEGAL  
ILLEGAL  
ILLEGAL  
ILLEGAL  
ILLEGAL  
ILLEGAL  
ILLEGAL  
L
X
H
L
BA, CA, A10  
L
H
H
L
BA, RA  
L
L
BA, A10  
PRE/PREA  
Refresh  
L
L
H
L
X
L
L
L
Op-Code, Mode-Add  
MRS  
MODE  
REGISTER  
SETTING  
L
H
H
L
H
L
L
X
Burst Stop  
READ/WRITE  
Active  
L
X
H
L
BA, CA, A10  
BA, RA  
L
H
H
L
BA, A10  
L
L
PRE/PREA  
Refresh  
L
L
H
L
X
L
L
L
Op-Code, Mode-Add  
MRS  
February 2006  
K4X51163PC - L(F)E/G  
Mobile-DDR SDRAM  
Functional truth table  
CKE  
n-1  
CKE  
n
Current State  
CS  
RAS  
CAS  
WE  
Add  
Action  
SELF-  
L
L
H
H
H
H
H
L
H
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Exit Self-Refresh  
*8  
REFRESHING  
Exit Self-Refresh  
L
L
ILLEGAL  
L
L
X
X
X
X
X
X
X
X
H
X
H
L
ILLEGAL  
L
L
X
X
X
X
X
X
X
L
ILLEGAL  
L
X
X
X
H
X
X
L
X
X
X
X
X
X
L
NOPeration(Maintain Self-Refresh)  
Exit Power Down(Idle after tPDEX)  
NOPeration(Maintain Power Down)  
POWER  
DOWN  
L
H
L
L
*10  
DEEP POWER  
DOWN  
L
H
L
Exit Deep Power Down  
L
NOPeration(Maintain Deep Power Down)  
Refer to Function True Table  
Enter Self-Refresh  
ALL BANKS  
IDLE*9  
H
H
H
H
H
H
H
H
L
H
L
L
H
L
X
H
H
H
H
L
X
H
H
H
L
Enter Power Down  
L
Enter Power Down  
L
L
Enter Deep Power Down  
ILLEGAL  
L
L
L
L
L
X
X
X
X
ILLEGAL  
L
L
X
X
X
ILLEGAL  
X
H
X
X
X
X
Refer to Current State=Power Down  
Refer to Function Truth Table  
ANY STATE  
other than  
H
listed above  
ABBREVIATIONS :  
H=High Level, L=Low level, X=Dont Care  
Note :  
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.  
2. ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank.(ILLEGAL = Device oper-  
ation and/or data integrity are not guaranteed.)  
3. Must satisfy bus contention, bus turn around and write recovery requirements.  
4. NOP to bank precharging or in idle sate. May precharge bank indicated by BA.  
5. ILLEGAL if any bank is not idle.  
6. Refer to "Read with Auto Precharge Timing Diagram" for detailed information.  
7. Refer to "Write with Auto Precharge Timing Diagram" for detailed information.  
8. CKE Low to High transition will re-enable CK, CK and other inputs asynchronously. A minimum setup time must be satisfied before issuing any com-  
mand other than EXIT.  
9. Power-Down, Self-Refresh and Deep Power Down Mode can be entered only from All Bank Idle state.  
10. The Deep Power Down Mode is exited by asserting CKE high and full initialization is required after exiting Deep Power Down Mode.  
February 2006  
配单直通车
K4X51163PC-FEC3产品参数
型号:K4X51163PC-FEC3
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Obsolete
包装说明:FBGA, BGA60,9X10,32
Reach Compliance Code:unknown
风险等级:5.84
最长访问时间:6 ns
最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMON
交错的突发长度:2,4,8,16
JESD-30 代码:R-PBGA-B60
JESD-609代码:e3
内存密度:536870912 bit
内存集成电路类型:DDR DRAM
内存宽度:16
湿度敏感等级:1
端子数量:60
字数:33554432 words
字数代码:32000000
最高工作温度:85 °C
最低工作温度:-25 °C
组织:32MX16
输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY
封装代码:FBGA
封装等效代码:BGA60,9X10,32
封装形状:RECTANGULAR
封装形式:GRID ARRAY, FINE PITCH
峰值回流温度(摄氏度):225
电源:1.8 V
认证状态:Not Qualified
刷新周期:8192
连续突发长度:2,4,8,16
最大待机电流:0.0003 A
子类别:DRAMs
最大压摆率:0.15 mA
标称供电电压 (Vsup):1.8 V
表面贴装:YES
技术:CMOS
温度等级:OTHER
端子面层:MATTE TIN
端子形式:BALL
端子节距:0.8 mm
端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1
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