K6F1616U6A-EF70中文资料应用文章市场行情现货热卖使用介绍-中国IC网-芯三七

当前位置：IC37首页_>K字母起始型号索引_>K字母起始型号索引第141页更新时间：2024-12-04 15:29:17

产品型号K6F1616U6A-EF70的概述

芯片K6F1616U6A-EF70的概述 K6F1616U6A-EF70是一款32Mb（即2M x 16-bit）的NAND Flash存储芯片，广泛应用于各种电子产品中，如手机、数码相机和其他便携式设备。该芯片由广为人知的半导体制造商——希捷科技（Seagate Technology）生产。其低功耗特性、优秀的读写速度和较高的存储密度使其在存储器市场中占据了一席之地。K6F1616U6A-EF70有助于满足现代电子设备对高速存储和小型化的需求。芯片K6F1616U6A-EF70的详细参数 K6F1616U6A-EF70具有多项技术参数，这些参数对其性能和应用场景起着至关重要的作用。以下列举了其主要参数： 1. 存储容量：32Mb（2M x 16-bit） 2. 操作电压：2.7V到3.6V（典型值为3.3V） 3. 存取时间：读出数据时间为25ns（最大值） 4. 写入速度：4字节...

产品型号K6F1616U6A-EF70的Datasheet PDF文件预览

K6F1616U6A Family

CMOS SRAM

Document Title

1M x16 bit Super Low Power and Low Voltage Full CMOS Static RAM

Revision History

Revision No. History

Draft Date

Remark

0.0

Initial draft

September 11, 2001 Preliminary

1.0

Finalize

January 4, 2002

Final

- added 45ns product

- changed ICC1 : 3mA to 2mA

- changed ICC2 : 38mA to 30mA for 55ns product

30mA to 25mA for 70ns product

1.1

Revise

September 11, 2002 Final

- Deleted 45ns product

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

Revision 1.1

September 2002

K6F1616U6A Family

CMOS SRAM

1M x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM

FEATURES

GENERAL DESCRIPTION

· Process Technology: Full CMOS

· Organization: 1M x16

The K6F1616U6A families are fabricated by SAMSUNG¢s

advanced full CMOS process technology. The families support

industrial operating temperature ranges and have chip scale

package for user flexibility of system design. The families also

support low data retention voltage for battery back-up operation

with low data retention current.

· Power Supply Voltage: 2.7~3.3V

· Low Data Retention Voltage: 1.5V(Min)

· Three State Outputs

· Package Type: 48-TBGA-7.50x9.50

PRODUCT FAMILY

Power Dissipation

Product Family

Operating Temperature

Vcc Range

Speed

PKG Type

Standby

(ISB1, Typ.)

Operating

(ICC1, Max)

55¹⁾/70ns

1mA²⁾

K6F1616U6A-F

Industrial(-40~85°C)

2.7~3.3V

2mA

48-TBGA-7.50x9.50

1. The parameter is measured with 30pF test load.

2. Typical values are measured at VCC=3.0V, TA=25°C and not 100% tested.

PIN DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

Clk gen.

Precharge circuit.

CS2

I/O1

I/O3

Vcc

Vss

I/O9

I/O10

Vss

CS1

I/O2

I/O4

I/O5

I/O6

Row

Addresses

Memory

Cell

Array

Row

select

I/O11

I/O12

I/O13

I/O14

A19

A17

Vss

A14

A12

I/O Circuit

Column select

Data

cont

I/O1~I/O8

Vcc

A16

A15

A13

A10

Vss

Data

cont

I/O9~I/O16

I/O15

I/O16

A18

I/O7

I/O8

DNU

Data

cont

Column Addresses

A11

CS1

CS2

48-TBGA: Top View (Ball Down)

Control Logic

Name

Function

Name

Function

CS1, CS2 Chip Select Inputs

Vcc Power

Vss Ground

Output Enable Input

Write Enable Input

Address Inputs

Upper Byte(I/O9~16)

Lower Byte(I/O1~8)

A0~A19

I/O1~I/O16 Data Inputs/Outputs

DNU Do Not Use

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Revision 1.1

September 2002

K6F1616U6A Family

CMOS SRAM

PRODUCT LIST

Industrial Temperature Products(-40~85°C)

Part Name

Function

K6F1616U6A-EF55

K6F1616U6A-EF70

48-TBGA, 55ns, 3.0V

48-TBGA, 70ns, 3.0V

FUNCTIONAL DESCRIPTION

CS1

X¹⁾

CS2

X¹⁾

I/O1~8

High-Z

Dout

I/O9~16

High-Z

Dout

Mode

Power

Standby

Active

Deselected

X¹⁾

Deselected

X¹⁾

Output Disabled

Lower Byte Read

Upper Byte Read

Word Read

X¹⁾

Active

High-Z

Dout

Active

Dout

Active

X¹⁾

Din

High-Z

Din

Lower Byte Write

Upper Byte Write

Word Write

Active

High-Z

Din

Active

Din

Active

1. X means don¢t care. (Must be low or high state)

ABSOLUTE MAXIMUM RATINGS¹⁾

Item

Voltage on any pin relative to Vss

Voltage on Vcc supply relative to Vss

Power Dissipation

Symbol

VIN,VOUT

VCC

Ratings

Unit

-0.2 to VCC+0.3V(Max. 3.6V)

-0.2 to 3.6

1.0

°C

Storage temperature

TSTG

-65 to 150

-40 to 85

Operating Temperature

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended period may affect reliability.

Revision 1.1

September 2002

K6F1616U6A Family

CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS¹⁾

Item

Symbol

Vcc

Min

2.7

Typ

Max

Unit

Supply voltage

Ground

3.0

3.3

Vss

Vcc+0.3²⁾

0.6

Input high voltage

Input low voltage

Note:

VIH

2.2

-0.3³⁾

VIL

1. TA=-40 to 85°C, otherwise specified

2. Overshoot: VCC+2.0V in case of pulse width £20ns.

3. Undershoot: -2.0V in case of pulse width £20ns.

4. Overshoot and Undershoot are sampled, not 100% tested.

CAPACITANCE¹⁾(f=1MHz, TA=25°C)

Item

Input capacitance

Symbol

CIN

Test Condition

VIN=0V

Min

Max

Unit

Input/Output capacitance

CIO

VIO=0V

1. Capacitance is sampled, not 100% tested

DC AND OPERATING CHARACTERISTICS

Typ¹⁾

Symbol

Item

Test Conditions

Min

Max

Unit

Input leakage current

ILI

VIN=Vss to Vcc

-1

CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or LB=UB=VIH,

VIO=Vss to Vcc

Output leakage current

ILO

-1

Cycle time=1ms, 100%duty, IIO=0mA, CS1£0.2V, LB£0.2V

or/and UB£0.2V, CS2³ Vcc-0.2V, VIN£0.2V or VIN³ VCC-0.2V

ICC1

Average operating current

Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL,

CS2=VIH, LB=VIL or/and UB=VIL, VIN=VIL or VIH

70ns

55ns

0.4

ICC2

Output low voltage

Output high voltage

VOL

VOH

IOL = 2.1mA

IOH = -1.0mA

2.4

Other input =0~Vcc

Standby Current (CMOS)

ISB1

1) CS1³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 controlled) or

2) 0V£CS2£0.2V(CS2 controlled)

1.0

1. Typical values are measured at VCC=3.0V, TA=25°C and not 100% tested.

Revision 1.1

September 2002

K6F1616U6A Family

CMOS SRAM

VTM

AC OPERATING CONDITIONS

TEST CONDITIONS(Test Load and Input/Output Reference)

Input pulse level: 0.4 to 2.2V

Input rising and falling time: 5ns

Input and output reference voltage:1.5V

Output load(see right): CL=100pF+1TTL

CL=30pF+1TTL

1. Including scope and jig capacitance

2. R1=3070W, R2=3150W

3. VTM =2.8V

AC CHARACTERISTICS ( Vcc=2.7~3.3V, Industrial product:TA=-40 to 85°C )

Speed

Parameter List

Symbol

Units

55ns

70ns

Min

Max

Min

Max

Read cycle time

tRC

tAA

Address access time

Chip select to output

tCO1, tCO2

tOE

Output enable to valid output

UB, LB valid to data output

Chip select to low-Z output

UB, LB enable to low-Z output

Output enable to low-Z output

Chip disable to high-Z output

UB, LB disable to high-Z output

Output disable to high-Z output

Output hold from address change

Write cycle time

tBA

tLZ1, tLZ2

tBLZ

Read

tOLZ

tHZ1, tHZ2

tBHZ

tOHZ

tOH

tWC

Chip select to end of write

Address set-up time

tCW1, tCW2

tAS

Address valid to end of write

UB, LB Valid to End of Write

Write pulse width

tAW

tBW

Write

tWP

Write recovery time

tWR

Write to output high-Z

tWHZ

tDW

Data to write time overlap

Data hold from write time

End write to output low-Z

tDH

tOW

DATA RETENTION CHARACTERISTICS

Item

Vcc for data retention

Data retention current

Data retention set-up time

Recovery time

Symbol

VDR

Test Condition

Min

Typ

Max

Unit

CS1³ Vcc-0.2V¹⁾, VIN³ 0V

1.5

3.3

Vcc=1.5V, CS1³ Vcc-0.2V¹⁾, VIN³ 0V

1.0²⁾

IDR

tSDR

tRDR

See data retention waveform

tRC

1. 1) CS¹³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 controlled) or

2) 0£CS2£0.2V(CS2 controlled)

2. Typical value is measured at TA=25°C and not 100% tested.

Revision 1.1

September 2002

K6F1616U6A Family

CMOS SRAM

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL)

tRC

Address

tAA

tOH

Data Valid

Data Out

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tOH

tAA

tCO

CS1

CS2

tHZ

tBA

UB, LB

tBHZ

tOHZ

tOE

tOLZ

tBLZ

tLZ

Data out

High-Z

Data Valid

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

Revision 1.1

September 2002

K6F1616U6A Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

tWC

Address

CS1

tCW(2)

tWR(4)

CS2

tAW

tBW

UB, LB

tWP(1)

tAS(3)

tDW

tDH

High-Z

Data in

Data Valid

tWHZ

tOW

Data Undefined

Data out

TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)

tWC

Address

tWR(4)

tAS(3)

tCW(2)

tAW

CS1

CS2

tBW

UB, LB

tWP(1)

tDW

tDH

Data Valid

Data in

Data out

High-Z

Revision 1.1

September 2002

K6F1616U6A Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)

tWC

Address

CS1

tWR(4)

tCW(2)

tAW

CS2

tBW

UB, LB

tAS(3)

tWP(1)

tDH

tDW

Data in

Data Valid

High-Z

Data out

High-Z

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting

UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-

sition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the CS1 going low to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high.

DATA RETENTION WAVE FORM

CS1 controlled

Data Retention Mode

tSDR

tRDR

VCC

2.7V

2.2V

VDR

CS1³ VCC - 0.2V

CS1

GND

CS2 controlled

Data Retention Mode

VCC

2.7V

CS2

tSDR

tRDR

VDR

CS2£0.2V

0.4V

GND

Revision 1.1

September 2002

K6F1616U6A Family

CMOS SRAM

Unit: millimeters

PACKAGE DIMENSION

48 BALL TAPE BALL GRID ARRAY(0.75mm ball pitch)

Top View

Bottom View

#A1

B/2

Detail A

Side View

Min

Typ

0.75

7.50

3.75

9.50

5.25

0.45

0.90

0.55

0.35

Max

7.40

Notes.

7.60

1. Bump counts: 48(8 row x 6 column)

2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)

3. All tolerence are ±0.050 unless

otherwise specified.

9.40

9.60

4. Typ: Typical

0.40

0.80

0.50

1.00

5. Y is coplanarity: 0.08(Max)

0.30

0.40

0.08

Revision 1.1

September 2002

K6F1616U6A-EF70相关文章

配单直通车

首天国际（深圳）科技有限公司服务专线: 0755-82807802/82807803 在线联系:

QQ：528164397 复制

QQ：1318502189 复制

深圳市芯福林电子有限公司服务专线: 13418564337 在线联系:

QQ：2881495808 复制

QQ：308365177 复制

深圳市中利达电子科技有限公司服务专线: 0755-13686833545 在线联系:

QQ：1902134819 复制

QQ：2881689472 复制

北京元坤伟业科技有限公司服务专线: 010-62104931621064316210489162104791 在线联系:

QQ：857273081 复制

QQ：1594462451 复制

柒号芯城电子商务（深圳）有限公司服务专线: 18922803401 在线联系:

QQ：2881677436 复制

QQ：2881620402 复制

K6F1616U6A-EF70产品参数

型号:	K6F1616U6A-EF70
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	SAMSUNG SEMICONDUCTOR INC
零件包装代码：	BGA
包装说明：	VFBGA, BGA48,6X8,30
针数：	48
Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41
风险等级：	5.89
Is Samacsys：	N
最长访问时间：	70 ns
I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B48
JESD-609代码：	e0
长度：	9.5 mm
内存密度：	16777216 bit
内存集成电路类型：	STANDARD SRAM
内存宽度：	16
功能数量：	1
端子数量：	48
字数：	1048576 words
字数代码：	1000000
工作模式：	ASYNCHRONOUS
最高工作温度：	85 °C
最低工作温度：	-40 °C
组织：	1MX16
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	VFBGA
封装等效代码：	BGA48,6X8,30
封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3 V
认证状态：	Not Qualified
座面最大高度：	1 mm
最大待机电流：	0.000008 A
最小待机电流：	1.5 V
子类别：	SRAMs
最大压摆率：	0.025 mA
最大供电电压 (Vsup)：	3.3 V
最小供电电压 (Vsup)：	2.7 V
标称供电电压 (Vsup)：	3 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL
端子节距：	0.75 mm
端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.5 mm
Base Number Matches：	1

电子百科

产品导航

产品型号K6F1616U6A-EF70的概述

产品型号K6F1616U6A-EF70的Datasheet PDF文件预览

K6F1616U6A-EF70相关产品

K6F1616U6A-EF70相关文章

IC37:专业IC行业平台