Preliminary
K6F2016U4E Family
CMOS SRAM
3)
AC OPERATING CONDITIONS
VTM
TEST CONDITIONS(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V
2)
R1
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): CL=100pF+1TTL
CL=30pF+1TTL
1)
2)
CL
R2
1. Including scope and jig capacitance
2. R1=3070W, R2=3150W
3. VTM =2.8V
AC CHARACTERISTICS(Vcc=2.7~3.3V, Industrial product:TA=-40 to 85°C)
Speed Bins
55ns1)
Parameter List
Symbol
Units
70ns
Min
55
-
Max
Min
Max
Read Cycle Time
tRC
tAA
-
55
55
25
55
-
70
-
-
70
70
35
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
-
-
Output Enable to Valid Output
UB, LB Access Time
-
-
tBA
-
-
Chip Select to Low-Z Output
UB, LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
tLZ
10
10
5
10
10
5
Read
tBLZ
tOLZ
tHZ
-
-
-
-
0
20
20
20
-
0
25
25
25
-
tBHZ
tOHZ
tOH
tWC
tCW
tAS
0
0
0
0
10
55
45
0
10
70
60
0
-
-
Chip Select to End of Write
Address Set-up Time
-
-
-
-
Address Valid to End of Write
UB, LB Valid to End of Write
Write Pulse Width
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
45
45
40
0
-
60
60
50
0
-
-
-
Write
-
-
Write Recovery Time
-
-
Write to Output High-Z
0
20
-
0
20
-
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
25
0
30
0
-
-
tOW
5
-
5
-
1. The parameter is measured with 30pF test load.
DATA RETENTION CHARACTERISTICS
Typ2)
Item
Symbol
VDR
Test Condition
Min
1.5
-
Max
Unit
V
CS³ Vcc-0.2V1)
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
-
0.5
-
3.3
Vcc= 1.5V, CS³ Vcc-0.2V1)
IDR
2
-
mA
tSDR
0
See data retention waveform
ns
tRDR
tRC
-
-
1. 1) CS³ Vcc-0.2V(CS controlled) or
2) LB=UB³ Vcc-0.2V, CS£0.2V(LB/UB controlled)
2. Typical value are measured at TA=25°C and not 100% tested.
Revision 0.0
- 5 -
February 2001