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    产品型号K6R4016V1C-TI120的Datasheet PDF文件预览

    PRELIMPreliminaryPPPPPPPPPINARY  
    CMOS SRAM  
    K6R4016V1C-C/C-L, K6R4016V1C-I/C-P  
    Document Title  
    256Kx16 Bit High Speed Static RAM(3.3V Operating).  
    Operated at Commercial and Industrial Temperature Ranges.  
    Revision History  
    RevNo.  
    Rev. 0.0  
    Rev. 1.0  
    History  
    Draft Data  
    Remark  
    Initial release with Preliminary.  
    Feb. 12. 1999  
    Mar. 29. 1999  
    Preliminary  
    Preliminary  
    1.1 Removed Low power Version.  
    1.2 Removed Data Retention Characteristics.  
    1.3 Changed ISB1 to 20mA  
    Rev. 2.0  
    Rev. 3.0  
    Relax D.C parameters.  
    Aug. 19. 1999  
    Mar. 27. 2000  
    Preliminary  
    Item  
    Previous  
    180mA  
    175mA  
    170mA  
    Current  
    200mA  
    195mA  
    190mA  
    12ns  
    15ns  
    20ns  
    ICC  
    Final  
    3.1 Delete Preliminary  
    3.2 Update D.C parameters and 10ns part.  
    Previous  
    Current  
    ICC  
    -
    200mA  
    195mA  
    190mA  
    Isb  
    Isb1  
    ICC  
    Isb  
    Isb1  
    10ns  
    12ns  
    15ns  
    20ns  
    160mA  
    150mA  
    140mA  
    130mA  
    70mA  
    20mA  
    60mA  
    10mA  
    Apr. 24. 2000  
    Sep. 24. 2001  
    Final  
    Final  
    Add Low Power-Ver.  
    Delete 20ns speed bin  
    Rev. 4.0  
    Rev. 5.0  
    The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the  
    specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-  
    tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.  
    Rev 5.0  
    September 2001  
    - 1 -  
    PRELIMPreliminaryPPPPPPPPPINARY  
    CMOS SRAM  
    K6R4016V1C-C/C-L, K6R4016V1C-I/C-P  
    256K x 16 Bit High-Speed CMOS Static RAM  
    FEATURES  
    • Fast Access Time 10,12,15ns(Max.)  
    • Low Power Dissipation  
    Standby (TTL)  
    (CMOS) : 10mA(Max.)  
    1.2mA(Max.) L-Ver. only  
    Operating K6R4016V1C-10 : 160mA(Max.)  
    K6R4016V1C-12 : 150mA(Max.)  
    K6R4016V1C-15 : 140mA(Max.)  
    • Single 3.3 ±0.3V Power Supply  
    • TTL Compatible Inputs and Outputs  
    • Fully Static Operation  
    GENERAL DESCRIPTION  
    The K6R4016V1C is a 4,194,304-bit high-speed Static Random  
    Access Memory organized as 262,144 words by 16 bits. The  
    K6R4016V1C uses 16 common input and output lines and has  
    an output enable pin which operates faster than address  
    access time at read cycle. Also it allows that lower and upper  
    byte access by data byte control(UB, LB). The device is fabri-  
    cated using SAMSUNG¢s advanced CMOS process and  
    designed for high-speed circuit technology. It is particularly well  
    suited for use in high-density high-speed system applications.  
    The K6R4016V1C is packaged in a 400mil 44-pin plastic SOJ  
    or TSOP(II) forward or 48 Fine pitch BGA.  
    : 60mA(Max.)  
    - No Clock or Refresh required  
    • Three State Outputs  
    • 2V Minimum Data Retention : L-Ver. only  
    • Center Power/Ground Pin Configuration  
    • Data Byte Control : LB : I/O1~ I/O8, UB : I/O9~ I/O16  
    • Standard Pin Configuration  
    K6R4016V1C-J : 44-SOJ-400  
    K6R4016V1C-T : 44-TSOP2-400BF  
    K6R4016V1C-F : 48-Fine pitch BGA with 0.75 Ball pitch  
    ORDERING INFORMATION  
    FUNCTIONAL BLOCK DIAGRAM  
    K6R4016V1C-C10/C12/C15  
    Commercial Temp.  
    Industrial Temp.  
    K6R4016V1C-I10/I12/I15  
    Clk Gen.  
    Pre-Charge Circuit  
    A0  
    A1  
    A2  
    A3  
    A4  
    A5  
    A6  
    A7  
    A8  
    A9  
    Memory Array  
    1024 Rows  
    256 x 16 Columns  
    Data  
    Cont.  
    I/O Circuit &  
    Column Select  
    I/O1~I/O8  
    Data  
    Cont.  
    I/O9~I/O16  
    Gen.  
    CLK  
    A10 A11 A12 A13 A14 A15 A16 A17  
    WE  
    OE  
    UB  
    LB  
    CS  
    Rev 5.0  
    September 2001  
    - 2 -  
    PRELIMPreliminaryPPPPPPPPPINARY  
    CMOS SRAM  
    K6R4016V1C-C/C-L, K6R4016V1C-I/C-P  
    PIN CONFIGURATION (Top View)  
    1
    2
    3
    4
    5
    6
    A0  
    A1  
    1
    2
    3
    4
    5
    6
    7
    8
    9
    44 A17  
    43 A16  
    42 A15  
    41 OE  
    A
    B
    C
    D
    E
    F
    LB  
    OE  
    UB  
    A0  
    A3  
    A1  
    A4  
    A2  
    N.C  
    I/O9  
    I/O10  
    Vcc  
    A2  
    A3  
    I/O1  
    CS  
    A4  
    40 UB  
    CS  
    I/O1  
    I/O2  
    I/O3  
    39 LB  
    I/O2  
    Vss  
    I/O3  
    I/O4  
    I/O5  
    I/O6  
    N.C  
    A8  
    A5  
    A6  
    I/O11  
    I/O12  
    I/O13  
    I/O14  
    WE  
    38 I/O16  
    37 I/O15  
    36 I/O14  
    35 I/O13  
    34 Vss  
    33 Vcc  
    32 I/O12  
    31 I/O11  
    30 I/O10  
    29 I/O9  
    28 N.C  
    27 A14  
    26 A13  
    25 A12  
    24 A11  
    23 A10  
    A17  
    N.C  
    A14  
    A12  
    A9  
    A7  
    I/O4 10  
    Vcc 11  
    Vss 12  
    I/O5 13  
    I/O6 14  
    I/O7 15  
    I/O8 16  
    WE 17  
    A5 18  
    SOJ/  
    TSOP2  
    Vcc  
    I/O7  
    I/O8  
    N.C  
    A16  
    A15  
    A13  
    A10  
    Vss  
    I/O15  
    I/O16  
    N.C  
    G
    H
    A11  
    A6 19  
    A7 20  
    48-CSP  
    A8 21  
    A9 22  
    PIN FUNCTION  
    Pin Name  
    A0 - A17  
    WE  
    Pin Function  
    Address Inputs  
    Write Enable  
    Chip Select  
    CS  
    OE  
    Output Enable  
    LB  
    Lower-byte Control(I/O1~I/O8)  
    Upper-byte Control(I/O9~I/O16)  
    Data Inputs/Outputs  
    Power(+3.3V)  
    UB  
    I/O1 ~ I/O16  
    VCC  
    VSS  
    Ground  
    N.C  
    No Connection  
    ABSOLUTE MAXIMUM RATINGS*  
    Parameter  
    Voltage on Any Pin Relative to VSS  
    Voltage on VCC Supply Relative to VSS  
    Power Dissipation  
    Symbol  
    VIN, VOUT  
    VCC  
    Rating  
    Unit  
    -0.5 to 4.6  
    -0.5 to 4.6  
    1.0  
    V
    V
    PD  
    W
    °C  
    °C  
    °C  
    Storage Temperature  
    TSTG  
    TA  
    -65 to 150  
    0 to 70  
    Operating Temperature  
    Commercial  
    Industrial  
    TA  
    -40 to 85  
    * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and  
    functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.  
    Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
    Rev 5.0  
    September 2001  
    - 3 -  
    PRELIMPreliminaryPPPPPPPPPINARY  
    CMOS SRAM  
    K6R4016V1C-C/C-L, K6R4016V1C-I/C-P  
    RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)  
    Parameter  
    Supply Voltage  
    Symbol  
    Min  
    3.0  
    Typ  
    Max  
    Unit  
    V
    VCC  
    3.3  
    3.6  
    Ground  
    VSS  
    0
    0
    -
    0
    VCC+0.3***  
    0.8  
    V
    V
    Input High Voltage  
    Input Low Voltage  
    VIH  
    2.0  
    V
    VIL  
    -0.3**  
    -
    *
    The above parameters are also guaranteed at industrial temperature range.  
    ** VIL(Min) = -2.0V a.c(Pulse Width £ 8ns) for I £ 20mA.  
    *** VIH(Max) = VCC + 2.0V a.c (Pulse Width £ 8ns) for I £ 20mA.  
    DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc= 3.3±0.3V, unless otherwise specified)  
    Parameter  
    Symbol  
    Test Conditions  
    Min  
    -2  
    Max  
    2
    Unit  
    mA  
    Input Leakage Current  
    Output Leakage Current  
    ILI  
    VIN=VSS to VCC  
    ILO  
    CS=VIH or OE=VIH or WE=VIL  
    VOUT = VSS to VCC  
    -2  
    2
    mA  
    Operating Current  
    ICC  
    Min. Cycle, 100% Duty  
    CS=VIL, VIN=VIH or VIL, IOUT=0mA  
    Com.  
    Ind.  
    10ns  
    12ns  
    15ns  
    10ns  
    12ns  
    15ns  
    -
    160  
    150  
    140  
    175  
    165  
    155  
    60  
    mA  
    -
    -
    -
    -
    -
    Standby Current  
    ISB  
    Min. Cycle, CS=VIH  
    -
    mA  
    ISB1  
    f=0MHz, CS³ VCC-0.2V,  
    VIN³ VCC-0.2V or VIN£0.2V  
    Normal  
    L-ver  
    -
    -
    10  
    1.2  
    0.4  
    -
    Output Low Voltage Level  
    Output High Voltage Level  
    VOL  
    VOH  
    IOL=8mA  
    -
    V
    V
    IOH=-4mA  
    2.4  
    * The above parameters are also guaranteed at industrial temperature range.  
    CAPACITANCE*(TA=25°C, f=1.0MHz)  
    Item  
    Input/Output Capacitance  
    Input Capacitance  
    Symbol  
    Test Conditions  
    VI/O=0V  
    MIN  
    Max  
    8
    Unit  
    CI/O  
    -
    -
    pF  
    pF  
    CIN  
    VIN=0V  
    7
    * Capacitance is sampled and not 100% tested.  
    Rev 5.0  
    September 2001  
    - 4 -  
    PRELIMPreliminaryPPPPPPPPPINARY  
    CMOS SRAM  
    K6R4016V1C-C/C-L, K6R4016V1C-I/C-P  
    AC CHARACTERISTICS(TA=0 to 70°C, VCC=3.3±0.3V, unless otherwise noted.)  
    TEST CONDITIONS*  
    Parameter  
    Value  
    Input Pulse Levels  
    0V to 3V  
    3ns  
    Input Rise and Fall Times  
    Input and Output timing Reference Levels  
    Output Loads  
    1.5V  
    See below  
    * The above test conditions are also applied at industrial temperature range.  
    Output Loads(B)  
    for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ  
    Output Loads(A)  
    +3.3V  
    RL = 50W  
    DOUT  
    319W  
    VL = 1.5V  
    DOUT  
    30pF*  
    ZO = 50W  
    353W  
    5pF*  
    * Capacitive Load consists of all components of the  
    test environment.  
    * Including Scope and Jig Capacitance  
    READ CYCLE*  
    K6R4016V1C-10  
    K6R4016V1C-12  
    K6R4016V1C-15  
    Parameter  
    Symbol  
    Unit  
    Min  
    10  
    -
    Max  
    Min  
    12  
    -
    Max  
    Min  
    15  
    -
    Max  
    Read Cycle Time  
    tRC  
    tAA  
    -
    10  
    10  
    5
    5
    -
    -
    12  
    12  
    6
    6
    -
    -
    15  
    15  
    7
    7
    -
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    Address Access Time  
    Chip Select to Output  
    tCO  
    tOE  
    -
    -
    -
    Output Enable to Valid Output  
    UB, LB Access Time  
    -
    -
    -
    tBA  
    -
    -
    -
    Chip Enable to Low-Z Output  
    Output Enable to Low-Z Output  
    UB, LB Enable to Low-Z Output  
    Chip Disable to High-Z Output  
    Output Disable to High-Z Output  
    UB, LB Disable to High-Z Output  
    Output Hold from Address Change  
    tLZ  
    3
    3
    3
    tOLZ  
    tBLZ  
    tHZ  
    0
    -
    0
    -
    0
    -
    0
    -
    0
    -
    0
    -
    0
    5
    5
    5
    -
    0
    6
    6
    6
    -
    0
    7
    7
    7
    -
    tOHZ  
    tBHZ  
    tOH  
    0
    0
    0
    0
    0
    0
    3
    3
    3
    * The above parameters are also guaranteed at industrial temperature range.  
    Rev 5.0  
    September 2001  
    - 5 -  
    PRELIMPreliminaryPPPPPPPPPINARY  
    CMOS SRAM  
    K6R4016V1C-C/C-L, K6R4016V1C-I/C-P  
    WRITE CYCLE*  
    K6R4016V1C-10  
    K6R4016V1C-12  
    K6R4016V1C-15  
    Unit  
    Parameter  
    Symbol  
    Min  
    10  
    7
    Max  
    Min  
    12  
    8
    Max  
    Min  
    15  
    10  
    0
    Max  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    Write Cycle Time  
    tWC  
    tCW  
    tAS  
    -
    -
    -
    -
    -
    -
    -
    -
    5
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    6
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    7
    -
    -
    -
    Chip Select to End of Write  
    Address Set-up Time  
    0
    0
    Address Valid to End of Write  
    Write Pulse Width(OE High)  
    Write Pulse Width(OE Low)  
    UB, LB Valid to End of Write  
    Write Recovery Time  
    tAW  
    tWP  
    tWP1  
    tBW  
    tWR  
    tWHZ  
    tDW  
    tDH  
    7
    8
    10  
    10  
    15  
    10  
    0
    7
    8
    10  
    7
    12  
    8
    0
    0
    Write to Output High-Z  
    0
    0
    0
    Data to Write Time Overlap  
    Data Hold from Write Time  
    End Write to Output Low-Z  
    5
    6
    7
    0
    0
    0
    tOW  
    3
    3
    3
    * The above parameters are also guaranteed at industrial temperature range.  
    TIMING DIAGRAMS  
    TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB, LB=VIL)  
    tRC  
    Address  
    tAA  
    tOH  
    Valid Data  
    Data Out  
    Previous Valid Data  
    TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)  
    tRC  
    Address  
    tAA  
    tCO  
    tHZ(3,4,5)  
    CS  
    tBHZ(3,4,5)  
    tBA  
    UB, LB  
    OE  
    tBLZ(4,5)  
    tOHZ  
    tOE  
    tOLZ  
    tOH  
    tLZ(4,5)  
    Data out  
    High-Z  
    Valid Data  
    Rev 5.0  
    September 2001  
    - 6 -  
    PRELIMPreliminaryPPPPPPPPPINARY  
    CMOS SRAM  
    K6R4016V1C-C/C-L, K6R4016V1C-I/C-P  
    NOTES(READ CYCLE)  
    1. WE is high for read cycle.  
    2. All read cycle timing is referenced from the last valid address to the first transition address.  
    3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL  
    levels.  
    4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to  
    device.  
    5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.  
    6. Device is continuously selected with CS=VIL.  
    7. Address valid prior to coincident with CS transition low.  
    8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.  
    TIMING WAVEFORM OF WRITE CYCLE(1) (OE Clock)  
    tWC  
    Address  
    tAW  
    tWR(5)  
    OE  
    tCW(3)  
    CS  
    tBW  
    UB, LB  
    tAS(4)  
    tWP(2)  
    WE  
    tDW  
    tDH  
    High-Z  
    High-Z  
    Data in  
    Data out  
    Valid Data  
    tOHZ(6)  
    TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low fixed)  
    tWC  
    Address  
    tAW  
    tWR(5)  
    tCW(3)  
    tBW  
    CS  
    UB, LB  
    WE  
    tWP1(2)  
    tAS(4)  
    tDW  
    tDH  
    High-Z  
    Valid Data  
    High-Z  
    Data in  
    (9)  
    (10)  
    tWHZ(6)  
    tOW  
    Data out  
    Rev 5.0  
    September 2001  
    - 7 -  
    PRELIMPreliminaryPPPPPPPPPINARY  
    CMOS SRAM  
    K6R4016V1C-C/C-L, K6R4016V1C-I/C-P  
    TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)  
    tWC  
    Address  
    tAW  
    tWR(5)  
    tCW(3)  
    CS  
    tBW  
    UB, LB  
    tWP(2)  
    tAS(4)  
    WE  
    tDH  
    tDW  
    High-Z  
    High-Z  
    High-Z  
    Data in  
    Data out  
    Valid Data  
    tLZ  
    tWHZ(6)  
    High-Z(8)  
    TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)  
    tWC  
    Address  
    CS  
    tAW  
    tCW(3)  
    tWR(5)  
    tBW  
    UB, LB  
    tAS(4)  
    tWP(2)  
    WE  
    tDH  
    tDW  
    High-Z  
    Data in  
    Valid Data  
    tBLZ  
    tWHZ(6)  
    High-Z(8)  
    High-Z  
    Data out  
    NOTES(WRITE CYCLE)  
    1. All write cycle timing is referenced from the last valid address to the first transition address.  
    2. A write occurs during the overlap of a low CS,WE,LB and UB. A write begins at the latest transition CS going low and WE  
    going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write  
    to the end of write.  
    3. tCW is measured from the later of CS going low to end of write.  
    4. tAS is measured from the address valid to the beginning of write.  
    5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.  
    6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase  
    of the output must not . be applied because bus contention can occur.  
    7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.  
    8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.  
    9. Dout is the read data of the new address.  
    10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be  
    applied.  
    Rev 5.0  
    September 2001  
    - 8 -  
    PRELIMPreliminaryPPPPPPPPPINARY  
    CMOS SRAM  
    K6R4016V1C-C/C-L, K6R4016V1C-I/C-P  
    FUNCTIONAL DESCRIPTION  
    I/O Pin  
    CS  
    WE  
    OE  
    LB  
    UB  
    Mode  
    Supply Current  
    I/O1~I/O8  
    High-Z  
    I/O9~I/O16  
    High-Z  
    H
    L
    L
    L
    X
    H
    X
    H
    X*  
    H
    X
    X
    X
    H
    L
    X
    X
    H
    H
    L
    Not Select  
    ISB, ISB1  
    ICC  
    Output Disable  
    High-Z  
    High-Z  
    L
    Read  
    Write  
    DOUT  
    High-Z  
    DOUT  
    DIN  
    High-Z  
    DOUT  
    DOUT  
    High-Z  
    DIN  
    ICC  
    ICC  
    H
    L
    L
    L
    L
    X
    L
    H
    L
    H
    L
    High-Z  
    DIN  
    L
    DIN  
    * X means Don¢t Care.  
    DATA RETENTION CHARACTERISTICS*(TA=0 to 70°C)  
    Parameter  
    VCC for Data Retention  
    Data Retention Current  
    Symbol  
    VDR  
    Test Condition  
    CS ³ VCC - 0.2V  
    VCC=3.0V, CS³ VCC - 0.2V  
    Min.  
    2.0  
    -
    Typ.  
    Max.  
    3.6  
    Unit  
    -
    -
    V
    IDR  
    1.0  
    mA  
    VIN ³ VCC - 0.2V or VIN£0.2V  
    VCC=2.0V, CS³ VCC - 0.2V  
    VIN³ VCC - 0.2V or VIN£0.2V  
    -
    -
    0.7  
    Data Retention Set-Up Time  
    Recovery Time  
    tSDR  
    tRDR  
    See Data Retention  
    Wave form(below)  
    0
    5
    -
    -
    -
    -
    ns  
    ms  
    * The above parameters are also guaranteed at industrial temperature range.  
    Data Retention Characteristic is for L-ver only.  
    DATA RETENTION WAVE FORM  
    CS controlled  
    Data Retention Mode  
    tSDR  
    tRDR  
    VCC  
    3.0V  
    VIH  
    VDR  
    CS³ VCC - 0.2V  
    CS  
    GND  
    Rev 5.0  
    September 2001  
    - 9 -  
    PRELIMPreliminaryPPPPPPPPPINARY  
    CMOS SRAM  
    K6R4016V1C-C/C-L, K6R4016V1C-I/C-P  
    PACKAGE DIMENSIONS  
    Units:millimeters/Inches  
    44-SOJ-400  
    #44  
    #23  
    9.40 ±0.25  
    0.370 ±0.010  
    11.18 ±0.12  
    0.440 ±0.005  
    +0.10  
    0.20  
    -0.05  
    0.008+0.004  
    -0.002  
    #1  
    #22  
    28.98  
    MAX  
    1.141  
    0.69  
    MIN  
    0.027  
    25.58 ±0.12  
    1.125 ±0.005  
    1.19  
    (
    (
    )
    0.047  
    3.76  
    0.148  
    1.27  
    MAX  
    )
    0.050  
    0.10  
    0.004  
    MAX  
    +0.10  
    -0.05  
    0.43  
    +0.10  
    -0.05  
    0.71  
    0.017 +0.004  
    0.95  
    0.0375  
    1.27  
    0.050  
    -0.002  
    (
    )
    0.028 +0.004  
    -0.002  
    44-TSOP2-400BF  
    Units:millimeters/Inches  
    0~8°  
    0.25  
    0.010  
    TYP  
    #23  
    #44  
    0.45 ~0.75  
    0.018 ~ 0.030  
    11.76 ±0.20  
    0.463 ±0.008  
    0.50  
    0.020  
    (
    )
    #1  
    #22  
    18.81  
    0.741  
    MAX  
    + 0.075  
    - 0.035  
    + 0.003  
    - 0.001  
    0.125  
    0.005  
    18.41 ±0.10  
    0.725 ±0.004  
    1.00 ±0.10  
    0.039 ±0.004  
    1.20  
    0.047  
    MAX  
    0.10  
    0.004  
    MAX  
    +0.10  
    - 0.05  
    +0.004  
    - 0.002  
    0.05  
    0.30  
    MIN  
    0.002  
    0.80  
    0.0315  
    0.805  
    0.032  
    (
    )
    0.012  
    Rev 5.0  
    September 2001  
    - 10  
    PRELIMPreliminaryPPPPPPPPPINARY  
    CMOS SRAM  
    K6R4016V1C-C/C-L, K6R4016V1C-I/C-P  
    PACKAGE DIMENSIONS  
    Units : millimeter.  
    Top View  
    Bottom View  
    B
    A1 INDEX MARK  
    0.50  
    B
    B1  
    0.50  
    6
    5
    4
    3
    2
    1
    A
    B
    #A1  
    C
    D
    E
    F
    G
    H
    B/2  
    Detail A  
    A
    Side View  
    D
    Y
    C
    Min  
    Typ  
    0.75  
    9.00  
    3.75  
    9.00  
    5.25  
    0.35  
    1.05  
    0.80  
    0.25  
    -
    Max  
    -
    A
    B
    -
    Notes.  
    8.90  
    9.10  
    -
    1. Bump counts: 48(8row x 6column)  
    2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)  
    3. All tolerence are +/-0.050 unless  
    otherwise specified.  
    B1  
    C
    -
    8.90  
    9.10  
    -
    C1  
    D
    -
    4. Typ : Typical  
    0.30  
    0.40  
    1.20  
    -
    5. Y is coplanarity: 0.08(Max)  
    E
    -
    E1  
    E2  
    Y
    -
    0.20  
    -
    0.30  
    0.08  
    Rev 5.0  
    September 2001  
    - 11  
    配单直通车
    K6R4016V1C-TI15产品参数
    型号:K6R4016V1C-TI15
    是否无铅： 含铅
    是否Rohs认证： 不符合
    生命周期：Obsolete
    IHS 制造商：SAMSUNG SEMICONDUCTOR INC
    零件包装代码：TSOP2
    包装说明：TSOP2, TSOP44,.46,32
    针数：44
    Reach Compliance Code：unknown
    ECCN代码：3A991.B.2.A
    HTS代码：8542.32.00.41
    风险等级：5.89
    最长访问时间：15 ns
    I/O 类型：COMMON
    JESD-30 代码：R-PDSO-G44
    JESD-609代码：e0
    长度：18.41 mm
    内存密度：4194304 bit
    内存集成电路类型：STANDARD SRAM
    内存宽度：16
    功能数量：1
    端子数量：44
    字数：262144 words
    字数代码：256000
    工作模式：ASYNCHRONOUS
    最高工作温度：85 °C
    最低工作温度：-40 °C
    组织：256KX16
    输出特性：3-STATE
    封装主体材料：PLASTIC/EPOXY
    封装代码：TSOP2
    封装等效代码：TSOP44,.46,32
    封装形状：RECTANGULAR
    封装形式：SMALL OUTLINE, THIN PROFILE
    并行/串行：PARALLEL
    峰值回流温度（摄氏度）：NOT SPECIFIED
    电源：3.3 V
    认证状态：Not Qualified
    座面最大高度：1.2 mm
    最大待机电流：0.0007 A
    最小待机电流：2 V
    子类别：SRAMs
    最大压摆率：0.155 mA
    最大供电电压 (Vsup)：3.6 V
    最小供电电压 (Vsup)：3 V
    标称供电电压 (Vsup)：3.3 V
    表面贴装：YES
    技术：CMOS
    温度等级：INDUSTRIAL
    端子面层：Tin/Lead (Sn/Pb)
    端子形式：GULL WING
    端子节距：0.8 mm
    端子位置：DUAL
    处于峰值回流温度下的最长时间：NOT SPECIFIED
    宽度：10.16 mm
    Base Number Matches：1
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