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产品型号K6R4016V1D-UI10的概述

K6R4016V1D-UI10 芯片的概述 K6R4016V1D-UI10 是一个高性能的动态随机存取存储器（DRAM）的型号，属于三星半导体公司生产的一系列快速存储器产品。这种DRAM芯片被广泛应用于计算机、消费电子和嵌入式系统等领域，以其高存储能力和快速响应特性满足现代电子设备的需求。K6R4016V1D-UI10 具体是一种16M x 4位的SDRAM，具有较高的性能和可靠性，适合用于需要大量存储和快速读写操作的应用。 K6R4016V1D-UI10 的详细参数 K6R4016V1D-UI10 的主要参数如下： - 存储容量: 16Mb (16M x 4位) - 存储类型: SDRAM - 工作电压: 3.3V - 数据传输速度: 133MHz - 接口类型: SRAM与标准DRAM互补 - 封装类型: TSOP-II - 引脚数量: 44针 - 最高时钟频率: 166MHz -...

产品型号K6R4016V1D-UI10的Datasheet PDF文件预览

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016V1D

Document Title

256Kx16 Bit High Speed Static RAM(3.3V Operating).

Operated at Commercial and Industrial Temperature Ranges.

Revision History

RevNo.

Rev. 0.0

Rev. 0.1

Rev. 0.2

Rev. 0.3

History

Draft Data

Remark

Initial release with Preliminary.

Add Low Ver.

Aug. 20. 2001

Sep. 19. 2001

Sep. 28. 2001

Oct. 09. 2001

Preliminary

Package dimensions modify on page 11.

Change ICC , ISB, ISB1

Item

Current

80mA

65mA

55mA

45mA

100mA

85mA

75mA

65mA

20mA

1.2mA

8ns

110mA

90mA

80mA

70mA

130mA

115mA

100mA

85mA

30mA

0.5mA

10ns

12ns

15ns

8ns

10ns

12ns

15ns

ICC(Commercial)

ICC(Industrial)

ISB

ISB1(L-ver.)

Rev. 0.4

Rev. 1.0

1. Correct AC parameters : Read & Write Cycle

2. Change Data Retention Current :

from 0.45mA to 1.1mA when Vcc=3.0V

from 0.35mA to 0.9mA when Vcc=2.0V

3. Limit L-Ver. to 48 TBGA Package

Nov.23. 2001

Dec.18. 2001

Preliminary

1. Delete 12ns,15ns speed bin.

2. Change Icc for Industrial mode.

Final

Item

100mA

85mA

Current

90mA

75mA

8ns

10ns

ICC(Industrial)

Rev. 2.0

Rev. 2.1

Rev. 2.2

Rev. 2.3

Rev. 3.0

Rev. 4.0

1. Add tBA,tBLZ,tBHZ,tBW AC parematers.

1. Correct the Package dimensions(48-TBGA)

1. Add the tPU and tPD into the waveform.

1. Change the current parameters (Isb1 L-ver, Idr)

1. Add the Lead Free Package type.

Feb. 14. 2002

Oct. 23. 2002

Mar. 10, 2003

Final

June. 12, 2003 Final

June. 20, 2003 Final

1. Change the Idr parameters

Mar. 15, 2004

Final

1.2mA

1.8mA

Current

1.4mA

2.0mA

Idr(2V)

Idr(3V)

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

Rev 4.0

Mar. 2004

- 1 -

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016V1D

4Mb Async. Fast SRAM Ordering Information

Org.

Part Number

K6R4004C1D-J(K)C(I) 10

K6R4004V1D-J(K)C(I) 08/10

K6R4008C1D-J(K,T,U)C(I) 10

VDD(V)

Speed ( ns )

PKG

Temp. & Power

3.3

8/10

J : 32-SOJ

1M x4

K : 32-SOJ(LF) C : Commercial Temperature

,Normal Power Range

I : Industrial Temperature

,Normal Power Range

L : Commercial Temperature

,Low Power Range

P : Industrial Temperature

,Low Power Range

J : 36-SOJ

K : 36-SOJ(LF)

T : 44-TSOP2

U : 44-TSOP2(LF)

512K x8

K6R4008V1D-J(K,T,U)C(I) 08/10

K6R4016C1D-J(K,T,U,E)C(I) 10

K6R4016V1D-J(K,T,U,E)C(I,L,P) 08/10

3.3

8/10

J : 44-SOJ

K : 44-SOJ(LF)

T : 44-TSOP2

U : 44-TSOP2(LF)

E : 48-TBGA

256K x16

3.3

8/10

Rev 4.0

Mar. 2004

- 2 -

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016V1D

256K x 16 Bit High-Speed CMOS Static RAM

FEATURES

GENERAL DESCRIPTION

• Fast Access Time 8,10ns(Max.)

The K6R4016V1D is a 4,194,304-bit high-speed Static Random

Access Memory organized as 262,144 words by 16 bits. The

K6R4016V1D uses 16 common input and output lines and has

an output enable pin which operates faster than address

access time at read cycle. Also it allows that lower and upper

byte access by data byte control(UB, LB). The device is fabri-

cated using SAMSUNG′s advanced CMOS process and

designed for high-speed circuit technology. It is particularly well

suited for use in high-density high-speed system applications.

The K6R4016V1D is packaged in a 400mil 44-pin plastic SOJ

or TSOP(II) forward or 48 TBGA.

• Low Power Dissipation

Standby (TTL) : 20mA(Max.)

(CMOS) : 5mA(Max.)

1.2mA(Max.)L-Ver. only.

Operating K6R4016V1D-08 : 80mA(Max.)

K6R4016V1D-10 : 65mA(Max.)

• Single 3.3 ±0.3V Power Supply

• TTL Compatible Inputs and Outputs

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• 2V Minimum Data Retention: L-Ver. only.

• Center Power/Ground Pin Configuration

• Data Byte Control : LB : I/O1~ I/O8, UB : I/O9~ I/O16

• Standard Pin Configuration

K6R4016V1D-J : 44-SOJ-400

K6R4016V1D-K : 44-SOJ-400(Lead-Free)

K6R4016V1D-T : 44-TSOP2-400BF

K6R4016V1D-U : 44-TSOP2-400BF (Lead-Free)

K6R4016V1D-E : 48-TBGA with 0.75 Ball pitch

(7mm X 9mm)

• Operating in Commercial and Industrial Temperature range.

FUNCTIONAL BLOCK DIAGRAM

Clk Gen.

Pre-Charge Circuit

Memory Array

1024 Rows

256 x 16 Columns

Data

Cont.

I/O Circuit &

Column Select

I/O1~I/O8

Data

Cont.

I/O9~I/O16

Gen.

CLK

A10 A11 A12 A13 A14 A15 A16 A17

Rev 4.0

Mar. 2004

- 3 -

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016V1D

PIN CONFIGURATION (Top View)

44 A17

43 A16

42 A15

41 OE

N.C

I/O9

I/O10

Vcc

I/O1

40 UB

I/O1

I/O2

I/O3

39 LB

I/O2

Vss

I/O3

I/O4

I/O5

I/O6

N.C

I/O11

I/O12

I/O13

I/O14

38 I/O16

37 I/O15

36 I/O14

35 I/O13

34 Vss

33 Vcc

32 I/O12

31 I/O11

30 I/O10

29 I/O9

28 N.C

27 A14

26 A13

25 A12

24 A11

23 A10

A17

N.C

A14

A12

I/O4 10

Vcc 11

Vss 12

I/O5 13

I/O6 14

I/O7 15

I/O8 16

WE 17

A5 18

SOJ/

TSOP2

Vcc

I/O7

I/O8

N.C

A16

A15

A13

A10

Vss

I/O15

I/O16

N.C

A11

A6 19

A7 20

48-TBGA

A8 21

A9 22

PIN FUNCTION

Pin Name

A0 - A17

Pin Function

Address Inputs

Write Enable

Chip Select

Output Enable

Lower-byte Control(I/O1~I/O8)

Upper-byte Control(I/O9~I/O16)

Data Inputs/Outputs

Power(+3.3V)

I/O1 ~ I/O16

VCC

VSS

Ground

N.C

No Connection

ABSOLUTE MAXIMUM RATINGS*

Parameter

Symbol

VIN, VOUT

VCC

Rating

Unit

Voltage on Any Pin Relative to VSS

Voltage on VCC Supply Relative to VSS

Power Dissipation

-0.5 to 4.6

1.0

°C

Storage Temperature

TSTG

-65 to 150

0 to 70

Operating Temperature

Commercial

Industrial

-40 to 85

* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Rev 4.0

Mar. 2004

- 4 -

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016V1D

RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)

Parameter

Symbol

Min

Typ

Max

Unit

Supply Voltage

VCC

3.0

3.3

3.6

Ground

VSS

Input High Voltage

Input Low Voltage

VIH

2.0

VCC+0.3***

0.8

VIL

-0.3**

The above parameters are also guaranteed at industrial temperature range.

** V^IL(Min) = -2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA.

*** VIH(Max) = VCC + 2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA.

DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)

Parameter

Symbol

Test Conditions

Min

Max

Unit

µA

Input Leakage Current

Output Leakage Current

ILI

VIN=VSS to VCC

-2

ILO

CS=VIH or OE=VIH or WE=VIL

VOUT=VSS to VCC

-2

µA

Operating Current

Standby Current

ICC

Min. Cycle, 100% Duty

CS=VIL, VIN=VIH or VIL, IOUT=0mA

Com.

Ind.

8ns

10ns

8ns

10ns

ISB

Min. Cycle, CS=VIH

ISB1

f=0MHz, CS≥VCC-0.2V,

VIN≥VCC-0.2V or VIN≤0.2V

Normal

L-ver.**

2.4

0.4

Output Low Voltage Level

Output High Voltage Level

VOL

VOH

IOL=8mA

IOH=-4mA

2.4

* The above parameters are also guaranteed at industrial temperature range.

** L-var is only supported with TBGA package type.

CAPACITANCE*(TA=25°C, f=1.0MHz)

Item

Input/Output Capacitance

Input Capacitance

Symbol

CI/O

Test Conditions

VI/O=0V

TYP

Max

Unit

CIN

VIN=0V

* Capacitance is sampled and not 100% tested.

Rev 4.0

Mar. 2004

- 5 -

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016V1D

AC CHARACTERISTICS(TA=0 to 70°C, VCC=3.3±0.3V, unless otherwise noted.)

TEST CONDITIONS*

Parameter

Value

Input Pulse Levels

0V to 3V

3ns

Input Rise and Fall Times

Input and Output timing Reference Levels

Output Loads

1.5V

See below

* The above test conditions are also applied at industrial temperature range.

Output Loads(B)

for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ

Output Loads(A)

+3.3V

RL = 50Ω

DOUT

319Ω

VL = 1.5V

DOUT

30pF*

ZO = 50Ω

353Ω

5pF*

* Capacitive Load consists of all components of the

test environment.

* Including Scope and Jig Capacitance

READ CYCLE*

K6R4016V1D-08

K6R4016V1D-10

Min Max

Parameter

Symbol

Unit

Min

Max

Read Cycle Time

tRC

tAA

Address Access Time

Chip Select to Output

tCO

tOE

tBA

Output Enable to Valid Output

UB, LB Access Time

Chip Enable to Low-Z Output

Output Enable to Low-Z Output

UB, LB Enable to Low-Z Output

Chip Disable to High-Z Output

Output Disable to High-Z Output

UB, LB Disable to High-Z Output

Output Hold from Address Change

Chip Selection to Power Up Time

Chip Selection to Power DownTime

tLZ

tOLZ

tBLZ

tHZ

tOHZ

tBHZ

tOH

tPU

tPD

* The above parameters are also guaranteed at industrial temperature range.

Rev 4.0

Mar. 2004

- 6 -

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016V1D

WRITE CYCLE*

Parameter

K6R4016V1D-08

Max

K6R4016V1D-10

Max

Symbol

Unit

Min

Write Cycle Time

tWC

tCW

tAS

Chip Select to End of Write

Address Set-up Time

Address Valid to End of Write

Write Pulse Width(OE High)

Write Pulse Width(OE Low)

UB, LB Valid to End of Write

Write Recovery Time

tAW

tWP

tWP1

tBW

tWR

tWHZ

tDW

tDH

Write to Output High-Z

Data to Write Time Overlap

Data Hold from Write Time

End of Write to Output Low-Z

tOW

* The above parameters are also guaranteed at industrial temperature range.

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB, LB=VIL)

tRC

Address

tAA

tOH

Valid Data

Data Out

Previous Valid Data

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tAA

tCO

tHZ(3,4,5)

tBHZ(3,4,5)

tBA

UB, LB

tBLZ(4,5)

tOHZ

tOE

tOLZ

tOH

tLZ(4,5)

Data out

High-Z

Valid Data

tPU

tPD

ICC

ISB

VCC

50%

Current

Rev 4.0

Mar. 2004

- 7 -

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016V1D

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. t^HZand tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL

levels.

4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to

device.

5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

6. Device is continuously selected with CS=VIL.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

TIMING WAVEFORM OF WRITE CYCLE(1) (OE Clock)

tWC

Address

tAW

tWR(5)

tCW(3)

tBW

UB, LB

tAS(4)

tWP(2)

tDW

tDH

High-Z

Data in

Data out

Valid Data

tOHZ(6)

TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low fixed)

tWC

Address

tAW

tWR(5)

tCW(3)

tBW

UB, LB

tWP1(2)

tAS(4)

tDW

tDH

High-Z

Valid Data

Data in

(9)

(10)

tWHZ(6)

tOW

High-Z

Data out

Rev 4.0

Mar. 2004

- 8 -

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016V1D

TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)

tWC

Address

tAW

tWR(5)

tCW(3)

tBW

UB, LB

tAS(4)

tWP(2)

tDH

tDW

High-Z

Data in

Valid Data

tLZ

tWHZ(6)

High-Z(8)

High-Z

Data out

TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)

tWC

Address

tAW

tCW(3)

tWR(5)

tBW

UB, LB

tAS(4)

tWP(2)

tDH

tDW

High-Z

Data in

Valid Data

tBLZ

tWHZ(6)

High-Z(8)

High-Z

Data out

NOTES(WRITE CYCLE)

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CS,WE,LB and UB. A write begins at the latest transition CS going low and WE

going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write

to the end of write.

3. t^CWis measured from the later of CS going low to end of write.

4. t^ASis measured from the address valid to the beginning of write.

5. t^WRis measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase

of the output must not . be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.

9. Dout is the read data of the new address.

10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be

applied.

Rev 4.0

Mar. 2004

- 9 -

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016V1D

FUNCTIONAL DESCRIPTION

I/O Pin

Mode

Supply Current

I/O1~I/O8

High-Z

I/O9~I/O16

High-Z

Not Select

ISB, ISB1

ICC

Output Disable

High-Z

Read

Write

DOUT

High-Z

DOUT

DIN

High-Z

DOUT

High-Z

DIN

ICC

High-Z

DIN

* X means Don′t Care.

DATA RETENTION CHARACTERISTICS*(TA=0 to 70°C)

Parameter

VCC for Data Retention

Data Retention Current

Symbol

VDR

Test Condition

CS ≥VCC - 0.2V

Min.

Typ.

Max.

Unit

2.0

3.6

IDR

VCC=3.0V, CS≥VCC - 0.2V

VIN ≥ VCC - 0.2V or VIN≤0.2V

2.0

1.4

VCC=2.0V, CS≥VCC - 0.2V

VIN≥VCC - 0.2V or VIN≤0.2V

Data Retention Set-Up Time

Recovery Time

tSDR

tRDR

See Data Retention

Wave form(below)

* The above parameters are also guaranteed at industrial temperature range.

Data Retention Characteristic is for L-ver only.

DATA RETENTION WAVE FORM

CS controlled

Data Retention Mode

tSDR

tRDR

VCC

3.0V

VIH

VDR

CS≥VCC - 0.2V

GND

Rev 4.0

Mar. 2004

- 10

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016V1D

PACKAGE DIMENSIONS

44-SOJ-400

Units:millimeters/Inches

#44

#23

9.40 ±0.25

0.370 ±0.010

11.18 ±0.12

0.440 ±0.005

+0.10

-0.05

0.20

0.008 ^+0.004

-0.002

#22

28.98

1.141

0.69

0.027

MAX

MIN

25.58 ±0.12

1.125 ±0.005

1.19

0.047

1.27

(

)

3.76

0.148

MAX

(

)

0.050

0.10

MAX

0.004

+0.10

-0.05

0.43

+0.10

-0.05

0.71

0.017 ^+0.004

0.95

0.0375

1.27

0.050

-0.002

(

)

0.028 ^+0.004

-0.002

44-TSOP2-400BF

Units:millimeters/Inches

0~8°

0.25

0.010

TYP

#23

#44

0.45 ~0.75

0.018 ~ 0.030

11.76 ±0.20

0.463 ±0.008

0.50

0.020

(

)

#22

18.81

0.741

MAX

+ 0.075

- 0.035

+ 0.003

- 0.001

0.125

0.005

18.41 ±0.10

0.725 ±0.004

1.00 ±0.10

0.039 ±0.004

1.20

0.047

MAX

0.10

0.004

MAX

+0.10

−0.05

+0.004

−0.002

0.05

0.002

0.30

MIN

0.80

0.0315

0.805

0.032

(

)

0.012

Rev 4.0

Mar. 2004

- 11

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016V1D

PACKAGE DIMENSIONS

Units : millimeter.

Top View

Bottom View

A1 INDEX MARK

0.50

#A1

B/2

Detail A

Side View

Min

Typ

Max

6.90

0.75

7.00

3.75

9.00

5.25

0.45

0.90

0.55

0.35

Notes.

7.10

1. Bump counts: 48(8row x 6column)

2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)

3. All tolerence are +/-0.050 unless

otherwise specified.

8.90

9.10

4. Typ : Typical

0.40

0.80

0.50

1.00

5. Y is coplanarity: 0.08(Max)

0.30

0.40

0.08

Rev 4.0

Mar. 2004

- 12

K6R4016V1D-UI10相关文章

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K6R4016V1D-UI10产品参数

型号:	K6R4016V1D-UI10
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Obsolete
零件包装代码：	TSOP2
包装说明：	0.400 INCH, LEAD FREE, TSOP2-44
针数：	44
Reach Compliance Code：	unknown
风险等级：	5.79
最长访问时间：	10 ns
其他特性：	LG-MAX
I/O 类型：	COMMON
JESD-30 代码：	R-PDSO-G44
JESD-609代码：	e6
长度：	18.81 mm
内存密度：	4194304 bit
内存集成电路类型：	STANDARD SRAM
内存宽度：	16
湿度敏感等级：	3
功能数量：	1
端子数量：	44
字数：	262144 words
字数代码：	256000
工作模式：	ASYNCHRONOUS
最高工作温度：	85 °C
最低工作温度：	-40 °C
组织：	256KX16
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP2
封装等效代码：	TSOP44,.46,32
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE
并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260
电源：	3.3 V
认证状态：	Not Qualified
座面最大高度：	1.2 mm
最大待机电流：	0.005 A
最小待机电流：	3 V
子类别：	SRAMs
最大压摆率：	0.075 mA
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Tin/Bismuth (Sn97Bi3)
端子形式：	GULL WING
端子节距：	0.8 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	40
宽度：	10.16 mm
Base Number Matches：	1

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