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产品型号K6T1008C2E-DB70的概述

芯片K6T1008C2E-DB70概述 K6T1008C2E-DB70是一款由韩国三星电子（Samsung Electronics）公司生产的动态随机存取存储器（DRAM）芯片。该芯片主要用于各种电子设备中，为系统提供高效的存储解决方案。作为一种高性能的存储器，K6T1008C2E-DB70在便携式设备和计算机应用中均广泛应用，其出色的存储性能和较低的功耗深受业界欢迎。芯片K6T1008C2E-DB70的详细参数 K6T1008C2E-DB70的技术规格促使它在多种领域内得到应用。以下是该芯片的一些关键参数： - 存储容量: 1 Megabit（1Mb） - 存储类型: DRAM - 内存结构: 64K x 16位 - 封装类型: TSOP II - 电源电压: 3.0V(±0.3V) - 工作温度范围: -40°C至+85°C - 操作频率: 133MHz（最大） - 数据传输速率...

产品型号K6T1008C2E-DB70的Datasheet PDF文件预览

K6T1008C2E Family

CMOS SRAM

Document Title

128Kx8 bit Low Power CMOS Static RAM

Revision History

Revision No. History

Draft Data

Remark

0.0

1.0

Design target

October 12, 1998

August 30, 1999

Preliminary

Final

Finalize

- Improve tWP form 55ns to 50ns for 70ns product.

- Remove 55ns speed bin from industrial product.

1.01

2.0

Errata correction

Revise

December 1, 1999

February 14, 2000

March 3, 2000

Final

3.0

Revise

- Add 55ns parts to industrial products.

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.

Revision 3.0

March 2000

K6T1008C2E Family

CMOS SRAM

128Kx8 bit Low Power CMOS Static RAM

FEATURES

GENERAL DESCRIPTION

· Process Technology: TFT

The K6T1008C2E families are fabricated by SAMSUNG¢s

advanced CMOS process technology. The families support

various operating temperature ranges and have various pack-

age types for user flexibility of system design. The families

also support low data retention voltage for battery back-up

operation with low data retention current.

· Organization: 128Kx8

· Power Supply Voltage: 4.5~5.5V

· Low Data Retention Voltage: 2V(Min)

· Three state output and TTL Compatible

· Package Type: 32-DIP-600, 32-SOP-525,

32-TSOP1-0820F/R

PRODUCT FAMILY

Power Dissipation

Product Family

Operating Temperature Vcc Range

Speed

PKG Type

Standby

(ISB1, Max)

Operating

(ICC2, Max)

K6T1008C2E-L

K6T1008C2E-B

K6T1008C2E-P

K6T1008C2E-F

50mA

10mA

50mA

15mA

32-DIP-600, 32-SOP-525

32-TSOP1-0820F/R

Commercial(0~70°C)

Industrial(-40~85°C)

4.5~5.5V

55¹⁾/70ns

50mA

32-SOP -525

32-TSOP1-0820F/R

1. The parameters are tested with 50pF test load

PIN DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

A11

Clk gen.

Precharge circuit.

A10

CS1

I/O8

I/O7

I/O6

I/O5

I/O4

VSS

I/O3

I/O2

I/O1

A13

CS2

A15

VCC

A16

A14

A12

VCC

A15

CS2

N.C

A16

A14

A12

32-TSOP

Type1-Forward

Memory array

1024 rows

128´ 8 columns

Raw

Address

Row

select

A13

32-SOP

32-DIP

A11

A10

CS1

I/O8

I/O7

I/O6

I/O5

I/O4

A12

A14

A16

VCC

A15

CS2

A13

I/O1

I/O2

I/O3

VSS

I/O4

I/O5

I/O6

I/O7

I/O8

CS1

A10

Data

cont

I/O Circuit

I/O1

I/O8

I/O1

I/O2

I/O3

VSS

32-TSOP

Type1-Reverse

Column select

Data

cont

A11

Column Address

Name

CS1, CS2

Function

Chip Select Input

Output Enable Input

Write Enable Input

Data Inputs/Outputs

Address Inputs

Power

CS1

Control

logic

CS2

I/O1~I/O8

A0~A16

Vcc

Vss

Ground

N.C.

No Connection

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Revision 3.0

March 2000

K6T1008C2E Family

CMOS SRAM

PRODUCT LIST

Commercial Temperature Products(0~70°C)

Industrial Temperature Products(-40~85°C)

Part Name

Function

Part Name

Function

K6T1008C2E-DL55

K6T1008C2E-DL70

K6T1008C2E-DB55

K6T1008C2E-DB70

32-DIP, 55ns, Low Power

32-DIP, 70ns, Low Power

32-DIP, 55ns, Low Low Power

32-DIP, 70ns, Low Low Power

K6T1008C2E-GP55

K6T1008C2E-GP70

K6T1008C2E-GF55

K6T1008C2E-GF70

32-SOP, 55ns, Low Power

32-SOP, 70ns, Low Power

32-SOP, 55ns, Low Low Power

32-SOP, 70ns, Low Low Power

K6T1008C2E-GL55

K6T1008C2E-GL70

K6T1008C2E-GB55

K6T1008C2E-GB70

32-SOP, 55ns, Low Power

32-SOP, 70ns, Low Power

32-SOP, 55ns, Low Low Power

32-SOP, 70ns, Low Low Power

K6T1008C2E-TF55

K6T1008C2E-TF70

K6T1008C2E-RF55

K6T1008C2E-RF70

32-TSOP F, 55ns, Low Low Power

32-TSOP F, 70ns, Low Low Power

32-TSOP R, 55ns, Low Low Power

32-TSOP R, 70ns, Low Low Power

K6T1008C2E-TB55

K6T1008C2E-TB70

K6T1008C2E-RB55

K6T1008C2E-RB70

32-TSOP F, 55ns, Low Low Power

32-TSOP F, 70ns, Low Low Power

32-TSOP R, 55ns, Low Low Power

32-TSOP R, 70ns, Low Low Power

FUNCTIONAL DESCRIPTION

CS1

CS2

I/O

Mode

Power

Standby

Active

X¹⁾

High-Z

Deselected

X¹⁾

High-Z

Dout

Din

Output Disabled

Read

Active

X¹⁾

Write

Active

1. X means don¢t care (Must be in high or low states)

ABSOLUTE MAXIMUM RATINGS¹⁾

Item

Symbol

Ratings

Unit

Remark

Voltage on any pin relative to Vss

Voltage on Vcc supply relative to Vss

Power Dissipation

VIN,VOUT

VCC

-0.5 to 7.0

1.0

Storage temperature

TSTG

-65 to 150

0 to 70

°C

K6T1008C2E-L/-B

K6T1008C2E-P/-F

Operating Temperature

-40 to 85

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Revision 3.0

March 2000

K6T1008C2E Family

CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS¹⁾

Item

Supply voltage

Ground

Symbol

Vcc

Product

Min

4.5

Typ

Max

5.5

Unit

K6T1008C2E Family

All Family

5.0

Vss

Vcc+0.5²⁾

0.8

Input high voltage

Input low voltage

Note:

VIH

K6T1008C2E Family

2.2

-0.5³⁾

VIL

1. Commercial Product: TA=0 to 70°C

Industrial Product: TA=-40 to 85°C, otherwise specified.

2. Overshoot: Vcc+3.0V in case of pulse width£30ns.

3. Undershoot: -3.0V in case of pulse width£30ns.

4. Overshoot and undershoot are sampled, not 100% tested.

)

CAPACITANCE (f=1MHz, TA=25°C)

Item

Input capacitance

Symbol

Test Condition

Min

Max

Unit

CIN

CIO

VIN=0V

VIO=0V

Input/Output capacitance

1. Capacitance is sampled, not 100% tested

DC AND OPERATING CHARACTERISTICS

Item

Symbol

ILI

Test Conditions

Min Typ Max Unit

Input leakage current

VIN=Vss to Vcc

-1

Output leakage current

Operating power supply current

ILO

CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc

IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL, Read

ICC

10 mA

50 mA

Cycle time=1ms, 100%duty, IIO=0mA, CS¹£0.2V, CS2³ Vcc-0.2V, VIN£0.2V

or VIN³ VCC-0.2V

ICC1

Average operating current

Cycle time=Min, 100% duty, IIO=0mA, CS¹=VIL, CS2=VIH, VIN=VIH or VIL

IOL=2.1mA

ICC2

VOL

VOH

ISB

Output low voltage

2.4

0.4

Output high voltage

Standby Current(TTL)

Standby Current(CMOS)

IOH=-1.0mA

CS1=VIH, CS2=VIL, Other inputs=VIH or VIL

CS1³ Vcc-0.2V, CS2³ Vcc-0.2V or CS2£0.2V, Other inputs=0~Vcc

50¹⁾

ISB1

1. 50mA for Low power product, in case of Low Low power products are comercial=10mA, industrial=15mA.

Revision 3.0

March 2000

K6T1008C2E Family

CMOS SRAM

AC OPERATING CONDITIONS

TEST CONDITIONS( Test Load and Input/Output Reference)

Input pulse level: 0.8 to 2.4V

Input rising and falling time: 5ns

Input and output reference voltage:1.5V

Output load(see right): CL=100pF+1TTL

CL=50pF+1TTL

1. Including scope and jig capacitance

AC CHARACTERISTICS (VCC=4.5~5.5V, Commercial Product: TA=0 to 70°C, Industrial Product: TA=-40 to 85°C)

Speed Bins

Parameter List

Symbol

Units

55ns

70ns

Min

Max

Min

Max

Read Cycle Time

tRC

tAA

Address Access Time

Chip Select to Output

tCO

tOE

Output Enable to Valid Output

Chip Select to Low-Z Output

Output Enable to Low-Z Output

Chip Disable to High-Z Output

Output Disable to High-Z Output

Output Hold from Address Change

Write Cycle Time

Read

tLZ

tOLZ

tHZ

tOHZ

tOH

tWC

tCW

tAS

Chip Select to End of Write

Address Set-up Time

Address Valid to End of Write

Write Pulse Width

tAW

tWP

tWR

tWHZ

tDW

tDH

Write

Write Recovery Time

Write to Output High-Z

Data to Write Time Overlap

Data Hold from Write Time

End Write to Output Low-Z

tOW

DATA RETENTION CHARACTERISTICS

Item

Symbol

Test Condition

Min

Typ

Max

Unit

CS1³ Vcc-0.2V¹⁾

Vcc for data retention

VDR

2.0

5.5

K6T1008C2E-L

K6T1008C2E-B

K6T1008C2E-P

K6T1008C2F-F

Vcc=3.0V, CS1³ Vcc-0.2V¹⁾

Data retention current

IDR

Data retention set-up time

Recovery time

tSDR

tRDR

See data retention waveform

1. CS¹³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 controlled) or CS2£0.2V(CS2 controlled)

Revision 3.0

March 2000

K6T1008C2E Family

CMOS SRAM

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)

tRC

Address

tAA

tOH

Data Valid

Data Out

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tOH

tAA

tCO1

CS1

tHZ(1,2)

CS2

tCO2

tOE

tOHZ

tOLZ

tLZ

High-Z

Data out

Data Valid

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

Revision 3.0

March 2000

K6T1008C2E Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

tWC

Address

tCW(2)

tWR(4)

CS1

tAW

CS2

tCW(2)

tWP(1)

tAS(3)

tDW

tDH

Data Valid

Data in

tWHZ

tOW

Data Undefined

Data out

TIMING WAVEFORM OF WRITE CYCLE(2) (CS¹Controlled)

tWC

Address

CS1

tCW(2)

tAS(3)

tWR(4)

tAW

CS2

tWP(1)

tDW

tDH

Data in

Data out

Data Valid

High-Z

Revision 3.0

March 2000

K6T1008C2E Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)

tWC

Address

CS1

tAS(3)

tCW(2)

tWR(4)

tAW

CS2

tCW(2)

tWP(1)

tDH

tDW

Data in

Data Valid

High-Z

Data out

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,

CS2 going high and WE going low: A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,

tWP is measured from the begining of write to the end of write.

2. tCW is measured from the CS¹going low or CS2 going high to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends as CS1 or WE going high tWR2 applied

in case a write ends as CS2 going to low.

DATA RETENTION WAVE FORM

CS1 controlled

Data Retention Mode

tSDR

tRDR

VCC

4.5V

2.2V

VDR

CS³ VCC - 0.2V

CS1

GND

CS2 controlled

Data Retention Mode

VCC

4.5V

CS2

tSDR

tRDR

VDR

CS2£0.2V

0.4V

GND

Revision 3.0

March 2000

K6T1008C2E Family

CMOS SRAM

PACKAGE DIMENSIONS

32 DUAL INLINE PACKAGE (600mil)

Units: millimeters(inches)

+0.10

0.25

-0.05

+0.004

-0.002

0.010

#32

#17

13.60±0.20

0.535±0.008

#16

0~15°

3.81±0.20

0.150±0.008

42.31

1.666

MAX

5.08

0.200

MAX

41.91±0.20

1.650±0.008

3.30±0.30

0.130±0.012

0.46±0.10

0.018±0.004

0.38

MIN

1.91

0.075

1.52±0.10

0.060±0.004

2.54

0.100

(

)

0.015

32 PLASTIC SMALL OUTLINE PACKAGE (525mil)

0~8°

#32

#17

14.12±0.30

0.556±0.012

11.43±0.20

0.450±0.008

#16

0.80±0.20

+0.10

-0.05

0.20

2.74±0.20

0.031±0.008

20.87

MAX

0.108±0.008

+0.004

0.822

0.008

-0.002

3.00

MAX

0.118

20.47±0.20

0.806±0.008

0.10 MAX

0.004 MAX

+0.100

-0.050

0.41

0.71

0.028

1.27

0.050

+0.004

-0.002

(

)

0.05

0.002

0.016

MIN

Revision 3.0

March 2000

K6T1008C2E Family

CMOS SRAM

PACKAGE DIMENSIONS

Units: millimeters(inches)

32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)

+0.10

-0.05

20.00±0.20

0.787±0.008

0.20

0.008^+0.004

-0.002

#32

0.25

0.010

(

)

8.40

0.331

MAX

0.50

0.0197

#17

#16

1.00±0.10

0.039±0.004

0.05

0.002

MIN

1.20

MAX

0.047

0.25

0.010

18.40±0.10

0.724±0.004

TYP

+0.10

0.15

-0.05

0.006^+0.004

-0.002

0~8°

0.50

0.020

0.45 ~0.75

0.018 ~0.030

(

)

32 THIN SMALL OUTLINE PACKAGE TYPE I (0820R)

+0.10

-0.05

20.00±0.20

0.787±0.008

0.20

+0.004

-0.002

0.008

#16

#17

0.25

0.010

(

)

0.50

0.0197

#32

1.00±0.10

0.039±0.004

0.05

0.002

MIN

1.20

MAX

0.047

0.25

0.010

18.40±0.10

0.724±0.004

TYP

+0.10

-0.05

0.15

+0.004

-0.002

0.006

0~8°

0.50

0.020

0.45 ~0.75

0.018 ~0.030

(

)

Revision 3.0

March 2000

K6T1008C2E-DB70相关文章

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K6T1008C2E-DB70产品参数

型号:	K6T1008C2E-DB70
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	DIP
包装说明：	0.600 INCH, DIP-32
针数：	32
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.32.00.41
风险等级：	5.82
Is Samacsys：	N
最长访问时间：	70 ns
I/O 类型：	COMMON
JESD-30 代码：	R-PDIP-T32
长度：	41.91 mm
内存密度：	1048576 bit
内存集成电路类型：	STANDARD SRAM
内存宽度：	8
湿度敏感等级：	1
功能数量：	1
端子数量：	32
字数：	131072 words
字数代码：	128000
工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	128KX8
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装等效代码：	DIP32,.6
封装形状：	RECTANGULAR
封装形式：	IN-LINE
并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	225
电源：	5 V
认证状态：	Not Qualified
座面最大高度：	5.08 mm
最小待机电流：	2 V
子类别：	SRAMs
最大压摆率：	0.05 mA
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	NO
技术：	CMOS
温度等级：	COMMERCIAL
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	15.24 mm
Base Number Matches：	1

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