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产品型号K6X4016C3F-TF55的概述

K6X4016C3F-TF55 芯片概述 K6X4016C3F-TF55是一款由原美国公司三星（Samsung）设计与生产的动态随机存取存储器（DRAM）芯片。它属于K6系列的存储器，主要用于各种电子设备中的存储解决方案。K6X4016C3F-TF55 针对高性能和大容量存储需求而设计，广泛应用于计算机、嵌入式系统和消费电子设备。随着技术的不断进步，DRAM存储器在电子产品中的应用场景日益增多，例如用于图形处理、数据缓存、以及各种复杂运算的临时存储。 K6X4016C3F-TF55 的详细参数 K6X4016C3F-TF55 的技术参数如下： - 存储容量：4Mb (4096K Bits) - 数据宽度：16位（x16） - 工作电压：2.5V/3.3V（双电源选择） - 访问时间：55ns - 封装类型：TSOPII（Thin Small Outline Package II） - ...

产品型号K6X4016C3F-TF55的Datasheet PDF文件预览

K6X4016C3F Family

CMOS SRAM

Document Title

256Kx16 bit Low Power full CMOS Static RAM

Revision History

Revision No. History

Draft Date

Remark

0.0

Initial draft

July 26, 2002

Preliminary

0.1

Revised

November 29, 2002 Preliminary

September 16, 2003 final

Added Commercial Product.

Deleted 44-TSOP2-400R Package Type.

1.0

Finalized

- Changed ICC from 10mA to 5mA

- Changed ICC1 from 10mA to 7mA

- Changed ICC2 from 50mA to 30mA

- Changed ISB from 3mA to 0.4mA

- Changed IDR(Commercial) from 15mA to 12mA

- Changed IDR(industrial) from 20mA to 12mA

- Changed IDR(Automotive) from 30mA to 25mA

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

Revision 1.0

September 2003

K6X4016C3F Family

CMOS SRAM

256Kx16 bit Low Power full CMOS Static RAM

FEATURES

GENERAL DESCRIPTION

· Process Technology: Full CMOS

· Organization: 256Kx16

The K6X4016C3F families are fabricated by SAMSUNG¢s

advanced full CMOS process technology. The families sup-

port various operating temperature range and small pack-

age types for user flexibility of system design. The families

also support low data retention voltage for battery back-up

operation with low data retention current.

· Power Supply Voltage: 4.5~5.5V

· Low Data Retention Voltage: 2V(Min)

· Three state output and TTL compatible

· Package Type: 44-TSOP2-400F

PRODUCT FAMILY

Power Dissipation

PKG Type

Product Family Operating Temperature Vcc Range

Speed

Standby

Operating

(ICC2, Max)

(ISB1, Max)

K6X4016C3F-B

K6X4016C3F-F

K6X4016C3F-Q

Commercial(0~70°C)

Industrial (-40~85°C)

Automotive (-40~125°C)

20 mA

30 mA

55¹⁾/70ns

4.5~5.5V

30 mA

44-TSOP2-400F

1. The parameter is measured with 50pF test load.

PIN DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

I/O16

I/O15

I/O14

I/O13

Vss

Vcc

I/O12

I/O11

I/O10

I/O9

N.C

Clk gen.

Precharge circuit.

Vcc

Vss

I/O1

I/O2

I/O3

I/O4

Vcc

Vss

I/O5

I/O6

I/O7

I/O8

A17

A16

A15

A14

A13

Row

select

Row

Addresses

Memory array

44-TSOP2

Forward

Data

cont

I/O Circuit

Column select

I/O1~I/O8

A10

A11

A12

Data

cont

I/O9~I/O16

Data

cont

Name

Function

Name

Function

Column Addresses

Chip Select Input

Output Enable Input

Write Enable Input

Address Inputs

Lower Byte (I/O1~8)

Upper Byte(I/O9~16)

Vcc Power

Vss Ground

A0~A17

Control

logic

I/O1~I/O16 Data Inputs/Outputs

No Connection

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Revision 1.0

September 2003

K6X4016C3F Family

CMOS SRAM

PRODUCT LIST

Commercial Products(0~70°C)

Industrial Products(-40~85°C)

Automotive Products(-40~125°C)

Part Name

Function

Part Name

Function

Part Name

Function

K6X4016C3F-TB55

K6X4016C3F-TB70

44-TSOP2-F, 55ns, LL

44-TSOP2-F, 70ns, LL

K6X4016C3F-TF55

K6X4016C3F-TF70

44-TSOP2-F, 55ns, LL

44-TSOP2-F, 70ns, LL

K6X4016C3F-TQ55

K6X4016C3F-TQ70

44-TSOP2-F, 55ns, L

44-TSOP2-F, 70ns, L

FUNCTIONAL DESCRIPTION

X¹⁾

I/O1~8

I/O9~16

High-Z

Dout

Mode

Power

Standby

Active

High-Z

Dout

Deselected

Output Disabled

Lower Byte Read

Upper Byte Read

Word Read

X¹⁾

High-Z

Dout

X¹⁾

Din

High-Z

Din

Lower Byte Write

Upper Byte Write

Word Write

High-Z

Din

1. X means don¢t care. (Must be in low or high state)

ABSOLUTE MAXIMUM RATINGS¹⁾

Item

Symbol

VIN,VOUT

VCC

Ratings

Unit

Remark

Voltage on any pin relative to Vss

Voltage on Vcc supply relative to Vss

Power Dissipation

-0.5 to VCC+0.5V(max. 7.0V)

-0.3 to 7.0

1.0

°C

Storage temperature

TSTG

-65 to 150

0 to 70

K6X4016C3F-B

K6X4016C3F-F

K6X4016C3F-Q

Operating Temperature

°C

-40 to 85

-40 to 125

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Revision 1.0

September 2003

K6X4016C3F Family

CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS¹⁾

Item

Supply voltage

Symbol

Vcc

Min

4.5

Typ

Max

Unit

5.0

5.5

Ground

Vss

Vcc+0.5²⁾

0.8

Input high voltage

Input low voltage

VIH

2.2

-0.5³⁾

VIL

Note:

1. Commercial Product: TA=0 to 70°C, otherwise specified

Industrial Product: TA=-40 to 85°C, otherwise specified

Automotive Product TA=-40 to 125°C, otherwise specified

2. Overshoot: VCC+3.0V in case of pulse width £ 30ns

3. Undershoot: -3.0V in case of pulse width £ 30ns

4. Overshoot and undershoot are sampled, not 100% tested

CAPACITANCE¹⁾(f=1MHz, TA=25°C)

Item

Symbol

CIN

Test Condition

VIN=0V

Min

Max

Unit

Input capacitance

Input/Output capacitance

CIO

VIO=0V

1. Capacitance is sampled, not 100% tested

DC AND OPERATING CHARACTERISTICS

Item

Symbol

ILI

Test Conditions

Min Typ Max Unit

Input leakage current

VIN=Vss to Vcc

-1

Output leakage current

Operating power supply current

ILO

CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc

IIO=0mA, CS=VIL, VIN=VIL or VIH, Read

ICC

Cycle time=1ms, 100% duty, IIO=0mA

CS£0.2V, VIN³ 0.2V or VIN³ Vcc-0.2V

ICC1

ICC2

Average operating current

Cycle time=Min, 100% duty, IIO=0mA, CS=VIL,

VIN=VIH or VIL

Output low voltage

Output high voltage

Standby Current(TTL)

VOL

VOH

ISB

IOL=2.1mA

0.4

IOH=-1.0mA

2.4

CS=VIH, Other inputs = VIL or VIH

0.4

K6X4016C3F-B

K6X4016C3F-F

K6X4016C3F-Q

Standby Current(CMOS)

ISB1

CS³ Vcc-0.2V, Other inputs=0~Vcc

Revision 1.0

September 2003

K6X4016C3F Family

CMOS SRAM

AC OPERATING CONDITIONS

TEST CONDITIONS (Test Load and Test Input/Output Reference)

Input pulse level: 0.8 to 2.4V

Input rising and falling time: 5ns

Input and output reference voltage: 1.5V

Output load (See right): CL=100pF+1TTL

CL=50pF+1TTL

1. Including scope and jig capacitance

AC CHARACTERISTICS

( Vcc=4.5~5.5V, Commercial Product: TA=0 to 70°C, Industrial Product: TA=-40 to 85°C, Automotive Product : TA=-40 to 125°C, )

Speed Bins

Parameter List

Symbol

Units

55ns

70ns

Min

Max

Min

Max

Read cycle time

tRC

tAA

Address access time

Chip select to output

tCO

tOE

Output enable to valid output

Chip select to low-Z output

Output enable to low-Z output

LB, UB enable to low-Z output

Chip disable to high-Z output

OE disable to high-Z output

Output hold from address change

LB, UB valid to data output

UB, LB disable to high-Z output

Write cycle time

tLZ

tOLZ

tBLZ

tHZ

Read

tOHZ

tOH

tBA

tBHZ

tWC

tCW

tAS

Chip select to end of write

Address set-up time

Address valid to end of write

Write pulse width

tAW

tWP

tWR

tWHZ

tDW

tDH

Write

Write recovery time

Write to output high-Z

Data to write time overlap

Data hold from write time

End write to output low-Z

LB, UB valid to end of write

tOW

tBW

DATA RETENTION CHARACTERISTICS

Item

Symbol

Test Condition

Min

Typ

Max

5.5

Unit

Vcc for data retention

VDR

CS³ Vcc-0.2V

2.0

K6X4016C3F-B

K6X4016C3F-F

K6X4016C3F-Q

Data retention current

IDR

Vcc=3.0V, CS³ Vcc-0.2V

Data retention set-up time

Recovery time

tSDR

tRDR

See data retention waveform

Revision 1.0

September 2003

K6X4016C3F Family

CMOS SRAM

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)

tRC

Address

tAA

tOH

Data Valid

Data Out

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tOH

tAA

tCO

tHZ

tBA

UB, LB

tBHZ

tOHZ

tOE

tOLZ

tBLZ

tLZ

Data out

High-Z

Data Valid

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

Revision 1.0

September 2003

K6X4016C3F Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

tWC

Address

tWR(4)

tCW(2)

tAW

tBW

UB, LB

tWP(1)

tAS(3)

tDW

tDH

High-Z

Data in

Data Valid

tWHZ

tOW

Data Undefined

Data out

TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)

tWC

Address

tAS(3)

tCW(2)

tWR(4)

tAW

tBW

UB, LB

tWP(1)

tDW

tDH

Data Valid

Data in

Data out

High-Z

Revision 1.0

September 2003

K6X4016C3F Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)

tWC

Address

tCW(2)

tWR(4)

tAW

tBW

UB, LB

tAS(3)

tWP(1)

tDH

tDW

Data in

Data Valid

High-Z

Data out

High-Z

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-

tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the CS going low to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

DATA RETENTION WAVE FORM

CS controlled

Data Retention Mode

tSDR

tRDR

VCC

4.5V

2.2V

VDR

CS³ VCC - 0.2V

GND

Revision 1.0

September 2003

K6X4016C3F Family

CMOS SRAM

Units: millimeter(inch)

PACKAGE DIMENSIONS

44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)

0~8°

0.25

0.010

(

)

#44

#23

0.45 ~0.75

0.018 ~ 0.030

11.76±0.20

0.463±0.008

0.50

)

(

0.020

#22

1.00±0.10

0.039±0.004

18.81

0.741

1.20

0.047

MAX.

18.41±0.10

0.725±0.004

0.10

0.004

MAX

0.35±0.10

0.014±0.004

0.80

0.0315

0.805

0.032

(

)

Revision 1.0

September 2003

K6X4016C3F-TF55相关文章

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K6X4016C3F-TF55产品参数

型号:	K6X4016C3F-TF55
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	SAMSUNG SEMICONDUCTOR INC
零件包装代码：	TSOP2
包装说明：	TSOP2, TSOP44,.46,32
针数：	44
Reach Compliance Code：	unknown
ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41
风险等级：	5.91
Is Samacsys：	N
最长访问时间：	55 ns
I/O 类型：	COMMON
JESD-30 代码：	R-PDSO-G44
JESD-609代码：	e0
长度：	18.41 mm
内存密度：	4194304 bit
内存集成电路类型：	STANDARD SRAM
内存宽度：	16
湿度敏感等级：	3
功能数量：	1
端子数量：	44
字数：	262144 words
字数代码：	256000
工作模式：	ASYNCHRONOUS
最高工作温度：	85 °C
最低工作温度：	-40 °C
组织：	256KX16
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP2
封装等效代码：	TSOP44,.46,32
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE
并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V
认证状态：	Not Qualified
座面最大高度：	1.2 mm
最小待机电流：	2 V
子类别：	SRAMs
最大压摆率：	0.05 mA
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.8 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10.16 mm
Base Number Matches：	1

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