K7A403609B-QC中文资料应用文章市场行情现货热卖使用介绍-中国IC网-芯三七

K7A403600B

K7A403200B

K7A401800B

128Kx36/x32 & 256Kx18 Synchronous SRAM

Document Title

128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM

Revision History

Remark

Rev. No

History

Draft Date

Preliminary

0.0

0.1

1. Initial draft

May. 15. 2001

June. 12. 2001

1. Changed DC parameters

Icc ; from 350mA to 290mA at -16,

from 330mA to 270mA at -15,

from 300mA to 250mA at -14,

ISB1 ; from 100mA to 80mA

Preliminary

Final

0.2

0.3

1.0

1. Delete Pass-Through

June.25. 2001

Aug. 11. 2001

Nov. 15. 2001

1. Add x32 org. and industrial temperature

1. Final spec release

2. Changed Pin Capacitance

- Cin ; from 5pF to 4pF

- Cout ; from 7pF to 6pF

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

- 1 -

Nov 2001

Rev 1.0

K7A403600B

K7A403200B

K7A401800B

128Kx36/x32 & 256Kx18 Synchronous SRAM

4Mb SB/SPB Synchronous SRAM Ordering Information

Speed

Org.

Part Number

Mode

VDD

FT ; Access Time(ns)

PKG

Temp

Pipelined ; Cycle Time(MHz)

K7B401825B-QC(I)65/75/80

K7A401800B-QC(I)16/14

SB

3.3

6.5/7.5/8.0 ns

167/138 MHz

256Kx18

SPB(2E1D)

SB

K7A401809B-QC(I)30/27/25/22/20

K7B403225B-QC(I)65/75/80

K7A403200B-QC(I)16/14

300/275/250/225/200 MHz

6.5/7.5/8.0 ns

C

(Commercial

Temperature

Range)

SPB(2E1D)

SPB(2E2D)

SB

167/138 MHz

Q

128Kx32

128Kx36

(100TQFP)

K7A403209B-QC(I)30/27/25/22/20

K7A403201B-QC(I)16/14

300/275/250/225/200 MHz

167/138/ MHz

I:

(Industrial

Temperature

Range)

K7B403625B-QC(I)65/75/80

K7A403600B-QC(I)16/14

6.5/7.5/8.0 ns

SPB(2E1D)

SPB(2E2D)

167/138 MHz

K7A403609B-QC(I)30/27/25/22/20

K7A403601B-QC(I)16/14

300/275/250/225/200 MHz

167/138 MHz

- 2 -

Nov 2001

Rev 1.0

K7A403600B

K7A403200B

K7A401800B

128Kx36/x32 & 256Kx18 Synchronous SRAM

128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM

FEATURES

GENERAL DESCRIPTION

• Synchronous Operation.

• 2 Stage Pipelined operation with 4 Burst.

• On-Chip Address Counter.

The K7A403600B, K7A403200B and K7A401800B are

4,718,592-bit Synchronous Static Random Access Memory

designed for high performance second level cache of Pen-

tium and Power PC based System.

• Self-Timed Write Cycle.

• On-Chip Address and Control Registers.

• VDD= 3.3V+0.3V/-0.165V Power Supply.

• VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O

or 2.5V+0.4V/-0.125V for 2.5V I/O.

• 5V Tolerant Inputs Except I/O Pins.

• Byte Writable Function.

• Global Write Enable Controls a full bus-width write.

• Power Down State via ZZ Signal.

• LBO Pin allows a choice of either a interleaved burst or a linear

burst.

• Three Chip Enables for simple depth expansion with No Data Cont-

nention ; 2cycle Enable, 1cycle Disable.

• Asynchronous Output Enable Control.

• ADSP, ADSC, ADV Burst Control Pins.

• TTL-Level Three-State Output.

It is organized as 128K(256K) words of 36(18) bits and inte-

grates address and control registers, a 2-bit burst address

counter and added some new functions for high perfor-

mance cache RAM applications; GW, BW, LBO, ZZ. Write

cycles are internally self-timed and synchronous.

Full bus-width write is done by GW, and each byte write is

performed by the combination of WEx and BW when GW is

high. And with CS1 high, ADSP is blocked to control signals.

Burst cycle can be initiated with either the address status

processor(ADSP) or address status cache controller(ADSC)

inputs. Subsequent burst addresses are generated inter-

nally in the system¢s burst sequence and are controlled by

the burst address advance(ADV) input.

LBO pin is DC operated and determines burst sequence(lin-

ear or interleaved).

• 100-TQFP-1420A .

• Operating in commeical and industrial temperature range.

ZZ pin controls Power Down State and reduces Stand-by

current regardless of CLK.

FAST ACCESS TIMES

The K7A403600B, K7A403200B and K7A401800B are fab-

ricated using SAMSUNG¢s high performance CMOS tech-

nology and is available in a 100pin TQFP package. Multiple

power and ground pins are utilized to minimize ground

bounce.

PARAMETER

Cycle Time

Symbol

tCYC

tCD

-16 -14

Unit

ns

6.0

3.5

7.2

4.0

Clock Access Time

ns

Output Enable Access Time

tOE

ns

LOGIC BLOCK DIAGRAM

CLK

LBO

128Kx36/32 , 256Kx18

BURST CONTROL

LOGIC

BURST

MEMORY

ADDRESS

COUNTER

ADV

ADSC

A¢0~A¢1

ARRAY

A0~A1

A2~A16

or A2~A17

ADDRESS

REGISTER

A0~A16

or A0~A17

ADSP

DATA-IN

REGISTER

CS1

CS2

OUTPUT

GW

BW

CONTROL

LOGIC

REGISTER

BUFFER

WEx

(x=a,b,c,d or a,b)

OE

ZZ

36/32 or 18

DQa0 ~ DQd7

DQPa ~ DQPd

or DQa0 ~ DQb7

DQPa ~ DQPb

- 3 -

Nov 2001

Rev 1.0

K7A403600B

128Kx36/x32 & 256Kx18 Synchronous SRAM

K7A401800B

PIN CONFIGURATION(TOP VIEW)

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQPb/NC

DQb7

DQb6

VDDQ

VSSQ

DQb5

DQb4

DQb3

DQb2

VSSQ

VDDQ

DQb1

DQb0

VSS

DQPc/NC

DQc0

DQc1

VDDQ

VSSQ

DQc2

DQc3

DQc4

DQc5

VSSQ

VDDQ

DQc6

DQc7

N.C.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

100 Pin TQFP

(20mm x 14mm)

N.C.

VDD

ZZ

VDD

N.C.

VSS

K7A403600B(128Kx36)

K7A403200B(128Kx32)

DQa7

DQa6

VDDQ

VSSQ

DQa5

DQa4

DQa3

DQa2

VSSQ

VDDQ

DQa1

DQa0

DQPa/NC

DQd0

DQd1

VDDQ

VSSQ

DQd2

DQd3

DQd4

DQd5

VSSQ

VDDQ

DQd6

DQd7

DQPd/NC

PIN NAME

SYMBOL

PIN NAME

TQFP PIN NO.

SYMBOL

PIN NAME

TQFP PIN NO.

A0 - A16

Address Inputs

32,33,34,35,36,37

44,45,46,47,48,49

50,81,82,99,100

83

VDD

VSS

Power Supply(+3.3V)

Ground

15,41,65,91

17,40,67,90

ADV

ADSP

ADSC

CLK

CS1

CS2

WEx

(x=a,b,c,d)

OE

Burst Address Advance

Address Status Processor 84

Address Status Controller 85

No Connect

14,16,38,39,42,43,66

N.C.

Data Inputs/Outputs

52,53,56,57,58,59,62,63

68,69,72,73,74,75,78,79

2,3,6,7,8,9,12,13

18,19,22,23,24,25,28,29

51,80,1,30

DQa0~a7

DQb0~b7

DQc0~c7

DQd0~d7

DQPa~Pd

/NC

Clock

89

98

97

92

Chip Select

Byte Write Inputs

93,94,95,96

Output Power Supply

(2.5V or 3.3V)

Output Ground

4,11,20,27,54,61,70,77

5,10,21,26,55,60,71,76

Output Enable

86

88

87

64

31

VDDQ

VSSQ

GW

BW

ZZ

LBO

Global Write Enable

Byte Write Enable

Power Down Input

Burst Mode Control

- 4 -

Nov 2001

Rev 1.0

K7A403600B

K7A403200B

K7A401800B

128Kx36/x32 & 256Kx18 Synchronous SRAM

PIN CONFIGURATION(TOP VIEW)

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

A10

N.C.

VDDQ

VSSQ

N.C.

1

2

3

4

5

6

7

8

N.C.

VDDQ

VSSQ

N.C.

DQPa

DQa7

DQa6

VSSQ

VDDQ

DQa5

DQa4

VSS

N.C.

DQb0

DQb1

VSSQ

VDDQ

DQb2

DQb3

N.C.

VDD

N.C.

VSS

DQb4

DQb5

VDDQ

VSSQ

DQb6

DQb7

DQPb

N.C.

VSSQ

VDDQ

N.C.

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

100 Pin TQFP

N.C.

VDD

ZZ

(20mm x 14mm)

DQa3

DQa2

VDDQ

VSSQ

DQa1

DQa0

N.C.

VSSQ

VDDQ

N.C.

K7A401800B(256Kx18)

PIN NAME

SYMBOL

PIN NAME

TQFP PIN NO.

SYMBOL

PIN NAME

TQFP PIN NO.

A0 - A17

Address Inputs

32,33,34,35,36,37,

44,45,46,47,48,49,

50,80,81,82,99,100

83

VDD

VSS

N.C.

Power Supply(+3.3V) 15,41,65,91

Ground

17,40,67,90

No Connect

1,2,3,6,7,14,16,25,28,29,

30,38,39,42,43,51,52,53,

56,57,66,75,78,79,95,96

ADV

ADSP

ADSC

CLK

CS1

CS2

WEx

(x=a,b)

OE

Burst Address Advance

Address Status Processor 84

Address Status Controller

Clock

Chip Select

Byte Write Inputs

85

89

98

97

92

93,94

DQa0~a7

DQb0~b7

DQPa, Pb

VDDQ

Data Inputs/Outputs

58,59,62,63,68,69,72,73

8,9,12,13,18,19,22,23

74,24

Output Power Supply

(2.5V or 3.3V)

4,11,20,27,54,61,70,77

VSSQ

Output Ground

5,10,21,26,55,60,71,76

Output Enable

86

88

87

64

31

GW

BW

ZZ

LBO

Global Write Enable

Byte Write Enable

Power Down Input

Burst Mode Control

- 5 -

Nov 2001

Rev 1.0

K7A403600B

K7A403200B

K7A401800B

128Kx36/x32 & 256Kx18 Synchronous SRAM

FUNCTION DESCRIPTION

The K7A4036/3200B and K7A401800B are synchronous SRAM designed to support the burst address accessing sequence of the

P6 and Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The

start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.

The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with

ADV.

When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ

returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.

Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address

register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-

ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-

ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output

pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address

increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to

control signals by disabling CS1.

All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx

when GW is high.

Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-

ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled

Low(regardless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the

next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte

write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7

and DQPb, WEc controls DQc0 ~ DQc7 and DQPc, and WEd control DQd0 ~ DQd7 and DQPd. Read or write cycle may also be initi-

ated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;

ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.

WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).

Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external

address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state

of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is

selected.

BURST SEQUENCE TABLE

(Interleaved Burst)

Case 4

Case 1

Case 2

Case 3

LBO PIN

HIGH

First Address

A1

A0

A1

A0

A1

A0

A1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Fourth Address

Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.

BQ TABLE

(Linear Burst)

Case 1

Case 2

Case 3

Case 4

LBO PIN

LOW

First Address

A1

A0

A1

A0

A1

A0

A1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Fourth Address

Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.

ASYNCHRONOUS TRUTH TABLE

(See Notes 1 and 2):

Notes

OPERATION

ZZ

H

L

OE

X

I/O STATUS

High-Z

1. X means "Don¢t Care".

2. ZZ pin is pulled down internally

3. For write cycles that following read cycles, the output buffers must be

disabled with OE, otherwise data bus contention will occur.

4. Sleep Mode means power down state of which stand-by current does

not depend on cycle time.

Sleep Mode

L

DQ

Read

L

H

X

High-Z

Write

L

Din, High-Z

High-Z

5. Deselected means power down state of which stand-by current

depends on cycle time.

Deselected

L

X

- 6 -

Nov 2001

Rev 1.0

K7A403600B

K7A403200B

K7A401800B

128Kx36/x32 & 256Kx18 Synchronous SRAM

TRUTH TABLES

SYNCHRONOUS TRUTH TABLE

CS1

H

L

CS2

X

L

CS2 ADSP ADSC ADV WRITE CLK

ADDRESS ACCESSED

N/A

OPERATION

Not Selected

X

H

X

H

L

X

L

X

L

X

L

X

L

•

N/A

Not Selected

L

X

L

N/A

Not Selected

L

X

L

N/A

Not Selected

L

X

H

X

L

N/A

Not Selected

L

X

L

External Address

Next Address

Current Address

Begin Burst Read Cycle

Begin Burst Write Cycle

Begin Burst Read Cycle

Continue Burst Read Cycle

Continue Burst Write Cycle

Suspend Burst Read Cycle

Suspend Burst Write Cycle

L

H

X

H

X

H

X

H

X

L

H

L

X

H

X

H

X

H

X

H

X

H

L

H

L

Notes : 1. X means "Don¢t Care".

2. The rising edge of clock is symbolized by • .

3. WRITE = L means Write operation in WRITE TRUTH TABLE.

WRITE = H means Read operation in WRITE TRUTH TABLE.

4. Operation finally depends on status of asynchronous input pins(ZZ and OE).

WRITE TRUTH TABLE( x36/32)

GW

H

BW

H

L

WEa

X

WEb

X

WEc

X

WEd

X

OPERATION

READ

H

READ

H

L

H

WRITE BYTE a

WRITE BYTE b

WRITE BYTE c and d

WRITE ALL BYTEs

H

L

H

L

H

L

H

L

H

L

X

Notes : 1. X means "Don¢t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).

WRITE TRUTH TABLE(x18)

GW

H

BW

H

L

WEa

X

WEb

X

OPERATION

READ

H

READ

H

L

H

WRITE BYTE a

WRITE BYTE b

WRITE ALL BYTEs

H

L

H

L

H

L

X

Notes : 1. X means "Don¢t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).

- 7 -

Nov 2001

Rev 1.0

K7A403600B

K7A403200B

K7A401800B

128Kx36/x32 & 256Kx18 Synchronous SRAM

ABSOLUTE MAXIMUM RATINGS*

PARAMETER

SYMBOL

VDD

RATING

-0.3 to 4.6

VDD

UNIT

V

Voltage on VDD Supply Relative to VSS

Voltage on VDDQ Supply Relative to VSS

VDDQ

VIN

V

Voltage on Input Pin Relative to VSS

Voltage on I/O Pin Relative to VSS

Power Dissipation

-0.3 to VDD+0.3

-0.3 to VDDQ+0.3

2.2

V

VIO

V

PD

W

Storage Temperature

TSTG

TOPR

TBIAS

-65 to 150

0 to 70

°C

Commercial

Industrial

Operating Temperature

-40 to 85

-10 to 85

Storage Temperature Range Under Bias

*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

OPERATING CONDITIONS at 3.3V I/O (0°C£ TA£70°C)

PARAMETER

Supply Voltage

Ground

SYMBOL

VDD

MIN

3.135

0

Typ.

3.3

0

MAX

3.6

0

UNIT

V

VDDQ

VSS

* The above parameters are also guaranteed at industrial temperature range.

OPERATING CONDITIONS at 2.5V I/O(0°C £ TA £ 70°C)

PARAMETER

Supply Voltage

Ground

SYMBOL

VDD

MIN

3.135

2.375

0

Typ.

3.3

2.5

0

MAX

3.6

2.9

0

UNIT

V

VDDQ

VSS

* The above parameters are also guaranteed at industrial temperature range.

CAPACITANCE*(TA=25°C, f=1MHz)

PARAMETER

Input Capacitance

SYMBOL

CIN

TEST CONDITION

VIN=0V

MIN

MAX

UNIT

pF

-

4

6

Output Capacitance

COUT

VOUT=0V

pF

*Note : Sampled not 100% tested.

- 8 -

Nov 2001

Rev 1.0

K7A403600B

K7A403200B

K7A401800B

128Kx36/x32 & 256Kx18 Synchronous SRAM

DC ELECTRICAL CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)

PARAMETER

Input Leakage Current(except ZZ)

Output Leakage Current

SYMBOL

TEST CONDITIONS

VDD = Max ; VIN=VSS to VDD

MIN

MAX

+2

UNIT

mA

IIL

-2

-

mA

IOL

Output Disabled, VOUT=VSS to VDDQ

+2

Device Selected, IOUT=0mA, ZZ£VIL,

All Inputs=VIL or VIH , Cycle Time ³ cyc Min

-16

-14

-16

-14

290

250

140

130

Operating Current

ICC

ISB

mA

-

Device deselected, IOUT=0mA,ZZ£VIL,

f=Max, All Inputs£0.2V or ³ VDD-0.2V

-

Device deselected, IOUT=0mA, ZZ£0.2V,

f = 0, All Inputs=fixed (VDD-0.2V or 0.2V)

Standby Current

ISB1

ISB2

-

80

50

mA

Device deselected, IOUT=0mA, ZZ³ VDD-0.2V,

f=Max, All Inputs£VIL or ³ VIH

Output Low Voltage(3.3V I/O)

Output High Voltage(3.3V I/O)

Output Low Voltage(2.5V I/O)

Output High Voltage(2.5V I/O)

Input Low Voltage(3.3V I/O)

Input High Voltage(3.3V I/O)

Input Low Voltage(2.5V I/O)

Input High Voltage(2.5V I/O)

VOL

VOH

VOL

VOH

VIL

IOL = 8.0mA

IOH = -4.0mA

IOL = 1.0mA

IOH = -1.0mA

-

0.4

V

2.4

-

0.4

-

2.0

-0.5*

2.0

-0.3*

1.7

0.8

VIH

VIL

VDD+0.3**

0.7

VIH

VDD+0.3**

The above parameters are also guaranteed at industrial temperature range.

*

VIL(Min)=-2.0(Pulse Width £ tCYC/2)

** VIH(Max)=4.6(Pulse Width £ tCYC/2)

** In Case of I/O Pins, the Max. VIH=VDDQ+0.3V

TEST CONDITIONS

(VDD=3.3V+0.3V/-0.165V,VDDQ=3.3V+0.3/-0.165V or VDD=3.3V+0.3V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0 to 70°C)

PARAMETER

VALUE

0 to 3V

0 to 2.5V

1ns

Input Pulse Level(for 3.3V I/O)

Input Pulse Level(for 2.5V I/O)

Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O)

Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O)

Input and Output Timing Reference Levels for 3.3V I/O

Input and Output Timing Reference Levels for 2.5V I/O

Output Load

1ns

1.5V

VDDQ/2

See Fig. 1

* The above parameters are also guaranteed at industrial temperature range.

- 9 -

Nov 2001

Rev 1.0

K7A403600B

K7A403200B

K7A401800B

128Kx36/x32 & 256Kx18 Synchronous SRAM

Output Load(A)

Output Load(B)

(for tLZC, tLZOE, tHZOE & tHZC)

+3.3V for 3.3V I/O

/+2.5V for 2.5V I/O

Dout

RL=50W

VL=1.5V for 3.3V I/O

VDDQ/2 for 2.5V I/O

319W / 1667W

30pF*

Dout

Z0=50W

353W / 1538W

5pF*

* Capacitive Load consists of all components of

the test environment.

* Including Scope and Jig Capacitance

Fig. 1

AC TIMING CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)

-16

-14

PARAMETER

Symbol

Unit

Min

6.0

-

Max

Min

7.2

-

Max

Cycle Time

tCYC

tCD

-

ns

Clock Access Time

3.5

4.0

Output Enable to Data Valid

tOE

-

3.5

-

4.0

ns

Clock High to Output Low-Z

tLZC

tOH

0

-

0

-

ns

Output Hold from Clock High

Output Enable Low to Output Low-Z

Output Enable High to Output High-Z

Clock High to Output High-Z

1.5

0

-

1.5

0

-

ns

tLZOE

tHZOE

tHZC

tCH

-

ns

-

3.5

-

4.0

ns

1.5

2.4

1.5

0.5

2

3.5

-

1.5

2.8

1.5

0.5

2

4.0

-

ns

Clock High Pulse Width

ns

Clock Low Pulse Width

tCL

-

ns

Address Setup to Clock High

Address Status Setup to Clock High

Data Setup to Clock High

tAS

-

ns

tSS

-

ns

tDS

-

ns

Write Setup to Clock High (GW, BW, WEX)

Address Advance Setup to Clock High

Chip Select Setup to Clock High

Address Hold from Clock High

Address Status Hold from Clock High

Data Hold from Clock High

tWS

-

ns

tADVS

tCSS

tAH

-

ns

-

ns

-

ns

tSH

-

ns

tDH

-

ns

Write Hold from Clock High (GW, BW, WEX)

Address Advance Hold from Clock High

Chip Select Hold from Clock High

ZZ High to Power Down

tWH

-

ns

tADVH

tCSH

tPDS

tPUS

-

ns

-

ns

-

cycle

ZZ Low to Power Up

2

-

2

-

Notes : 1. The above parameters are also guaranteed at industrial temperature range.

2. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP

is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times

whenever this device is chip selected.

3. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.

4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.

- 10 -

Nov 2001

Rev 1.0

K7A403600B

K7A403200B

K7A401800B

128Kx36/x32 & 256Kx18 Synchronous SRAM

- 11 -

Nov 2001

Rev 1.0

K7A403600B

K7A403200B

K7A401800B

128Kx36/x32 & 256Kx18 Synchronous SRAM

- 12 -

Nov 2001

Rev 1.0

K7A403600B

K7A403200B

K7A401800B

128Kx36/x32 & 256Kx18 Synchronous SRAM

- 13 -

Nov 2001

Rev 1.0

K7A403600B

K7A403200B

K7A401800B

128Kx36/x32 & 256Kx18 Synchronous SRAM

- 14 -

Nov 2001

Rev 1.0

K7A403600B

K7A403200B

K7A401800B

128Kx36/x32 & 256Kx18 Synchronous SRAM

- 15 -

Nov 2001

Rev 1.0

K7A403600B

K7A403200B

K7A401800B

128Kx36/x32 & 256Kx18 Synchronous SRAM

APPLICATION INFORMATION

DEPTH EXPANSION

The Samsung 128Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.

This permits easy secondary cache upgrades from 128K depth to 256K depth without extra logic.

I/O[0:71]

Data

Address

A[0:17]

A[17]

A[0:16]

A[17]

A[0:16]

Address Data

CS

Address Data

CS

CLK

2

CS2

64-Bits

Microprocessor

CLK

ADSC

WEx

OE

128Kx36

SPB

SRAM

CLK

ADSC

WEx

OE

128Kx36

SPB

SRAM

Address

CLK

(Bank 1)

(Bank 0)

Cache

Controller

CS1

ADV ADSP

ADS

INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)

(ADSP CONTROLLED , ADSC=HIGH)

Clock

tSS

tSH

ADSP

tAS

tAH

A2

A1

ADDRESS

[0:n]

tWS

tWH

WRITE

CS1

tCSS

tCSH

Bank 0 is selected by CS2, and Bank 1 deselected by CS2

An+1

ADV

OE

Bank 0 is deselected by CS2, and Bank 1 selected by CS2

tADVS

tADVH

tOE

tHZC

tLZOE

Data Out

(Bank 0)

Q1-1

Q1-2

Q1-3

Q1-4

tCD

tLZC

Data Out

(Bank 1)

Q2-1

Q2-2

Q2-3

Q2-4

*Notes : n = 14 32K depth

15 64K depth

Don¢t Care

Undefined

16 128K depth

17 256K depth

- 16 -

Nov 2001

Rev 1.0

K7A403600B

K7A403200B

K7A401800B

128Kx36/x32 & 256Kx18 Synchronous SRAM

APPLICATION INFORMATION

DEPTH EXPANSION

The Samsung 256Kx18 Synchronous Pipelinde Burst SRAM has two additional chip selects for simple depth expansion.

This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic.

I/O[0:71]

Data

Address

A[18]

A[0:17]

A[18]

A[0:17]

A[0:18]

Address Data

CS

Address Data

CS

CLK

2

CS2

Microprocessor

CLK

ADSC

WEx

OE

256Kx18

SPB

SRAM

CLK

ADSC

WEx

OE

256Kx18

SPB

SRAM

Address

CLK

(Bank 1)

(Bank 0)

Cache

Controller

CS1

ADV ADSP

ADS

INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)

(ADSP CONTROLLED , ADSC=HIGH)

Clock

tSS

tSH

ADSP

tAS

tAH

A2

A1

ADDRESS

[0:n]

tWS

tWH

WRITE

CS1

tCSS

tCSH

Bank 0 is selected by CS2, and Bank 1 deselected by CS2

An+1

ADV

OE

Bank 0 is deselected by CS2, and Bank 1 selected by CS2

tADVS

tADVH

tOE

tHZC

tLZOE

Data Out

(Bank 0)

Q1-1

Q1-2

Q1-3

Q1-4

tCD

tLZC

Data Out

(Bank 1)

Q2-1

Q2-2

Q2-3

Q2-4

*Notes : n = 14 32K depth, 15 64K depth, 16 128K depth, 17 256K depth

Don¢t Care

Undefined

- 17 -

Nov 2001

Rev 1.0

K7A403600B

K7A403200B

K7A401800B

128Kx36/x32 & 256Kx18 Synchronous SRAM

PACKAGE DIMENSIONS

Units ; millimeters/Inches

100-TQFP-1420A

22.00 ±0.30

20.00 ±0.20

0~8°

+ 0.10

- 0.05

0.127

16.00 ±0.30

14.00 ±0.20

0.10 MAX

(0.83)

0.50 ±0.10

#1

0.65

(0.58)

0.30 ±0.10

0.10 MAX

1.40 ±0.10

1.60 MAX

0.05 MIN

0.50 ±0.10

- 18 -

Nov 2001

Rev 1.0

型号:	K7A403609B-QC20
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	QFP
包装说明：	LQFP, QFP100,.63X.87
针数：	100
Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41
风险等级：	5.87
最长访问时间：	2.8 ns
其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	200 MHz
I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e0
长度：	20 mm
内存密度：	4718592 bit
内存集成电路类型：	CACHE SRAM
内存宽度：	36
功能数量：	1
端子数量：	100
字数：	131072 words
字数代码：	128000
工作模式：	SYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	128KX36
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP
封装等效代码：	QFP100,.63X.87
封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified
座面最大高度：	1.6 mm
最大待机电流：	0.05 A
最小待机电流：	3.14 V
子类别：	SRAMs
最大压摆率：	0.33 mA
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm
Base Number Matches：	1

电子百科

产品导航

产品型号K7A403609B-QC的Datasheet PDF文件预览

K7A403609B-QC相关产品..

K7A403609B-QC相关文章

IC37:专业IC行业平台