K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
Accelerated Program Operation
Accelerated program operation reduces the program time. This is one of two functions provided by the WP/ACC pin. When the WP/
ACC pin is asserted as VHH, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotecting any
protected blocks, and reduces the program operation time. The system would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing VHH from the WP/ACC pin returns the device to normal operation. Recommend
that the WP/ACC pin must not be asserted at VHH except accelerated program operation, or the device may be damaged. In
addition, the WP/ACC pin must not be in the state of floating or unconnected, otherwise the device may be led to malfunc-
tion.
Software Reset
The reset command provides that the bank is reseted to read mode or erase-suspend-read mode. The addresses are in Don't Care
state. The reset command is vaild between the sequence cycles in an erase command sequence before erasing begins, or in a pro-
gram command sequence before programming begins. This resets the bank in which was operating to read mode. if the device is be
erasing or programming, the reset command is invalid until the operation is completed. Also, the reset command is valid between the
sequence cycles in an autoselect command sequence. In the autoselect mode, the reset command returns the bank to read mode.
If a bank entered the autoselect mode in the Erase Suspend mode, the reset command returns the bank to erase-suspend-read
mode. If DQ5 is high on erase or program operation, the reset command return the bank to read mode or erase-suspend-read mode
if the bank was in the Erase Suspend state.
Hardware Reset
The K8D3216U offers a reset feature by driving the RESET pin to VIL. The RESET pin must be kept low (VIL) for at least 500ns.
When the RESET pin is driven low, any operation in progress will be terminated and the internal state machine will be reset to the
standby mode after 20µs. If a hardware reset occurs during a program operation, the data at that particular location will be lost.
Once the RESET pin is taken high, the device requires 200ns of wake-up time until outputs are valid for read access. Also, note that
all the data output pins are tri-stated for the duration of the RESET pulse.
The RESET pin may be tied to the system reset pin. If a system reset occurs during the Internal Program and Erase Routine, the
device will be automatically reset to the read mode ; this will enable the systems microprocessor to read the boot-up firmware from
the Flash memory.
Power-up Protection
To avoid initiation of a write cycle during Vcc Power-up, RESET low must be asserted during power-up. After RESET goes high, the
device is reset to the read mode.
Low Vcc Write Inhibit
To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than 1.8V. If Vcc <
VLKO (Lock-Out Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the device
will reset itself to the read mode. Subsequent writes will be ignored until the Vcc level is greater than VLKO. It is the user′s responsi-
bility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above 1.8V.
Write Pulse Glitch Protection
Noise pulses of less than 5ns(typical) on CE, OE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited under any one of the following conditions : OE = VIL, CE = VIH or WE = VIH. To initiate a write, CE and WE must
be "0", while OE is "1".
Commom Flash Memory Interface
Common Flash Momory Interface is contrived to increase the compatibility of host system software. It provides the specific informa-
tion of the device, such as memory size, byte/word configuration, and electrical features. Once this information has been obtained,
the system software will know which command sets to use to enable flash writes, block erases, and control the flash component.
When the system writes the CFI command(98H) to address 55H in word mode(or address AAH in byte mode), the device enters the
CFI mode. And then if the system writes the address shown in Table 12, the system can read the CFI data. Query data are always
presented on the lowest-order data outputs(DQ0-7) only. In word(x16) mode, the upper data outputs(DQ8-15) is 00h. To terminate
this operation, the system must write the reset command.
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Revision 1.7
September, 2006
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