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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • K8P3215UQB-PI4B 现货库存
  • 数量69850 
  • 厂家SAMSUNG 
  • 封装SOD323 
  • 批号22+ 
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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • K8P3215UQB-PI4B 现货库存
  • 数量6980 
  • 厂家SAMSUNG 
  • 封装TSSOP48 
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  • 新到现货、一手货源、当天发货、bom配单
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  • 深圳市美思瑞电子科技有限公司

     该会员已使用本站12年以上
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  • 数量12245 
  • 厂家SAMSUNG/三星 
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  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
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  • 数量8500 
  • 厂家原厂品牌 
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
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  • 数量332 
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     该会员已使用本站15年以上
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  • 数量60000 
  • 厂家SAMSUNG/三星 
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  • 集好芯城

     该会员已使用本站13年以上
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  • 数量18747 
  • 厂家SAMSUNG/三星 
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  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
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  • 数量9800 
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  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
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  • 数量1137 
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
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  • 数量12500 
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  • 深圳市集创讯科技有限公司

     该会员已使用本站5年以上
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  • 数量35000 
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  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
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  • 数量5680 
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     该会员已使用本站12年以上
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  • 深圳市华芯盛世科技有限公司

     该会员已使用本站13年以上
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  • 数量865000 
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
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  • 数量13050 
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  • 封装TSOP48 
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     该会员已使用本站14年以上
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  • 数量21000 
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
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  • 数量1145 
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  • 深圳市硅诺电子科技有限公司

     该会员已使用本站8年以上
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  • 厂家SAMSUNG 
  • 封装原厂指定分销商,有意请来电或QQ洽谈 
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  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
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  • 数量85000 
  • 厂家SAMSUNG/三星 
  • 封装TSOP-48 
  • 批号23+ 
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  • 上海磐岳电子有限公司

     该会员已使用本站11年以上
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  • 数量5800 
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  • 封装TSOP 
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  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
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  • 数量3505 
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  • 深圳市宗天技术开发有限公司

     该会员已使用本站10年以上
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  • 数量16 
  • 厂家SAMSUNG/三星 
  • 封装TSSOP 
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  • 深圳市宏诺德电子科技有限公司

     该会员已使用本站8年以上
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  • 数量68000 
  • 厂家SAMSUNG 
  • 封装TSOP48 
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  • 上海意淼电子科技有限公司

     该会员已使用本站14年以上
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  • 数量20000 
  • 厂家SEC 
  • 封装TSOP48 
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  • 深圳市楷兴电子科技有限公司

     该会员已使用本站7年以上
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  • 数量10500 
  • 厂家SAMSUNG/三星 
  • 封装原厂原装 
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  • 深圳市亿智腾科技有限公司

     该会员已使用本站8年以上
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  • 数量16680 
  • 厂家SAMSUNG 
  • 封装TSOP 
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  • 假一赔十★全新原装现货★★特价供应★工厂客户可放款
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  • 深圳市珩瑞科技有限公司

     该会员已使用本站2年以上
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  • 数量6756 
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  • 深圳市卓越微芯电子有限公司

     该会员已使用本站12年以上
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  • 数量5500 
  • 厂家Samsung 
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  • 深圳市特拉特科技有限公司

     该会员已使用本站2年以上
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  • 数量18000 
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  • 封装TSSOP48 
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  • 深圳市隆鑫创展电子有限公司

     该会员已使用本站15年以上
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  • 数量30000 
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  • 深圳市宇川湘科技有限公司

     该会员已使用本站6年以上
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  • 深圳市科庆电子有限公司

     该会员已使用本站16年以上
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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
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  • 数量6980 
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  • 深圳市瑞天芯科技有限公司

     该会员已使用本站7年以上
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  • 数量20000 
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  • 深圳市科雨电子有限公司

     该会员已使用本站9年以上
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  • 深圳市创思克科技有限公司

     该会员已使用本站2年以上
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  • 深圳市澳亿芯电子

     该会员已使用本站13年以上
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  • 深圳市一线半导体有限公司

     该会员已使用本站11年以上
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  • 深圳市一线半导体有限公司

     该会员已使用本站16年以上
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产品型号K8P3215UQB-PI4B的概述

芯片K8P3215UQB-PI4B的概述 K8P3215UQB-PI4B是一款高性能、低功耗的片上系统(SoC)芯片,广泛应用于消费电子、物联网及通信设备等领域。该芯片集成了多个功能模块,具有较强的计算能力和丰富的接口,使其在现代电子设备中具有重要的应用价值。 这款芯片主要基于先进的微处理器架构,利用高集成度的设计,实现了高频工作与低功耗运行的优良平衡。其设计宗旨是满足当今市场对高效率与小型化的双重需求,为各种应用提供核心处理能力。 芯片K8P3215UQB-PI4B的详细参数 K8P3215UQB-PI4B的详细参数如下: - 处理器架构:采用ARM Cortex系列微处理器。 - 运行频率:最高可达1 GHz。 - 供电电压:1.2 V(工作电压范围倾向于低功耗优化)。 - 存储: - 内置RAM:512 MB。 - Flash存储:8 GB 可选。 - 接口: - U...

产品型号K8P3215UQB-PI4D0的Datasheet PDF文件预览

K8P3215UQB  
FLASH MEMORY  
32Mb B-die Page NOR Specification  
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,  
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.  
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,  
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,  
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL  
INFORMATION IN THIS DOCUMENT IS PROVIDED  
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.  
1. For updates or additional information about Samsung products, contact your nearest Samsung office.  
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar  
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or  
defense application, or any governmental procurement to which special terms or provisions may apply.  
* Samsung Electronics reserves the right to change products or specification without notice.  
1
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
Document Title  
32M Bit (2M x16) Page Mode / Multi-Bank NOR Flash Memory  
Revision History  
Revision No. History  
Draft Date  
Remark  
0.0  
Initial draft  
October 11, 2006  
Target  
Information  
0.1  
-Accelerated Program Time is changed from 4ns to 6ns.  
-Accelerated Quad Word Program Time is changed from 1.2ns to  
1.5ns.  
November 13, 2006 Target  
Information  
0.2  
0.3  
- Die version is changed E-die to B-die  
(K8P3215UQE --> K8P3215UQB)  
November 21, 2006 Target  
Information  
-64FBGA 13x11 with 1.0mm Ball Pitch is added.  
-56FBGA is deleted.  
January 15, 2007  
Target  
Information  
-48FBGA 6x8.5 is deleted.  
-56TSOP 20x14 is deleted.  
-CFI code is changed  
Data 00h is changed to 07h in address 35h  
Data 00h is changed to 20h in address 37h  
-Change Vih Min. from Vio-0.4(2.2) to Vio-0.4(Vccx0.8)  
-Change Vil Max. from 0.4(0.8) to 0.4(Vccx0.2)  
0.4  
- Group block protect time : 100us --> 120us  
- Group block unprotect time : 1.2ms --> 3ms  
February 08, 2007 Target  
Information  
In Figure 8. Block Group Protection & Unprotection Algorithms &  
Block Group Protect & Unprotect Operations timing  
0.5  
0.6  
1.0  
- Package Hight is changed from 1.3 ±0.10 to 1.2 ±0.10.  
February 15, 2007 Target  
Information  
- 48FBGA, 48TSOP dimension are added.  
March 22, 2007  
Preliminary  
- Specification is finalized.  
April 19, 2007  
- Package ’E’ is added in ordering information.  
1.1  
- "#OE or #CE should be toggled in each toggle bit status read." is April 23, 2007  
added in DQ2 & DQ6 toggle bit.  
2
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
32M Bit (2M x16) Page Mode / Multi-Bank NOR Flash Memory  
FEATURES  
Single Voltage, 2.7V to 3.6V for Read and Write operations  
Voltage range of 2.7V to 3.1V valid for MCP product  
Organization  
2M x16 bit (Word mode Only)  
Fast Read Access Time : 55ns  
Page Mode Operation  
8 Words Page access allows fast asychronous read  
Page Read Access Time : 20ns  
Endurance : 100,000 Program/Erase Cycles Minimum  
Data Retention : 10 years  
Vio options at 1.8V and 3V I/O  
Package options  
- 48 Pin TSOP (20x12mm)  
- 48 Ball FBGA (6x8mm, 0.8mm Ball Pitch)  
- 64 Ball FBGA (13x11mm, 1.0mm Ball Pitch)  
Read While Program/Erase Operation  
Multiple Bank architectures (4 banks)  
Bank 0: 4Mbit (4Kw x 8 and 32Kw x 7)  
Bank 1: 12Mbit (32Kw x 24)  
GENERAL DESCRIPTION  
Bank 2: 12Mbit (32Kw x 24)  
Bank 3: 4Mbit (4Kw x 8 and 32Kw x 7)  
OTP Block : Extra 256 word  
The K8P3215UQB featuring single 3.0V power supply, is an  
32Mbit NOR-type Flash Memory organized as 2Mx16. The  
memory architecture of the device is designed to divide its  
memory arrays into 78 blocks with independent hardware pro-  
tection. This block architecture provides highly flexible erase  
and program capability. The K8P3215UQB NOR Flash consists  
of four banks. This device is capable of reading data from one  
bank while programming or erasing in the other banks.  
The K8P3215UQB offers fast page access time of 20~30ns with  
random access time of 55~70ns. The devices fast access  
times allow high speed microprocessors to operate without wait  
states. The device performs a program operation in unit of 16  
bits (Word) and erases in units of a block. Single or multiple  
blocks can be erased. The block erase operation is completed  
within typically 0.7 sec. The device requires 17mA as program/  
erase current in the commercial and industrial temperature  
ranges.  
- 128word for factory and 128word for customer OTP  
Power Consumption (typical value)  
- Active Read Current : 45mA (@10MHz)  
- Program/Erase Current : 17mA  
- Read While Program or Read While Erase Current : 35mA  
- Standby Mode/Auto Sleep Mode : 15uA  
Support Single & Quad word accelerate program  
WP/ACC input pin  
- Allows special protection of two outermost boot blocks at VIL,  
regardless of block protect status  
- Removes special protection of two outermost boot block at VIH,  
the two blocks return to normal block protect status  
- Accelerated Quadword Program time : 1.5us  
Erase Suspend/Resume  
Program Suspend/Resume  
Unlock Bypass Program  
The K8P3215UQB NOR Flash Memory is created by using  
Samsung's advanced CMOS process technology. This device is  
available in 48 Pin TSOP package and 48/64 Ball FBGA pack-  
age. The device is compatible with EPROM applications to  
require high-density and cost-effective non-volatile read/write  
storage solutions.  
Hardware RESET Pin  
Command Register Operation  
Block Protection / Unprotection  
Supports Common Flash Memory Interface  
Operation Temperature Rnage  
- Industrial Temperature : -40°C to 85°C  
- Extended Temperature : -25°C to 85°C  
- Commercial Temperature : 0°C to 70°C  
PIN DESCRIPTION  
Pin Name  
Pin Function  
A0 - A20  
Address Inputs  
DQ0 - DQ15 Data Inputs / Outputs  
CE  
OE  
Chip Enable  
Output Enable  
RESET  
RY/BY  
WE  
Hardware Reset Pin  
Ready/Busy Output  
Write Enable  
WP/ACC  
Vcc  
Hardware Write Protection/Program Acceleration  
Power Supply  
VSS  
Ground  
N.C  
No Connection  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.  
3
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
PIN CONFIGURATION  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
A19  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
A16  
N.C  
Vss  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
DQ15  
DQ7  
DQ14  
DQ6  
DQ13  
DQ5  
DQ12  
DQ4  
Vcc  
DQ11  
DQ3  
DQ10  
DQ2  
DQ9  
DQ1  
DQ8  
DQ0  
OE  
48-pin TSOP1  
Standard Type  
12mm x 20mm  
A20  
WE  
RESET  
N.C  
WP/ACC  
RY/BY  
A18  
A17  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
Vss  
CE  
A0  
4
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
64 Ball FBGA TOP VIEW (BALL DOWN)  
G
H
E
F
B
A
D
C
8
NC  
NC  
NC  
NC  
NC  
Vss  
NC  
NC  
7
6
A13  
A9  
A12  
A8  
A14  
A10  
NC  
A15  
A11  
A19  
A20  
A16  
DQ7  
DQ5  
DQ2  
NC  
DQ15  
DQ13  
Vcc  
Vss  
DQ6  
DQ4  
DQ14  
DQ12  
5
4
WE  
RESET  
RY/BY  
A7  
WP/ACC  
A17  
A18  
A6  
DQ10  
DQ8  
DQ11  
DQ9  
DQ3  
DQ1  
A5  
DQ0  
3
2
1
A3  
A4  
A2  
A1  
A0  
CE  
NC  
OE  
NC  
Vss  
NC  
NC  
NC  
NC  
NC  
NC  
5
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
1
2
3
4
5
6
RY/  
BY  
A3  
A4  
A2  
A1  
A0  
A7  
A
A9  
A8  
A13  
WE  
WP/  
ACC  
A17  
B
C
A12  
A14  
RESET  
N.C  
A6  
A5  
A18  
A20  
A10  
A11  
D
A19  
A15  
E
F
DQ2  
DQ10  
DQ11  
DQ5  
DQ12  
Vcc  
A16  
DQ7  
DQ0  
DQ8  
DQ9  
DQ1  
DQ14  
CE  
RFU  
DQ15  
Vss  
DQ13  
DQ6  
G
H
OE  
DQ3  
DQ4  
Vss  
48 Ball FBGA TOP VIEW (BALL DOWN)  
FUNCTIONAL BLOCK DIAGRAM  
Bank 0  
Cell Array  
Bank 0  
Address  
X
Dec  
Latch &  
Control  
Y Dec  
Vcc  
Vss  
Latch &  
Control  
CE  
Y Dec  
OE  
Bank 1  
Cell Array  
Bank 1  
Address  
X
I/O  
Interface  
&
Dec  
WE  
Bank  
RESET  
RY/BY  
WP/ACC  
A0~A20  
DQ0~DQ15  
Control  
Bank 3  
Cell Array  
Bank 3  
Address  
X
Dec  
Latch &  
Control  
Y Dec  
Erase  
Control  
High  
Voltage  
Gen.  
Block  
Inform  
Program  
Control  
6
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
ORDERING INFORMATION  
K8 P 32 15 U Q B - P E 4 A  
Access Time  
4A = 55ns/20ns  
4B = 60ns/25ns  
4C = 65ns/25ns  
4D = 70ns/30ns  
Samsung  
NOR Flash Memory  
Operating Temperature Range  
Device Type  
Page Mode  
C = Commercial Temp. (0 °C to 70 °C)  
I = Industrial Temp. (-40 °C to 85 °C)  
E = Extended Temp. (-25 °C to 85 °C)  
Package  
Density & Bank Architecture  
P = TSOP1(Lead Free), D = FBGA(Lead Free)  
E = FBGA(Lead Free, 1.0mm ball pitch)  
32 Mbits & 4 Banks  
Organization  
x16  
Version  
3th Generation  
Operating Voltage Range  
Block Architecture  
2.7V to 3.6V  
Q = Top and Bottom Boot Block  
Table 1. PRODUCT LINE-UP  
Speed Item  
Speed Option  
4A  
4B  
4C  
4D  
Vcc  
2.7V~3.6V  
1.65~1.95V , 2.7~3.6V  
VIO (1)  
Max. Address Access Time (ns)  
Max. CE Access Time (ns)  
Max. OE Access Time (ns)  
Max. Page Access Time (ns)  
55ns  
55ns  
20ns  
20ns  
60ns  
60ns  
25ns  
25ns  
65ns  
70ns  
70ns  
30ns  
30ns  
65ns  
25ns  
25ns  
Notes :  
1. Only 4C or 4D speed options can be provided in case of using 1.65~1.95V V  
.
IO  
Table 2. K8P3215UQB DEVICE BANK DIVISIONS  
Bank 0, Bank 3  
Bank 1, Bank 2  
Mbit  
Block Sizes  
Mbit  
Block Sizes  
4 Kw x 8 and  
32 Kw x 7  
4 Mbit  
12 Mbit  
32 Kw x 24  
Table 3. OTP BLOCK  
Block Address  
Area  
Block Size  
Address Range  
A20~A8  
OTP  
Factory-Locked Area  
128 words  
128 words  
000000h-00007Fh  
000080h-0000FFh  
0000h  
Customer-Locked Area  
After entering OTP block, any issued addresses should be in the range of OTP block address  
7
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
Table 4. K8P3215UQB DEVICE BANK DIVISIONS  
Bank  
Number of Blocks  
Block Size  
4 Kwords  
8
7
0
32 Kwords  
32 Kwords  
32 Kwords  
32 Kwords  
4 Kwords  
1
2
24  
24  
7
3
8
8
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
PRODUCT INTRODUCTION  
The K8P3215UQB is an 32Mbit NOR-type Flash memory. The device features single voltage power supply operating within the  
range of 2.7V to 3.6V. The device is programmed by using the Channel Hot Electron (CHE) injection mechanism which is used to  
program EPROMs. The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To provide highly flexible  
erase and program capability, the device adapts a block memory architecture that divides its memory array into 78 blocks (4 Kw x 16  
, 32 Kw x 62). Programming is done in units of 16 bits (Word). All bits of data in one or multiple blocks can be erased simultaneously  
when the device executes the erase operation. To prevent the device from accidental erasing or over-writing the programmed data,  
78 memory blocks can be hardware protected. The device offers fast page access time of 20~30ns with random access time of  
55~70ns supporting high speed microprocessors to operate without any wait states.  
The command set of K8P3215UQB is fully compatible with standard Flash devices. The device is controlled by chip enable (CE), out-  
put enable (OE) and write enable (WE). Device operations are executed by selective command codes. The command codes to be  
combined with addresses and data are sequentially written to the command registers using microprocessor write timing. The com-  
mand codes serve as inputs to an internal state machine which controls the program/erase circuitry. Register contents also internally  
latch addresses and data necessary to execute the program and erase operations. The K8P3215UQB is implemented with Internal  
Program/Erase Algorithms to execute the program/erase operations. The Internal Program/Erase Algorithms are invoked by pro-  
gram/erase command sequences. The Internal Program Algorithm automatically programs and verifies data at specified addresses.  
The Internal Erase Algorithm automatically pre-programs the memory cell which is not programmed and then executes the erase  
operation. The K8P3215UQB has means to indicate the status of completion of program/erase operations. The status can be indi-  
cated via the RY/BY pin, Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device auto-  
matically resets itself to the read mode.  
Table 5. Operations Table  
WP/  
ACC  
DQ8/  
DQ15  
DQ0/  
DQ7  
Operation  
CE  
OE  
WE  
A9  
A6  
A1  
A0  
RESET  
Read  
L
H
L
L
X
H
X
H
H
H
X
H
X
H
X
L
L/H  
(2)  
A9  
X
A6  
X
A1  
X
A0  
X
DOUT  
High-Z  
High-Z  
High-Z  
DIN  
DOUT  
High-Z  
High-Z  
High-Z  
DIN  
H
(2)  
H
Stand-by  
Output Disable  
L/H  
L/H  
(4)  
X
X
X
X
Reset  
X
L
X
X
X
X
L
Write  
A9  
X
A6  
L
A1  
H
A0  
L
H
Enable Block Protect (3)  
Enable Block Unprotect (3)  
Temporary Block Unprotect  
Auto Select Manufacturer ID (5)  
L
L
L/H  
(4)  
X
DIN  
VID  
VID  
VID  
L
L
X
H
H
L
X
DIN  
X
X
(4)  
X
X
X
X
X
X
Code(See  
Table 7)  
L
L
L
L
H
H
L/H  
L/H  
VID  
VID  
L
L
L
L
L
X
X
H
H
Auto Select Device Code (5)  
Code(See  
Table 7)  
H
Notes :  
1. L = VIL (Low), H = VIH (High), VID = 8.5V to 9.5V, DIN = Data in, DOUT = Data out, X = Don't care.  
2. WP/ACC and RESET pin are asserted at Vcc±0.2 V or Vss±0.2 V in the Stand-by mode.  
3. Addresses must be composed of the Block address (A12 - A20).  
The Block Protect and Unprotect operations may be implemented via programming equipment too.  
Refer to the "Block Protection and Unprotection".  
4. If WP/ACC=VIL, the two outermost boot blocks is protected. If WP/ACC=VIH, the two outermost boot block protection depends on whether those  
blocks were last protected or unprotected using the method described in "Block Protection and Unprotection". If WP/ACC=VHH, all blocks  
will be temporarily unprotected.  
5. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 7.  
9
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
COMMAND DEFINITIONS  
The K8P3215UQB operates by selecting and executing its operational modes. Each operational mode has its own command set. In  
order to select a certain mode, a proper command with specific address and data sequences must be written into the command reg-  
ister. Writing incorrect information which include address and data or writing an improper command will reset the device to the read  
mode. The defined valid register command sequences are stated in Table 6. Note that Erase Suspend (B0H) and Erase Resume  
(30H) commands are valid only while the Block Erase Operation is in progress. Program Suspend (B0H) and Program Resume  
(30H) commands are valid during Program Operation and Erase Suspend - Program Operation. Only Read Operation is available  
after Program Suspend Operation.  
Table 6. Command Sequences  
Command Sequence  
Cycle  
1st Cycle  
R A  
2nd Cycle  
3rd Cycle  
4th Cycle  
5th Cycle  
6th Cycle  
Addr  
Data  
Read  
1
RD  
Addr  
Data  
Add  
XXXH  
F0H  
Reset  
1
4
4
4
4
4
555H  
AAH  
2AAH  
55H  
DA/555H  
90H  
DA/X00H  
ECH  
Autoselect  
Manufacturer ID (1,2)  
Data  
Addr  
Data  
Addr  
Data  
Addr  
Data  
Addr  
Data  
Addr  
Data  
Addr  
Data  
Addr  
Data  
Addr  
Data  
Addr  
Data  
Addr  
Data  
Addr  
Data  
Addr  
Data  
Addr  
Data  
Addr  
Data  
Addr  
Data  
Addr  
Data  
Addr  
Data  
555H  
AAH  
2AAH  
55H  
DA/555H  
90H  
DA/X01H  
257EH  
DA/X0EH  
2503H  
DA/X0FH  
2501H  
Autoselect Device Code  
(1,2,3)  
555H  
AAH  
2AAH  
55H  
DA/555H  
90H  
BA / X02H  
(See Table 7)  
Autoselect  
B l o c k P r o t e c t Ve r i f y ( 1 , 2 )  
555H  
AAH  
2AAH  
55H  
DA/555H  
90H  
X03H  
(See Note 10)  
PA  
Autoselect OTP Factory  
Protect  
2AAH  
555H  
555H  
AAH  
Program  
55H  
A0H  
PD  
2AAH  
555H  
555H  
AAH  
Unlock Bypass  
3
2
2
2
2
1
6
6
1
1
1
1
1
55H  
PA  
20H  
XXXH  
Unlock Bypass  
Program  
A0H  
PD  
XXXH  
BA  
Unlock Bypass  
Block Erase  
80H  
30H  
XXXH  
10H  
XXXH  
XXXH  
Unlock Bypass Chip Erase  
Unlock Bypass Reset  
Unlock Bypass CFI  
Chip Erase  
80H  
XXXH  
90H  
XXH  
98H  
00H  
2AAH  
555H  
555H  
555H  
10H  
BA  
555H  
AAH  
555H  
AAH  
DA  
2AAH  
55H  
55H  
80H  
AAH  
2AAH  
555H  
555H  
2AAH  
55H  
Block Erase  
55H  
80H  
AAH  
30H  
Block Erase Suspend  
(4, 5)  
B0H  
DA  
Block Erase Resume  
Program Suspend (6,7)  
Program Resume  
CFI Query (8)  
30H  
DA  
B0H  
DA  
30H  
55H  
98H  
10  
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
Table 6. Command Sequences (Continued)  
2nd  
Cycle  
Command Definitions  
Cycle  
1st Cycle  
3rd Cycle 4th Cycle 5th Cycle 6th Cycle  
Addr  
XXH  
A0H  
PA  
PD  
Accelerated Program  
Data  
2
Addr  
Quadruple word Accelerated Program(9)  
Data  
XXXH  
A5H  
PA1  
PA2  
PD2  
555H  
88H  
PA3  
PD3  
PA4  
PD4  
5
3
4
6
5
PD1  
2AAH  
55H  
Addr  
555H  
AAH  
555H  
AAH  
555H  
AAH  
555H  
AAH  
Enter OTP Block Region  
Data  
Addr  
2AAH  
55H  
555H  
90H  
XXX  
00H  
OW  
68H  
OW  
48H  
Exit OTP Block Region  
Data  
Addr  
2AAH  
55H  
555H  
60H  
OW  
48H  
OW  
OTP Protection bit Program (11,12)  
Data  
RD(0)  
Addr  
2AAH  
55H  
555H  
60H  
OW  
OTP Protection bit Status  
Data  
RD(0)  
Notes : RA : Read Address, PA : Program Address, RD : Read Data, PD : Program Data  
DA : Bank Address (A19- A20), BA : Block Address (A12 - A20), ABP : Address of the block to be protected or unprotected, X = Don’t care .  
OW = Address (A7:A0) is (00011010), RD(0) = Read Data DQ0 for protection indicator bit ,RD(1) = Read Data DQ1 for PPB Lock status.  
DQ8 - DQ15 are don’t care in command sequence, except for RD and PD.  
A11 - A20 are also don’t care, except for the case of special notice.  
1. To terminate the Autoselect Mode, it is necessary to write Reset command to the register.  
2. The 4th cycle data of Autoselect mode is output data.  
The 3rd and 4th cycle bank addresses of Autoselect mode must be same.  
3. Device ID must be read across cycles 4, 5 and 6.  
K8P2815U(xOEh = 2508h, x0Fh = 2501h), K8P6415U(xOEh = 2506h, x0Fh = 2501h), K8P3215U(xOEh = 2503h, x0Fh = 2501h)  
4. The Read / Program operations at non-erasing blocks and the autoselect mode are allowed in the Erase Suspend mode.  
5. The Erase Suspend command is applicable only to the Block Erase operation.  
6. The Read Operation is allowed in the Program Suspend mode.  
7. The Program Suspend command is applicable to Program and Erase Suspend - Program operation.  
8. Command is valid when the device is in read mode or Autoselect mode.  
9. Quadruple word accelerated program is invoked only at Vpp=Vid, Vpp setup is required prior to this command sequence.  
PA1,PA2,PA3,PA4 have the same A20~A2 address  
10. The data is DQ6=1 for customer locked and DQ7=1 for factory locked.  
11. Reset command returns device to reading array.  
12. Cycle 4 programs the addressed locking bit. Cycle 5 and 6 validate bit has been fully programmed when DQ0=1. If DQ0=0 in cycle 6,  
program command must be issued and verified again.  
Table 7. K8P3215UQB Autoselect Codes, (High Voltage Method)  
A20  
to  
A5  
to  
DQ7  
to  
Description  
CE  
OE WE  
A10 A9 A8 A7 A6  
A3 A2 A1 A0  
DQ15  
A12  
A4  
to DQ8  
DQ0  
Manufacturer ID  
L
L
L
H
H
DA  
X
X
VID  
VID  
X
X
L
L
L
L
X
L
L
L
L
X
ECH  
Read Cycle 1  
L
H
H
L
H
H
L
H
H
H
L
25H  
25H  
25H  
7EH  
03H  
01H  
Devi  
ce  
ID  
Read Cycle 2  
Read Cycle 3  
L
L
DA  
L
H
Block Protection Veri-  
fication  
01H(Proected)  
00H (Unproteced)  
L
H
BA  
X
VID  
X
L
L
L
L
L
H
L
X
OTP Indicator Bit  
(DQ7. DQ6)  
D Q 7 = 1 ( F a c t o r y lo c k e d )  
DQ6=1(Customer  
locked)  
L
L
L
L
H
H
DA  
BA  
X
X
VID  
VID  
X
X
X
L
L
L
L
L
L
L
L
H
H
H
H
X
X
Master locking bit  
Indicator Bit  
01H(Proected)  
00H (Unproteced)  
H
Notes : 1. L=Logic Low=VIL, H=Logic High=VIH, DA= Bank Address, BA=Block Address, X=Don’t care.  
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DEVICE OPERATION  
Read Mode  
The K8P3215UQB is controlled by Chip Enable (CE), Output Enable (OE) and Write Enable (WE). When CE and OE are low and  
WE is high, the data stored at the specified address location,will be the output of the device. The outputs are in high impedance state  
whenever CE or OE is high. The K8P3215UQB is available for Page mode. Page mode provides fast access time for high perfor-  
mance system.  
Standby Mode  
The K8P3215UQB features Stand-by Mode to reduce power consumption. This mode puts the device on hold when the device is  
deselected by making CE high (CE = VIH). Refer to the DC characteristics for more details on stand-by modes.  
Output Disable  
The device outputs are disabled when OE is High (OE = VIH). The output pins are in high impedance state.  
Automatic Sleep Mode  
The K8P3215UQB features Automatic Sleep Mode to minimize the device power consumption. When addresses remain steady for  
tAA+30ns, the device automatically activates the Automatic Sleep Mode. In the sleep mode, output data is latched and always avail-  
able to the system. When addresses are changed, the device provides new data without wait time.  
tAA + 30ns  
Address  
Outputs  
Data  
Data  
Data  
Data  
Data  
Data  
Auto Sleep Mode  
Figure 1. Auto Sleep Mode Operation  
Autoselect Mode  
The K8P3215UQB offers the Autoselect Mode to identify manufacturer, device type and block protection verification by reading a  
binary code. The Autoselect Mode allows programming equipment to automatically match the device to be programmed with its cor-  
responding programming algorithm. In addition, this mode allows the verification of the status of write protected blocks. This mode is  
used by two method. The one is high voltage method to be required VID (8.5V - 9.5V) on address pin A9. When A9 is held at VID and  
the bank address or block address is asserted, the device outputs the valid data via DQ pins(see Table 7 and Figure 2). The rest of  
addresses except A0, A1 and A6 are dont care. The other is autoselect command method that the autoselect code is accessable by  
the commamd sequence without VID. The manufacturer, device code and block protection verification can be read via the command  
register. The Command Sequence is shown in Table 7 and Figure 3. The autoselect operation of block protection verification is initi-  
ated by first writing two unlock cycle. The third cycle must contain the bank address and autoselect command (90H). If Block address  
while (A6, A1, A0) = (0,1,0) is finally asserted on the address pin, it will produce a logical "1" at the device output DQ0 to indicate a  
write protected block or a logical "0" at the device output DQ0 to indicate a write unprotected block. To terminate the autoselect oper-  
ation, write Reset command (F0H) into the command register.  
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VID  
V = VIH or VIL  
A9  
0EH  
0FH  
01H  
00H  
A6,A1,A0*  
ECH  
DQ15-DQ0  
257EH  
2503H  
2501H  
Manufacturer ID  
Device ID  
(K8P3215UQB)  
Return to  
Read Mode  
Note : The addresses other than A0 , A1 and A6 are Dont care. Please refer to Table 7 for device code.  
Figure 2. Autoselect Operation ( by High Voltage Method )  
WE  
Address  
2AAH  
01H  
0EH  
0FH  
555H  
555H  
00H  
ECH  
2501H  
DQ15DQ0  
55H  
90H  
257EH  
2503H  
AAH  
Manufacturer ID  
Device ID  
(K8P3215UQB)  
Note : The 3rd Cycle and 4th Cycle address must include the same bank address. Please refer to Table 7 for device code.  
Figure 3. Autoselect Operation ( by Command Sequence Method )  
Write (Program/Erase) Mode  
The K8P3215UQB executes its program/erase operations by writing commands into the command register. In order to write the com-  
mands to the register, CE and WE must be low and OE must be high. Addresses are latched on the falling edge of CE or WE (which-  
ever occurs last) and the data are latched on the rising edge of CE or WE (whichever occurs first). The device uses standard  
microprocessor write timing.  
Program  
The K8P3215UQB can be programmed in units of a word. Programming is writing 0's into the memory array by executing the Internal  
Program Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two  
cycles are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address of the memory  
location and the data to be programmed at that location are written. The device automatically generates adequate program pulses  
and verifies the programmed cell margin by the Internal Program Routine. During the execution of the Routine, the system is not  
required to provide further controls or timings.  
During the Internal Program Routine, commands written to the device will be ignored. Note that a hardware reset during a program  
operation will cause data corruption at the corresponding location.  
WE  
555H  
2AAH  
555H  
Program  
Address  
Address  
Program  
Data  
A0H  
55H  
AAH  
DQ15-DQ0  
RY/BY  
Program  
Start  
Figure 4. Program Command Sequence  
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In accross block boundaries and any sequence programming is allowed. A bit cannot be programmed from ’0’ back to ’1’. If attempt-  
ing to do, it may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful.  
However, a succeeding read will show that the data is still ’0’. Only erase operations can convert a ’0’ to a ’1’.  
Unlock Bypass  
The K8P3215UQB provides the unlock bypass mode to save its operation time. This mode is possible for program, block erase and  
chip erase operation. There are two methods to enter the unlock bypass mode. The mode is invoked by the unlock bypass command  
sequence. Unlike the standard program/erase command sequence that contains four to six bus cycles, the unlock bypass program/  
erase command sequence comprises only two bus cycles. The unlock bypass mode is engaged by issuing the unlock bypass com-  
mand sequence which is comprised of three bus cycles. Writing first two unlock cycles is followed by a third cycle containing the  
unlock bypass command (20H). Once the device is in the unlock bypass mode, the unlock bypass program/erase command  
sequence is necessary. The unlock bypass program command sequence is comprised of only two bus cycles; writing the unlock  
bypass program command (A0H) is followed by the program address and data. This command sequence is the only valid one for  
programming the device in the unlock bypass mode. Also, The unlock bypass erase command sequence is comprised of two bus  
cycles; writing the unlock bypass block erase command(80H-30H) or writing the unlock bypass chip erase command(80H-10H). This  
command sequences are the only valid ones for erasing the device in the unlock bypass mode. The unlock bypass reset command  
sequence is the only valid command sequence to exit the unlock bypass mode. The unlock bypass reset command sequence con-  
sists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains only the data (00H). Then, the device  
returns to the read mode.  
Chip Erase  
To erase a chip is to write 1s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus  
cycles to write the command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two  
more write cycles prior to writing the chip erase command. The Internal Erase Routine automatically pre-programs and verifies the  
entire memory for an all zero data pattern prior to erasing. The automatic erase begins on the rising edge of the last WE or CE pulse  
in the command sequence and terminates when DQ7 is "1". After that the device returns to the read mode.  
WE  
555H  
2AAH  
555H  
555H  
2AAH  
555H  
Address  
DQ15-DQ0  
RY/BY  
80H  
55H  
AAH  
AAH  
10H  
55H  
Chip Erase  
Start  
Figure 5. Chip Erase Command Sequence  
Block Erase  
To erase a block is to write 1s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six  
bus cycles to write the command sequence shown in Table 6. After the first two "unlock" cycles, the erase setup command (80H) is  
written at the third cycle. Then there are two more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine  
automatically pre-programs and verifies the entire memory prior to erasing it. The block address is latched on the falling edge of WE  
or CE, while the Block Erase command is latched on the rising edge of WE or CE.  
Multiple blocks can be erased sequentially by writing the six bus-cycle operation in Figure 6. Upon completion of the last cycle for the  
Block Erase, additional block address and the Block Erase command (30H) can be written to perform the Multi-Block Erase. An 50us  
(typical) "time window" is required between the Block Erase command writes. The Block Erase command must be written within the  
50us "time window", otherwise the Block Erase command will be ignored. The 50us "time window" is reset when the falling edge of  
the WE occurs within the 50us of "time window" to latch the Block Erase command. During the 50us of "time window", any command  
other than the Block Erase or the Erase Suspend command written to the device will reset the device to read mode. After the 50 us  
of "time window", the Block Erase command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase  
address and command following the exceeded "time window" may or may not be accepted. No other commands will be recognized  
except the Erase Suspend command.  
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WE  
555H  
2AAH  
555H  
555H  
2AAH  
Block  
Address  
Address  
80H  
DQ15-DQ0  
55H  
AAH  
AAH  
30H  
55H  
Block Erase  
Start  
RY/BY  
Figure 6. Block Erase Command Sequence  
Erase Suspend / Resume  
The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. The Erase Sus-  
pend command is only valid during the Block Erase operation including the time window of 50us. The Erase Suspend command is  
not valid while the Chip Erase or the Internal Program Routine sequence is running.  
When the Erase Suspend command is written during a Block Erase operation, the device requires a maximum of 20us to suspend  
the erase operation. But, when the Erase Suspend command is written during the block erase time window (50us) , the device imme-  
diately terminates the block erase time window and suspends the erase operation.  
After the erase operation has been suspended, the device is availble for reading or programming data in a block that is not being  
erased. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode.  
When the Erase Resume command is executed, the Block Erase operation will resume. When the Erase Suspend or Erase Resume  
command is executed, the addresses are in Don't Care state.  
WE  
555H  
Block  
Address  
Address  
XXXH  
XXXH  
30H  
AAH  
B0H  
30H  
DQ15-DQ0  
Block Erase  
Command Sequence  
Erase  
Resume  
Block Erase  
Start  
Erase  
Suspend  
Figure 7. Erase Suspend/Resume Command Sequence  
Program Suspend / Resume  
The Program Suspend command interrupts the Program operation. Also the Program Suspend command interrupts the Program  
operation during Erase Suspend Mode. The Read operation is available only during Program Suspend. When the Program Suspend  
command is written during a Program operation, the device requires a maximum of 10us to suspend the Program operation. The  
system may also write the autoselect command sequence when the device is in the Program Suspend mode. When the Program  
Resume command is executed, the Program operation will resume. When the Program Suspend or Program Resume command is  
executed, the addresses are in Don't Care state.  
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Read While Write  
The K8P3215UQB provides multi-bank memory architecture that divides the memory array into four banks. The device is capable of  
reading data from one bank and writing data to the other bank simultaneously. This is so called the Read While Write operation with  
multi-bank architecture; this feature provides the capability of executing the read operation during Program/Erase or Erase-Suspend-  
Program operation. The Read While Write operation is prohibited during the chip erase operation. It is also allowed during erase  
operation when either single block or multiple blocks from same bank are loaded to be erased. It means that the Read While Write  
operation is prohibited when blocks from one Bank and another blocks from the other Bank are loaded all together for the multi-block  
erase operation.  
Write Protect (WP)  
The WP/ACC pin has two useful functions. The one is that certain boot block is protected by the hardware method not to use VID.  
The other is that program operation is accelerated to reduce the program time (Refer to Accelerated program Operation Paragraph).  
When the WP/ACC pin is asserted at VIL, the device can not perform program and erase operation in the two "outermost" 4Kword  
boot blocks on both ends of the flash array independently of whether those blocks were protected or unprotected using the method  
described in "Block protection/Unprotection". ( BA77 and BA76, BA0 and BA1)  
The write protected blocks can only be read. This is useful method to preserve an important program data.  
When the WP/ACC pin is asserted at VIH, the device reverts to whether the two outermost 4Kword boot blocks were last set to be  
protected or unprotected. That is, block protection or unprotection for these two blocks depends on whether they were last protected  
or unprotected using the method described in "Block protection/unprotection".  
Recommend that the WP/ACC pin must not be in the state of floating or unconnected, otherwise the device may be led to malfunc-  
tion.  
Software Reset  
The reset command provides that the bank is reseted to read mode or erase-suspend-read mode. The addresses are in Don't Care  
state. The reset command is vaild between the sequence cycles in an erase command sequence before erasing begins, or in a pro-  
gram command sequence before programming begins. This resets the bank in which was operating to read mode. if the device is be  
erasing or programming, the reset command is invalid until the operation is completed. Also, the reset command is valid between the  
sequence cycles in an autoselect command sequence. In the autoselect mode, the reset command returns the bank to read mode. If  
a bank entered the autoselect mode in the Erase Suspend mode, the reset command returns the bank to erase-suspend-read mode.  
If DQ5 is high on erase or program operation, the reset command return the bank to read mode or erase-suspend-read mode if the  
bank was in the Erase Suspend state.  
Hardware Reset  
The K8P3215UQB offers a reset feature by driving the RESET pin to VIL. The RESET pin must be kept low (VIL) for at least 500ns.  
When the RESET pin is driven low, any operation in progress will be terminated and the internal state machine will be reset to the  
standby mode after 20us. If a hardware reset occurs during a program operation, the data at that particular location will be lost. Once  
the RESET pin is taken high, the device requires 200ns of wake-up time until outputs are valid for read access. Also, note that all the  
data output pins are tri-stated for the duration of the RESET pulse.  
The RESET pin may be tied to the system reset pin. If a system reset occurs during the Internal Program and Erase Routine, the  
device will be automatically reset to the read mode ; this will enable the systems microprocessor to read the boot-up firmware from  
the Flash memory.  
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Power-up Protection  
To avoid initiation of a write cycle during Vcc Power-up, RESET low must be asserted during power-up. After RESET goes high, the  
device is reset to the read mode.  
Low Vcc Write Inhibit  
To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than 2.3V. If Vcc <  
VLKO (Lock-Out Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the device  
will reset itself to the read mode. Subsequent writes will be ignored until the Vcc level is greater than VLKO. It is the users responsi-  
bility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above 2.3V.  
Write Pulse Glitch Protection  
Noise pulses of less than 5ns(typical) on CE, OE, or WE will not initiate a write cycle.  
Logical Inhibit  
Writing is inhibited under any one of the following conditions : OE = VIL, CE = VIH or WE = VIH. To initiate a write, CE and WE must  
be "0", while OE is "1".  
Commom Flash Memory Interface  
Common Flash Momory Interface is contrived to increase the compatibility of host system software. It provides the specific informa-  
tion of the device, such as memory size, word configuration, and electrical features. Once this information has been obtained, the  
system software will know which command sets to use to enable flash writes, block erases, and control the flash component.  
When the system writes the CFI command(98H) to address 55H in word mode, the device enters the CFI mode. And then if the sys-  
tem writes the address shown in Table 8, the system can read the CFI data. Query data are always presented on the lowest-order  
data outputs(DQ0-7) only. In word(x16) mode, the upper data outputs(DQ8-15) is 00h. To terminate this operation, the system must  
write the reset command.  
OTP Block Region  
The OTP Block feature provides a 256-word Flash memory region that enables permanent part identification through an Electronic  
Serial Number (ESN). The OTP Block is customer lockable and shipped with itself unlocked, allowing customers to untilize the that  
block in any manner they choose. Indicator bits DQ6 and DQ7 are used to indicate the factory-locked and customer locked status of  
the part. The data is DQ6 = "1" for customer locked and DQ7 = "1" for factory locked.  
The system accesses the OTP Block through a command sequence (see "Enter OTP Block / Exit OTP Block Command sequence"  
at Table 6). After the system has written the "Enter OTP Block" Command sequence, it may read the OTP Block by using the  
addresses (000000h~0000FFh) normally and may check the Protection Verify Bit (DQ7,DQ6) by using the "Autoselect Block Protec-  
tion Verify" Command sequence with OTP Block address. This mode of operation continues until the system issues the "Exit OTP  
Block" Command suquence, a hardware reset or until power is removed from the device. On power-up, or following a hardware  
reset, the device reverts to sending commands to main blocks. Note that the Accelerated function and unlock bypass modes are not  
available when the OTP Block is enabled.  
Customer Lockable  
In a Customer lockable device, The OTP Block is one-time programmable and can be locked only once. Note that the Accelerated  
programming and Unlock bypass functions are not available when programming the OTP Block. Locking operation to the OTP Block  
is started by writing the "Enter OTP Block" Command sequence, and it can be permanently locked to "1" by issuing the OTP Protec-  
tion bit program Command sqeunce. Once the OTP block is locked and verified, the system must write the Exit OTP block command  
to return to reading and writing the remainder of the array.  
OTP Protection Bits  
OTP protection bits prevent programming of the OTP block memory area. Once set, the OTP area are non-modifiable.  
The OTP Block Lock operation must be used with caution since, once locked, there is no procedure available for unlocking and none of the  
bits in the OTP Block space can be modified in any way.  
Suspend and resume operation are not supported during OTP protect, nor is OTP protect supported during any suspend operation.  
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High Voltage Block Protection  
Block protection and unprotection may also be implemented using programming equipment. The procedure requires high voltage  
(Vid) to be placed on the RESET# pin. Refer to Figure 8 for details on this procedure. Note that for block unprotect, all unprotected  
blocks must first be protected prior to the first sector write cycle.  
Accelerated Program Operation  
Accelerated program operation is one of two functions provided by the WP/ACC pin. When the WP/ACC pin is asserted as VHH, the  
device automatically enters the Unlock Bypass mode, temporarily unprotecting any protected blocks. The system would use a two-  
cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP/ACC pin returns the  
device to normal operation.  
Recommend that the WP/ACC pin must not be asserted at VHH except on accelerated program operation, or the device may  
be damaged. In addition, the WP/ACC pin must not be in the state of floating or unconnected, otherwise the device may  
be led to malfunction.  
Single word accelerated program operation  
The system would use two-cycle program sequence (One-cycle (XXX - A0H) is for single word program command, and Next one-  
cycle (PA - PD) is for program address and data ).  
Quadruple word accelerated program operation  
As well as Single word accelerated program, the system would use five-cycle program sequence (One-cycle (XXX - A5H) is for qua-  
druple word program command, and four cycles are for program address and data).  
Only four words programming is possible  
Each program address must have the same A20~A2 address  
The device automatically generates adequate program pulses and ignores other command after program command  
Program/Erase cycling must be limited below 100cycles for optimum performance.  
Read while Write mode is not guaranteed  
Requirements : Ambient temperature : TA=30°C±10°C  
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START  
COUNT = 1  
RESET=VID  
Wait 4µs  
No  
First Write  
Temporary Block Group  
Cycle=60h?  
Unprotect Mode  
Yes  
Yes  
No  
Block Group  
Protection ?  
No  
Block Unprotect  
Algorithm  
Block Protect  
Algorithm  
Yes  
All Block Groups  
Protected ?  
Set up Block Group  
Block Group <i>, i= 0  
address  
Block Group Unprotect  
Write 60H  
with  
Block Group Protect:  
Write 60H to Block  
Group address with  
A6=0,A1=1  
A6=1,A1=1  
A0=0  
A0=0  
Wait 3ms  
Wait 120µs  
Reset  
Verify Block Group  
Unprotect:Write 40H to  
Block Group address  
with A6=1,  
COUNT=1  
Verify Block Group  
Protect:Write 40H to  
Block Group address  
with A6=0,  
Increment  
COUNT  
A1=1,A0=0  
Increment  
COUNT  
A1=1,A0=0  
Read from  
Block Group address  
with A6=1,  
Read from  
Block Group address  
with A6=0,  
A1=1,A0=0  
Set up next Block  
Group address  
A1=1,A0=0  
No  
No  
No  
COUNT  
=1000?  
Data=00h?  
Yes  
No  
COUNT  
=25?  
Data=01h?  
Yes  
Yes  
Yes  
No  
Last Block Group  
verified ?  
Device failed  
Protect another  
Block Group?  
Device failed  
Yes  
Yes  
Remove VID  
from RESET  
No  
Remove VID  
from RESET  
Write RESET  
command  
Write RESET  
command  
END  
END  
Note : All blocks must be protected before unprotect operation is executing.  
Figure 8. Block Group Protection & Unprotection Algorithms  
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Table 8. Block Protection Schemes  
DYB  
0
PPB  
0
PPB Lock  
Block State  
0
1
Unprotected-PPB and DYB are changeable  
0
0
Unprotected-PPB not changeable and DYB are changeable  
0
1
1
0
1
1
1
0
1
1
0
1
0
0
0
1
1
1
Protected-PPB and DYB are changeable  
Protected-PPB not changeable, DYB is changeable  
Block Protection  
The K8P3215UQB features several levels of block protection, which can disable both the program and erase operations in certain  
blocks or block groups:  
Persistent Block Protection  
A command block protection method that replaces the old 12 V controlled protection method.  
Password Block Protection  
A highly sophisticated protection method that requires a password before changes to certain blocks or block groups are permitted  
Selecting a Block Protection Mode  
All parts default to operate in the Persistent Block Protection mode. The customer must then choose if the Persistent or Password  
Protection method is most desirable. There are two one-time programmable non-volatile bits that define which block protection-  
method will be used. If the Persistent Block Protection method is desired, programming the Persistent Block Protection Mode Lock-  
ing Bit permanently sets the device to the Persistent Block Protection mode. If the Password Block Protection method is desired,  
programming the Password Mode Locking Bit permanently sets the device to the Password Block Protection mode.  
It is not possible to switch between the two protection modes once a locking bit has been set. One of the two modes must be  
selected when the device is first programmed. This prevents a program or virus from later setting the Password Mode Locking Bit,  
which would cause an unexpected shift from the default Persistent Block Protection Mode into the Password Protection Mode.  
The device is shipped with all blocks unprotected. Optional Samsung programming services enable programming and protecting  
blocks at the factory prior to shipping the device. Contact your local sales office for details.  
It is possible to determine whether a block is protected or unprotected. See Autoselect Mode for details.  
Persistent Block Protection  
The Persistent Block Protection method replaces the 12 V controlled protection method in previous flash devices. This new method  
provides three different block protection states:  
Persistently Locked - The block is protected and cannot be changed.  
Dynamically Locked - The block is protected and can be changed by a simple command.  
Unlocked - The block is unprotected and can be changed by a simple command.  
To achieve these states, three types of "bits" are used:  
Persistent Protection Bit  
Persistent Protection Bit Lock  
Persistent Block Protection Mode Locking Bit  
Persistent Protection Bit (PPB)  
A single Persistent (non-volatile) Protection Bit is assigned to a maximum four blocks (see the block address tables for specific  
block protection groupings). All 4 Kword boot-block sectors have individual block Persistent Protection Bits(PPBs) for greater flexi-  
bility. Each PPB is individually modifiable through the PPB Write Command.  
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The device erases all PPBs in parallel. If any PPB requires erasure, the device must be instructed to preprogram all of the block PPBs  
prior to PPB erasure. Otherwise, a previously erased block PPBs can potentially be over-erased. The flash device does not have a  
built-in means of preventing block PPBs over-erasure.  
Persistent Protection Bit Lock (PPB Lock)  
The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to "1", the PPBs cannot be changed. When cleared "0",  
the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset.  
There is no command sequence to unlock the PPB Lock.  
Dynamic Protection Bit (DYB)  
A volatile protection bit is assigned for each block. After power-up or hardware reset, the contents of all DYBs is "0". Each DYB is indi-  
vidually modifiable through the DYB Write Command.  
When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is defaulted to power up in the cleared  
state - meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (blocks not protected). The  
Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that block. For the blocks that have  
the PPBs cleared, the DYBs control whether or not the block is protected or unprotected.  
By issuing the DYB Write command sequences, the DYBs will be set or cleared, thus placing each block in the protected or unpro-  
tected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to  
switch back and forth between the protected and unprotected conditions. This allows software to easily protect blocks against inadvert-  
ent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often  
as needed.  
The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because  
they are non-volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of pro-  
gram and erasing commands. The PPBs are also limited to 100 erase cycles.  
The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be  
set to "1". Setting the PPB Lock disables all program and erase commands to the non-volatile PPBs. In effect, the PPB Lock Bit locks  
the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine  
if any changes to the PPB are needed; for example, to allow new system code to be downloaded. If no changes are needed then the  
boot code can set the PPB Lock to disable any further changes to the PPBs during system operation.  
The WP#/ACC write protect pin adds a final level of hardware protection to blocks BA141 and BA140, BA0 and BA1. When this pin is  
low it is not possible to change the contents of these blocks. These blocks generally hold system boot code. The WP#/ACC pin can  
prevent any changes to the boot code that could override the choices made while setting up block protection during system initializa-  
tion.  
For customers who are concerned about malicious viruses there is another level of security - the persistently locked state. To persis-  
tently protect a given block or block group, the PPBs associated with that block need to be set to "1". Once all PPBs are programmed  
to the desired settings, the PPB Lock should be set to "1". Setting the PPB Lock automatically disables all program and erase com-  
mands to the Non-Volatile PPBs. In effect, the PPB Lock "freezes" the PPBs into their current state. The only way to clear the PPB  
Lock is to go through a power cycle.  
It is possible to have blocks that have been persistently locked, and blocks that are left in the dynamic state. The blocks in the dynamic  
state are all unprotected. If there is a need to protect some of them, a simple DYB Write command sequence is all that is necessary.  
The DYB write command for the dynamic blocks switch the DYBs to signify protected and unprotected, respectively. If there is a need  
to change the status of the persistently locked blocks, a few more steps are required. First, the PPB Lock bit must be disabled by either  
putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the  
PPB lock bit once again will lock the PPBs, and the device operates normally again.  
The best protection is achieved by executing the PPB lock bit set command early in the boot code, and protect the boot code by hold-  
ing WP#/ACC = VIL.  
Table 8 contains all possible combinations of the DYB, PPB, and PPB lock relating to the status of the block.  
In summary, if the PPB is set, and the PPB lock is set, the block is protected and the protection can not be removed until the next  
power cycle clears the PPB lock. If the PPB is cleared, the block can be dynamically locked or unlocked. The DYB then controls  
whether or not the block is protected or unprotected.  
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If the user attempts to program or erase a protected block, the device ignores the command and returns to read mode. A program  
command to a protected block enables status polling for approximately 1us before the device returns to read mode without having  
modified the contents of the protected block. An erase command to a protected block enables status polling for approximately 50us  
after which the device returns to read mode without having erased the protected block.  
The programming of the DYB, PPB, and PPB lock for a given block can be verified by writing a DYB/PPB/PPB lock verify command  
to the device.  
Persistent Block Protection Mode Locking Bit  
Like the password mode locking bit, a Persistent Block Protection mode locking bit exists to guarantee that the device remain in soft-  
ware block protection. Once set, the Persistent Block Protection locking bit prevents programming of the password protection mode  
locking bit. This guarantees that a hacker could not place the device in password protection mode.  
Password Protection Mode  
The Password Block Protection Mode method allows an even higher level of security than the Persistent Block Protection Mode.  
There are two main differences between the Persistent Block Protection and the Password Block Protection Mode:  
When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the  
unlocked state.  
The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device.  
The Password Block Protection method is otherwise identical to the Persistent Block Protection method.  
A 64-bit password is the only additional tool utilized in this method.  
Once the Password Mode Locking Bit is set, the password is permanently set with no means to read, program, or erase it. The pass-  
word is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The  
flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock bit is cleared,  
and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2us delay for each "password  
check." This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the pass-  
word.  
Password and Password Mode Locking Bit  
In order to select the Password block protection scheme, the customer must first program the password. The password may be cor-  
related to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device;  
therefore each password should be different for every flash device. While programming in the password region, the customer may  
perform Password Verify operations.  
Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves  
two objectives:  
Permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function.  
Disables all further commands to the password region. All program, and read operations are ignored.  
Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that  
the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure  
that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is  
no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be  
no way to clear the PPB Lock bit.  
The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming.  
The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Block Protection  
Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed.  
64-bit Password  
The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify com-  
mands (see "Password Verify Command"). The password function works in conjunction with the Password Mode Locking Bit, which  
when set, prevents the Password Verify command from reading the contents of the password on the pins of the device.  
Write Protect (WP#)  
The Write Protect feature provides a hardware method of protecting the upper two and lower two blocks without using VID. This func-  
tion is provided by the WP# pin and overrides the previously discussed "High Voltage Block Protection" section method.  
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If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two outermost 4 Kword blocks  
on both ends of the flash array independent of whether it was previously protected or unprotected.  
If the system asserts VIH on the WP#/ACC pin, the device reverts the upper two and lower two blocks to whether they were last set  
to be protected or unprotected. That is, block protection or unprotection for these sectors depends on whether they were last pro-  
tected or unprotected using the method described in the "High Voltage Block Protection" section.  
Persistent Protection Bit Lock  
The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset.  
If the Password Mode Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the ONLY means for clear-  
ing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password  
Unlock command clears the PPB Lock Bit, allowing for block PPBs modifications. Asserting RESET#, taking the device through a  
power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a "1" when the Password Mode Lock Bit is not  
set.  
If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hard-  
ware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock  
Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode.  
Master locking bit set  
This Master locking bit can ensure that protected blocks be permanently unalterable.  
Master locking bit is non-volatile bit. Master locking bit controls protection status of entire blocks.  
The usage of the master locking bit command sequence is absolutely required to ensure full protection of data from future alterations.  
If master locking bit is set ("1"), entire blocks are permanently protected. They are not changed and altered by any future lock/unlock  
commands.  
Anyone who uses this fuction needs much attention. Because there is no way to return to unlock status. Default status of master lock-  
ing bit is unlock status("0").  
If Master locking bit sets on unprotected block, the block still are remaining in status of unprotected block.  
The unprotected block can be protected by protection command.  
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Table 9. K8P3215UQB Boot Block/Block Addresses for Protection / Unprotection  
Block  
A20-A12  
000000000  
000000001  
Block Size  
4 Kwords  
4 Kwords  
BA0  
BA1  
BA2  
BA3  
BA4  
BA5  
BA6  
BA7  
BA8  
BA9  
BA10  
000000010  
000000011  
000000100  
000000101  
000000110  
000000111  
000001XXX  
000010XXX  
000011XXX  
0001XXXXX  
4 Kwords  
4 Kwords  
4 Kwords  
4 Kwords  
4 Kwords  
4 Kwords  
32 Kwords  
32 Kwords  
32 Kwords  
BA11-BA14  
BA15-BA18  
BA19-BA22  
BA23-BA26  
BA27-BA30  
BA31-BA34  
BA35-BA38  
BA39-BA42  
BA43-BA46  
BA47-BA50  
BA51-BA54  
BA55-BA58  
BA59-BA62  
BA63-BA66  
BA67  
128 (4x32) Kwords  
128 (4x32) Kwords  
128 (4x32) Kwords  
128 (4x32) Kwords  
128 (4x32) Kwords  
128 (4x32) Kwords  
128 (4x32) Kwords  
128 (4x32) Kwords  
128 (4x32) Kwords  
128 (4x32) Kwords  
128 (4x32) Kwords  
128 (4x32) Kwords  
128 (4x32) Kwords  
128 (4x32) Kwords  
32 Kwords  
0010XXXXX  
0011XXXXX  
0100XXXXX  
0101XXXXX  
0110XXXXX  
0111XXXXX  
1000XXXXX  
1001XXXXX  
1010XXXXX  
1011XXXXX  
1100XXXXX  
1101XXXXX  
1110XXXXX  
111100XXX  
111101XXX  
111110XXX  
111111000  
BA68  
32 Kwords  
BA69  
32 Kwords  
BA70  
4 Kwords  
BA71  
111111001  
4 Kwords  
BA72  
111111010  
4 Kwords  
BA73  
111111011  
4 Kwords  
BA74  
111111100  
4 Kwords  
BA75  
111111101  
4 Kwords  
BA76  
111111110  
4 Kwords  
BA77  
111111111  
4 Kwords  
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Table 10. Block Protection Command Sequences  
Cycl  
Command Sequence  
1st Cycle  
555H  
2nd Cycle  
3rd Cycle  
555H  
38H  
4th Cycle  
XX[0-3]H  
PD[0-3]  
5th Cycle  
6th Cycle  
7th Cycle  
Add  
Dat  
Add  
Dat  
2 A A H  
Password Program(1,2)  
4
AAH  
55H  
2AAH  
55H  
555H  
555H  
C8H  
PWA[0-3]  
PWD[0-3]  
Password Verify(2,4,5)  
PasswordUnlock(3,6,7)  
4
7
AAH  
Add  
r
555H  
AAH  
555H  
AAH  
555H  
2AAH  
55H  
555H  
28H  
PWA[0]  
PWD[0]  
(BA)WP  
68H  
PWA[1]  
PWD[1]  
(BA)WP  
48H  
PWA[2]  
PWD[2]  
(BA)WP  
RD(0)  
PWA[3]  
PWD[3]  
Dat  
Add  
r
2AAH  
55H  
555H  
60H  
PPB Program(1,2,8)  
Master locking bit Set  
PPB Status  
6
3
4
Dat  
Add  
r
2AAH  
555H  
Dat  
a
AAH  
55H  
F1H  
Add  
r
555H  
2AAH  
555H  
(BA)WP  
Dat  
Add  
Dat  
Add  
Dat  
Add  
Dat  
Add  
Dat  
Add  
Dat  
Add  
Dat  
Add  
Dat  
Add  
Dat  
Add  
Dat  
Add  
Dat  
RD(0)  
WP  
AAH  
555H  
AAH  
555H  
AAH  
555H  
55H  
90H  
2AAH  
555H  
(BA)  
40H  
(BA)WP  
RD(0)  
All PPB Erase(1,2,9,10)  
PPB Lock Bit Set  
6
3
4
4
4
4
6
5
6
5
55H  
60H  
60H  
2AAH  
555H  
55H  
2AAH  
55H  
78H  
555H  
58H  
BA  
RD(1)  
BA  
PPB Lock Bit Status(11)  
DYB Write(3)  
AAH  
555H  
2AAH  
55H  
555H  
48H  
AAH  
X1H  
BA  
555H  
2AAH  
55H  
555H  
48H  
DYB Erase(3)  
AAH  
X0H  
BA  
555H  
2AAH  
(DA)555H  
58H  
DYB Status(2)  
AAH  
555H  
AAH  
555H  
AAH  
555H  
55H  
RD(0)  
PL  
2AAH  
555H  
PL  
48H  
PL  
PL  
PPMLB Program(1,2,8)  
PPMLB Status(1)  
SPMLB Program(1,2,8)  
55H  
60H  
68H  
PL  
RD(0)  
2AAH  
555H  
55H  
2AAH  
55H  
60H  
555H  
60H  
48H  
BL  
68  
RD(0)  
BL  
BL  
AAH  
48  
RD(0)  
555H  
2AAH  
55H  
555H  
60H  
BL  
48  
BL  
SPMLB Status(1)  
AAH  
RD(0)  
Legend:  
DYB = Dynamic Protection Bit  
OW = Address (A7:A0) is (00011010)  
PD[3:0] = Password Data (1 of 4 portions)  
PPB = Persistent Protection Bit  
PWA = Password Address. A1:A0 selects portion of password.  
PWD = Password Data being verified.  
PL = Password Protection Mode Lock Address (A7:A0) is (00001010)  
RD(0) = Read Data DQ0 for protection indicator bit.  
RD(1) = Read Data DQ1 for PPB Lock status.  
BA = Block Address where security command applies. Address bits Amax:A12 uniquely select any block.  
BL = Persistent Protection Mode Lock Address (A7:A0) is (00010010)  
WP = PPB Address (A7:A0) is (00000010)  
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X = Don’t care  
PPMLB = Password Protection Mode Locking Bit  
SPMLB = Persistent Protection Mode Locking Bit  
Notes:  
See the description of bus operations.  
All values are in hexadecimal.  
Shaded cells in table denote read cycles. All other cycles are write operations.  
During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than  
A11 (except where BA is required) and data bits higher than DQ7 are don’t cares.  
1. The reset command returns device to reading array.  
2. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1.  
If DQ0 = 0 in cycle 6, program command must be issued and verified again.  
3. Data is latched on the rising edge of WE#.  
4. Entire command sequence must be entered for each portion of password.  
5. Command sequence returns FFh if PPMLB is set.  
6. The password is written over four consecutive cycles, at addresses 0-3.  
7. 2us timeout is required between any two portions of password.  
8. 100us timeout is required between cycles 4 and 5.  
9. 1.2 ms timeout is required between cycles 4 and 5.  
10. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase  
command must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPB  
overerasure.  
11. DQ1 = 1 if PPB locked, 0 if unlocked.  
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Table 11. Common Flash Memory Interface Code  
Description  
Addresses  
Data  
(Word Mode)  
10H  
11H  
12H  
0051H  
0052H  
0059H  
Query Unique ASCII string "QRY"  
13H  
14H  
0002H  
0000H  
Primary OEM Command Set  
15H  
16H  
0040H  
0000H  
Address for Primary Extended Table  
17H  
18H  
0000H  
0000H  
Alternate OEM Command Set (00h = none exists)  
Address for Alternate OEM Extended Table (00h = none exists)  
19H  
1AH  
0000H  
0000H  
Vcc Min. (write/erase)  
D7-D4: volt, D3-D0: 100 millivolt  
1BH  
1CH  
0027H  
0036H  
Vcc Max. (write/erase)  
D7-D4: volt, D3-D0: 100 millivolt  
Vpp Min. voltage(00H = no Vpp pin present)  
1DH  
1EH  
1FH  
20H  
21H  
22H  
23H  
24H  
25H  
26H  
27H  
0000H  
0000H  
0003H  
0000H  
0009H  
0000H  
0004H  
0000H  
0004H  
0000H  
0016H  
Vpp Max. voltage(00H = no Vpp pin present)  
Typical timeout per single word write 2N us  
Typical timeout for Min. size buffer write 2N us(00H = not supported)  
Typical timeout per individual block erase 2N ms  
Typical timeout for full chip erase 2N ms(00H = not supported)  
Max. timeout for word write 2N times typical  
Max. timeout for buffer write 2N times typical  
Max. timeout per individual block erase 2N times typical  
Max. timeout for full chip erase 2N times typical(00H = not supported)  
Device Size = 2N byte  
28H  
29H  
0001H  
0000H  
Flash Device Interface description  
2AH  
2BH  
0000H  
0000H  
Max. number of byte in multi-byte write = 2N  
Number of Erase Block Regions within device  
2CH  
0003H  
2DH  
2EH  
2FH  
30H  
0007H  
0000H  
0020H  
0000H  
Erase Block Region 1 Information  
Erase Block Region 2 Information  
Erase Block Region 3 Information  
Erase Block Region 4 Information  
31H  
32H  
33H  
34H  
003DH  
0000H  
0000H  
0001H  
35H  
36H  
37H  
38H  
0007H  
0000H  
0020H  
0000H  
39H  
3AH  
3BH  
3CH  
0000H  
0000H  
0000H  
0000H  
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Table 11. Common Flash Memory Interface Code  
Description  
Addresses  
Data  
(Word Mode)  
40H  
41H  
42H  
0050H  
0052H  
0049H  
Query-unique ASCII string "PRI"  
Major version number, ASCII  
Minor version number, ASCII  
43H  
44H  
0030H  
0030H  
Address Sensitive Unlock(Bits 1-0)  
0 = Required, 1= Not Required  
Silcon Revision Number(Bits 7-2)  
45H  
46H  
0000H  
0002H  
Erase Suspend  
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write  
Block Protect  
00 = Not Supported, 01 = Supported  
47H  
48H  
49H  
0001H  
0001H  
0001H  
Block Temporary Unprotect 00 = Not Supported, 01 = Supported  
Block Protect/Unprotect scheme,  
00 = Not Supported, 01 = Supported  
Simultaneous Operation  
00 = Not Supported, 01 = Supported  
4AH  
4BH  
4CH  
0001H  
0000H  
0002H  
Burst Mode Type 00 = Not Supported, 01 = Supported  
Page Mode Type  
00 = Not Supported, 01 = 4 Word Page 02 = 8 Word Page  
ACC(Acceleration) Supply Minimum  
00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV  
4DH  
4EH  
4FH  
0085H  
0095H  
0004H  
ACC(Acceleration) Supply Maximum  
00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV  
Top/Bottom Boot Block Flag  
02H = Bottom Boot Device, 03H = Top Boot Device, 04H = Top and Bottom Device  
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DEVICE STATUS FLAGS  
The K8P3215UQB has means to indicate its status of operation in the bank where a program or erase operation is in processes.  
Address must include bank address being excuted internal routine operation. The status is indicated by raising the device status flag  
via corresponding DQ pins or the RY/ BY pin. The corresponding DQ pins are DQ7, DQ6, DQ5, DQ3 and DQ2. The statuses are as  
follows :  
Table 12. Hardware Sequence Flags  
Status  
DQ7  
DQ7  
0
DQ6  
Toggle  
Toggle  
DQ5  
DQ3  
DQ2  
1
RY/BY  
Programming  
0
0
0
1
0
0
Block Erase or Chip Erase  
Erase Suspend Read  
Toggle  
Erase Suspended  
Block  
Toggle  
(Note 1)  
1
1
Data  
Toggle  
1
0
Data  
0
0
Data  
0
1
1
0
1
1
Non-Erase Sus-  
pended Block  
Erase Suspend Read  
Data  
DQ7  
DQ7  
Data  
Data  
1
In Progress  
Erase Suspend  
Program  
Non-Erase Sus-  
pended Block  
Program Sus-  
pended Block  
Toggle  
(Note 1)  
Program Suspend Read  
Program Suspend Read  
0
0
Non-Program Sus-  
pended Block  
Data  
Data  
Data  
Data  
No  
Toggle  
Programming  
DQ7  
0
Toggle  
Toggle  
Toggle  
1
1
1
0
1
0
0
0
0
Exceeded  
Time Limits  
Block Erase or Chip Erase  
Erase Suspend Program  
(Note 2)  
No  
Toggle  
DQ7  
Notes :  
1. DQ2 will toggle when the device performs successive read operations from the erase/program suspended block.  
2. If DQ5 is High (exceeded timing limits), successive reads from a problem block will cause DQ2 to toggle.  
DQ7 : Data Polling  
When an attempt to read the device is made while executing the Internal Program, the complement of the data is written to DQ7 as  
an indication of the Routine in progress. When the Routine is completed an attempt to access to the device will produce the true data  
written to DQ7. When a user attempts to read the block being erased, DQ7 will be low. If the device is placed in the Erase/Program  
Suspend Mode, the status can be detected via the DQ7 pin. If the system tries to read an address which belongs to a block that is  
being erase suspended, DQ7 will be high. And, if the system tries to read an address which belongs to a block that is being program  
suspended, the output will be the true data of DQ7 itself. If a non-erase-suspended or non-program-suspended block address is  
read, the device will produce the true data to DQ7. If an attempt is made to program a protected block, DQ7 outputs complements  
the data for approximately 1µs and the device then returns to the Read Mode without changing data in the block. If an attempt is  
made to erase a protected block, DQ7 outputs complement data in approximately 100us and the device then returns to the Read  
Mode without erasing the data in the block.  
DQ6 : Toggle Bit  
Toggle bit is another option to detect whether an Internal Routine is in progress or completed. Once the device is at a busy state,  
DQ6 will toggle. Toggling DQ6 will stop after the device completes its Internal Routine. If the device is in the Erase/Program Suspend  
Mode, an attempt to read an address that belongs to a block that is being erased or programmed will produce a high output of DQ6.  
If an address belongs to a block that is not being erased or programmed, toggling is halted and valid data is produced at DQ6. If an  
attempt is made to program a protected block, DQ6 toggles for approximately 1us and the device then returns to the Read Mode  
without changing the data in the block. If an attempt is made to erase a protected block, DQ6 toggles for approximately 100µs and  
the device then returns to the Read Mode without erasing the data in the block. #OE or #CE should be toggled in each toggle bit sta-  
tus read.  
29  
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
DQ5 : Exceed Timing Limits  
If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure.  
DQ3 : Block Erase Timer  
The status of the multi-block erase operation can be detected via the DQ3 pin. DQ3 will go High if 50µs of the block erase time win-  
dow expires. In this case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write  
commands until the erase operation is completed. DQ3 is Low if the block erase time window is not expired. Within the block erase  
time window, an additional block erase command (30H) can be accepted. To confirm that the block erase command has been  
accepted, the software may check the status of DQ3 following each block erase command.  
DQ2 : Toggle Bit 2  
The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase/Program Suspend is in progress. When  
the device executes the Internal Erase Routine, DQ2 toggles only if an erasing bank is read. Although the Internal Erase Routine is  
in the Exceeded Time Limits, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the  
Erase/Program Suspend mode, DQ2 toggles only if an address in the erasing or programming block is read. If a non-erasing or non-  
programmed block address is read during the Erase/Program Suspend mode, then DQ2 will produce valid data. DQ2 will go High if  
the user tries to program a non-erase suspend block while the device is in the Erase Suspend mode. #OE or #CE should be toggled  
in each toggle bit status read.  
RY/BY : Ready/Busy  
The K8P3215UQB has a Ready / Busy output that indicates either the completion of an operation or the status of Internal Algorithms.  
If the output is Low, the device is busy with either a program or an erase operation. If the output is High, the device is ready to accept  
any read/write or erase operation. When the RY/ BY pin is low, the device will not accept any additional program or erase commands  
with the exception of the Erase Suspend command. If the K8P3215UQB is placed in an Erase Suspend mode, the RY/ BY output will  
be High. For programming, the RY/ BY is valid (RY/ BY = 0) after the rising edge of the fourth WE pulse in the four write pulse  
sequence. For Chip Erase, RY/ BY is also valid after the rising edge of WE pulse in the six write pulse sequence. For Block Erase,  
RY/ BY is also valid after the rising edge of the sixth WE pulse.  
The pin is an open drain output, allowing two or more Ready/ Busy outputs to be OR-tied. An appropriate pull-up resistor is required  
for proper operation.  
Rp  
VCC  
Vcc (Max.) - VOL (Max.)  
3.2 V  
Rp =  
=
IOL + Σ IL  
2.1mA + Σ IL  
Ready / Busy  
open drain output  
where Σ IL is the sum of the input currents of all devices tied to the  
Ready / Busy pin.  
GND  
Device  
30  
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
Start  
Read(DQ0~DQ7)  
Valid Address  
Start  
Read(DQ0~DQ7)  
Valid Address  
Read(DQ0~DQ7)  
Valid Address  
DQ7 = Data ?  
No  
DQ6 = Toggle ?  
Yes  
Yes  
No  
No  
No  
DQ5 = 1 ?  
Yes  
DQ5 = 1 ?  
Yes  
Read(DQ0~DQ7)  
Valid Address  
Read twice(DQ0~DQ7)  
Valid Address  
Yes  
No  
DQ7 = Data ?  
DQ6 = Toggle ?  
No  
Yes  
Fail  
Fail  
Pass  
Pass  
Figure 10. Toggle Bit Algorithms  
Figure 9. Data Polling Algorithms  
31  
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Symbol  
Rating  
Unit  
Vcc  
Vcc  
-0.5 to +4.0  
-0.5 to +9.5  
-0.5 to +9.5  
-0.5 to +2.5  
-10 to +125  
-25 to +125  
-65 to +150  
5
A9, RESET  
Voltage on any pin relative to VSS  
WP/ACC  
V
VIN  
All Other Pins  
Commercial  
Temperature Under Bias  
Tbias  
°C  
Extended  
Storage Temperature  
Tstg  
IOS  
°C  
mA  
°C  
Short Circuit Output Current  
TA (Commercial  
TA (Extended Temp.)  
0 to +70  
Operating Temperature  
-25 to + 85  
°C  
Notes :  
1. Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC voltage on  
input / output pins is Vcc+0.5V which, during transitions, may overshoot to Vcc+2.0V for periods <20ns.  
2. Minimum DC voltage is -0.5V on A9, RESET and WP/ACC pins. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC  
voltage on A9, RESET, WP/ACC pins is 9.5V which, during transitions, may overshoot to 14.0V for periods <20ns.  
3. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions  
detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
RECOMMENDED OPERATING CONDITIONS ( Voltage reference to GND )  
Parameter  
Symbol  
Min  
2.7  
0
Typ.  
3.0  
0
Max  
3.6  
0
Unit  
V
Supply Voltage  
VCC  
Supply Voltage  
VSS  
V
DC CHARACTERISTICS  
Parameter  
Sym-  
bol  
Test Conditions  
Min  
Typ  
Max  
Unit  
Input Leakage Current  
ILI  
VIN=VSS to VCC, VCC=VCCmax  
VCC=VCCmax, A9, RESET=9.5V  
VCC=VCCmax, WP/ACC=9.5V  
1.0  
-
-
-
+ 1.0  
35  
µA  
µA  
µA  
A9,RESET Input Leakage Current  
WP/ACC Input Leakage Current  
ILIT  
ILIW  
-
-
35  
VOUT=VSS to VCC,VCC=VCC-  
max,OE=VIH  
Output Leakage Current  
Active Read Current (1)  
ILO  
1.0  
-
+ 1.0  
µA  
10MHz  
5MHz  
-
-
-
-
-
45  
20  
15  
35  
35  
55  
30  
30  
55  
55  
ICC1  
OE=VIH, VCC=VCCmax  
mA  
Active Write Current (2)  
ICC2  
ICC3  
ICC4  
CE=VIL, OE=VIH, WE=VIL  
CE=VIL, OE=VIH (@10Mhz)  
CE=VIL, OE=VIH (@10Mhz)  
mA  
mA  
mA  
Read While Program Current (3)  
Read While Erase Current (3)  
Program While Erase Suspend  
Current  
ICC5  
ICC6  
CE=VIL, OE=VIH  
-
-
15  
10  
35  
15  
mA  
mA  
Page Read Current  
OE=VIH, 8 word Page Read  
ACC Accelerated Program  
Current  
IACC  
CE=VIL, OE=VIH  
-
15  
30  
mA  
Standby Current  
ISB1  
ISB2  
ISB3  
-
-
-
15  
15  
15  
30  
30  
30  
µA  
µA  
µA  
CE, RESET, WP/ACC= VIO± 0.3  
RESET= Vss± 0.3  
Standby Current During Reset  
Automatic Sleep Mode  
VIH=VIO ± 0.3V, VIL=VSS ±0.2V  
0.4  
(Vccx0.2)  
Input Low Level  
Input High Level  
VIL  
Vio=1.65~1.95V(2.7~3.6V)  
Vio=1.65~1.95V(2.7~3.6V)  
-0.4(-0.5)  
-
-
V
V
Vio -0.4  
(Vccx0.8)  
Vio+0.4  
(Vcc+0.3)  
VIH  
Voltage for WP/ACC Block Tempo-  
rarily Unprotect and Program Accelera-  
tion (4)  
VHH  
8.5  
-
9.5  
V
Vcc = 3.0V ± 0.15V  
32  
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
Parameter  
Symbol  
Test Conditions  
Vcc = 3.0V ± 10%  
Min  
Typ  
Max  
Unit  
Voltage for Autoselect and  
Block Protect (4)  
VID  
8.5  
-
9.5  
V
IOL =100uA,Vcc=VCCmin,  
Vio=1.65~1.95V  
-
0.1  
0.4  
-
V
V
V
Output Low Level  
Output High Level  
VOL  
IOL =2.0mA,Vcc=VCCmin,  
Vio=2.7~3.6V  
-
IOH = -100uA, Vcc=VCCmin,  
Vio=1.65~1.95V  
Vio-0.1  
-
VOH  
IOH = -2.0mA, Vcc=VCCmin,  
Vio=2.7~3.6V  
2.4  
-
-
-
V
V
Low VCC Lock-out Voltage (5)  
VLKO  
2.3  
2.5  
Notes :  
1. The ICC current listed includes both the DC operating current and the frequency dependent component(at 10 MHz).  
2. ICC active during Internal Routine(program or erase) is in progress.  
3. ICC active during Read while Write is in progress.  
4. The high voltage ( VHH or VID ) must be used in the range of Vcc = 3.0V ± 0.15V  
5. Not 100% tested.  
6. Typical value are measured at Vcc = 3.0V,TA=25°C , Not 100% tested.  
CAPACITANCE(TA = 25 °C, VCC = 3.0V, f = 1.0MHz)  
Item  
Symbol  
Test Condition  
Min  
Max  
Unit  
pF  
Input Capacitance  
CIN  
VIN=0V  
-
-
-
10  
10  
10  
Output Capacitance  
Control Pin Capacitance  
COUT  
CIN2  
VOUT=0V  
VIN=0V  
pF  
pF  
Note : Capacitance is periodically sampled and not 100% tested.  
AC TEST CONDITION  
Parameter  
Value  
0V to Vcc  
5ns  
Input Pulse Levels  
Input Rise and Fall Times(Vio=1.8,3.0V)  
Input and Output Timing Levels  
Output Load  
Vcc/2  
CL = 30pF  
Vcc  
Device  
Input & Output  
Vcc/2  
Vcc/2  
Test Point  
* CL= 30pF including Scope  
and Jig Capacitance  
0V  
CL  
Input Pulse and Test Point  
Output Load  
AC CHARACTERISTICS  
Read Operations  
VCC=2.7V~3.6V  
4B  
Parameter  
Symbol  
4A  
4C  
4D  
Unit  
Min  
Max  
-
Min  
Max  
-
Min  
Max  
-
Min  
Max  
-
Read Cycle Time (1)  
tRC  
tAA  
55  
-
60  
-
65  
-
70  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
55  
55  
20  
-
60  
60  
25  
-
65  
65  
30  
-
70  
70  
30  
-
Chip Enable Access Time  
Output Enable Time  
tCE  
tOE  
tPRC  
tPA  
-
-
-
-
-
-
-
-
Page Read Cycle Time (1)  
Page Address Access Time  
CE & OE Disable Time (1)  
20  
-
25  
-
25  
-
30  
-
20  
16  
25  
16  
25  
16  
30  
16  
tDF  
-
-
-
-
Output Hold Time from  
Address, CE or OE (1)  
tOH  
5
-
5
-
5
-
5
-
ns  
Note : 1. Not 100% tested.  
33  
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
AC CHARACTERISTICS  
Write(Erase/Program)Operations  
Alternate WE Controlled Write  
VCC=2.7V ~ 3.6V  
4B  
Parameter  
Symbol  
4A  
4C  
4D  
Unit  
Min  
55  
0
Max  
Min  
60  
0
Max  
Min  
65  
0
Max  
Min  
70  
0
Max  
Write Cycle Time (1)  
Address Setup Time  
tWC  
tAS  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tASO  
tAH  
15  
30  
0
15  
35  
0
15  
35  
0
15  
35  
0
Address Hold Time  
tAHT  
tDS  
Data Setup Time  
25  
0
30  
0
30  
0
30  
0
Data Hold Time  
tDH  
Output Enable Setup Time (1)  
tOES  
tOEH1  
0
0
0
0
Output  
Enable  
Hold  
Read (1)  
0
0
0
0
Toggle and Data  
Polling (1)  
tOEH2  
10  
-
10  
-
10  
-
10  
-
ns  
CE Setup Time  
tCS  
tCH  
0
0
-
-
-
-
0
0
-
-
-
-
0
0
-
-
-
-
0
0
-
-
-
-
ns  
ns  
ns  
ns  
µs  
CE Hold Time  
Write Pulse Width  
Write Pulse Width High  
Programming Operation  
tWP  
35  
20  
35  
25  
35  
25  
35  
25  
tWPH  
tPGM  
6(typ.)  
6(typ.)  
6(typ)  
6(typ)  
6(typ.)  
6(typ.)  
6(typ.)  
6(typ.)  
Accelerated Programming  
Operation  
tACCPGM  
µs  
µs  
Accelerated Quad word  
Programming Operation  
tACCPGM_Q  
UAD  
1.5(typ.)  
0.7(typ.)  
1.5(typ.)  
0.7(typ)  
1.5(typ.)  
0.7(typ.)  
1.5(typ.)  
0.7(typ.)  
Block Erase Operation (2)  
VCC Set Up Time  
tBERS  
tVCS  
sec  
50  
0
-
-
50  
-
-
50  
-
-
50  
-
-
µs  
Write Recovery Time from RY/  
BY  
tRB  
0
0
0
ns  
RESET High Time Before Read  
RESET to Power Down Time  
tRH  
50  
20  
-
-
50  
20  
-
-
50  
20  
-
-
50  
20  
-
-
ns  
tRPD  
µs  
Program/Erase Valid to RY/BY  
Delay  
tBUSY  
35  
90  
35  
90  
35  
90  
35  
90  
ns  
VID Rising and Falling Time  
RESET Pulse Width  
tVID  
tRP  
500  
500  
-
-
-
500  
500  
-
-
-
500  
500  
-
-
-
500  
500  
-
-
-
ns  
ns  
µs  
RESET Low to RY/BY High  
tRRB  
20  
20  
20  
20  
RESET Setup Time for Tempo-  
rary Unprotect  
tRSP  
4
-
4
-
4
-
4
-
µs  
RESET Low Setup Time  
tRSTS  
tRSTW  
500  
200  
-
-
500  
200  
-
-
500  
200  
-
-
500  
200  
-
-
ns  
ns  
RESET High to Address Valid  
Read Recovery Time Before  
Write  
tGHWL  
tCEPH  
tOEPH  
0
-
-
-
0
-
-
-
0
-
-
-
0
-
-
-
ns  
ns  
ns  
CE High during toggling bit poll-  
ing  
20  
10  
20  
10  
20  
10  
20  
10  
OE High during toggling bit poll-  
ing  
Notes : 1. Not 100% tested.  
2. The duration of the Program or Erase operation varies and is calculated in the internal algorithms.  
34  
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
AC CHARACTERISTICS  
Write(Erase/Program)Operations  
Alternate CE Controlled Writes  
VCC=2.7V ~ 3.6V  
Parameter  
Symbol  
4A  
4B  
4C  
4D  
Unit  
Min  
55  
0
Max  
Min  
60  
0
Max  
Min  
65  
0
Max  
Min  
70  
0
Max  
Write Cycle Time (1)  
Address Setup Time  
Address Hold Time  
Data Setup Time  
Data Hold Time  
tWC  
tAS  
tAH  
tDS  
tDH  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
30  
25  
0
35  
30  
0
35  
30  
0
35  
30  
0
Output Enable Setup Time  
(1)  
tOES  
0
0
-
-
0
0
-
-
0
0
-
-
0
0
-
-
ns  
ns  
Out-  
put  
Read (1)  
tOEH1  
Toggle and Data  
Polling (1)  
Enable  
Hold  
tOEH2  
10  
-
10  
-
10  
-
10  
-
ns  
WE Setup Time  
tWS  
tWH  
0
0
-
-
-
-
0
0
-
-
-
-
0
0
-
-
-
-
0
0
-
-
-
-
ns  
ns  
ns  
ns  
µs  
WE Hold Time  
CE Pulse Width  
tCP  
35  
20  
40  
25  
40  
25  
40  
25  
CE Pulse Width High  
Programming Operation  
tCPH  
tPGM  
6(typ.)  
6(typ.)  
6(typ)  
6(typ)  
6(typ.)  
6typ.)  
6(typ.)  
6(typ.)  
Accelerated Programming  
Operation  
tACCPGM  
µs  
Accelerated Quad word  
Programming Operation  
1.5(typ.)  
0.7(typ.)  
1.5(typ.)  
0.7(typ)  
1.5(typ.)  
0.7typ.)  
1.5(typ.)  
0.7(typ.)  
µs  
tACCPGM_QUA  
D
Block Erase Operation (2)  
tBERS  
sec  
Notes : 1. Not 100% tested.  
2.This does not include the preprogramming time.  
ERASE AND PROGRAM PERFORMANCE  
Limits  
Typ  
0.7  
39  
Parameter  
Unit  
Comments  
Min  
Max  
2
Block Erase Time  
-
sec  
sec  
µs  
Excludes 00H programming  
prior to erasure  
Chip Erase Time  
-
62.4  
100  
100  
-
Word Programming Time  
-
6
Accelerated Word Program Time  
Accelerated Quad Word Program Time  
Chip Programming Time (Normal)  
Chip Programming Time (Acc. Quad)  
Erase/Program Endurance  
-
6
µs  
-
1.5  
12.6  
3
µs  
Excludes system-level overhead  
-
25.2  
-
sec  
sec  
-
100,000  
-
-
cycles Minimum 100,000 cycles guaranteed  
Notes : 1. 25 °C, VCC = 3.0V 100,000 cycles, typical pattern.  
2. System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each word.  
In the preprogramming step of the Internal Erase Routine, all words are programmed to 00H before erasure.  
35  
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
SWITCHING WAVEFORMS  
Conventional Read Operations  
tRC  
Address Stable  
Address  
tAA  
CE  
tOE  
tDF  
OE  
tOEH  
WE  
tCE  
tOH  
HIGH-Z  
HIGH-Z  
Outputs  
Output Valid  
HIGH  
RY/BY  
Figure 11. Conventional Read Operation Timings  
4A  
4B  
4C  
4D  
Parameter  
Read Cycle Time  
Symbol  
Unit  
Min  
Max  
-
Min  
Max  
-
Min  
Max  
-
Min  
Max  
-
tRC  
tAA  
tCE  
tOE  
tDF  
55  
-
60  
-
65  
-
70  
-
ns  
ns  
ns  
ns  
ns  
Address Access Time  
Chip Enable Access Time  
Output Enable Time  
55  
55  
20  
16  
60  
60  
25  
16  
65  
65  
30  
16  
70  
70  
30  
16  
-
-
-
-
-
-
-
-
CE & OE Disable Time (1)  
-
-
-
-
Output Hold Time from  
Address, CE or OE  
tOH  
5
0
-
5
0
-
5
0
-
5
0
-
ns  
ns  
OE Hold Time  
tOEH  
10  
10  
10  
10  
Note : 1. Not 100% tested.  
36  
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
SWITCHING WAVEFORMS  
Page Read Operations  
Same page Addresses  
A3 to A20  
A0 to A2  
CE  
Aa  
Ab  
Ac  
Ad  
tRC  
tPRC  
tAA  
tCE  
tOEH  
tOE  
OE  
tDF  
tPA  
tPA  
WE  
tOH  
tOH  
tOH  
Dd  
High-Z  
Da  
Db  
Dc  
Output  
Figure 12. Page Read Operation Timings  
4A  
4B  
4C  
4D  
Parameter  
Read Cycle Time  
Symbol  
Unit  
Min  
Max  
-
Min  
Max  
-
Min  
Max  
-
Min  
Max  
-
tRC  
tPRC  
tAA  
55  
20  
-
60  
25  
-
65  
25  
-
70  
30  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Page Read Cycle Time  
Address Access Time  
-
-
-
-
55  
20  
55  
20  
16  
60  
25  
60  
25  
16  
65  
25  
65  
30  
16  
70  
30  
70  
30  
16  
Page Address Access Time  
Chip Enable Access Time  
Output Enable Time  
tPA  
-
-
-
-
tCE  
tOE  
tDF  
-
-
-
-
-
-
-
-
CE & OE Disable Time (1)  
-
-
-
-
Output Hold Time from  
Address, CE or OE  
tOH  
5
0
-
-
5
0
-
-
5
0
-
-
5
0
-
-
ns  
ns  
OE Hold Time  
tOEH  
Note : 1. Not 100% tested.  
37  
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
SWITCHING WAVEFORMS  
Hardware Reset/Read Operations  
tRC  
Address Stable  
Address  
tAA  
CE  
tRH  
tRP  
tRH  
tCE  
RESET  
tOH  
High-Z  
Output Valid  
Outputs  
Figure 13. Hardware Reset/Read Operation Timings  
4A  
4B  
4C  
4D  
Parameter  
Read Cycle Time  
Symbol  
Unit  
Min  
Max  
-
Min  
Max  
-
Min  
Max  
-
Min  
Max  
-
tRC  
tAA  
tCE  
55  
-
60  
-
65  
-
70  
-
ns  
ns  
ns  
Address Access Time  
55  
55  
60  
60  
65  
65  
70  
70  
Chip Enable Access Time  
-
-
-
-
Output Hold Time from  
Address, CE or OE  
tOH  
tRP  
tRH  
5
-
-
-
5
-
-
-
5
-
-
-
5
-
-
-
ns  
ns  
ns  
RESET Pulse Width  
500  
50  
500  
50  
500  
50  
500  
50  
RESET High Time Before  
Read  
38  
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
SWITCHING WAVEFORMS  
Alternate WE Controlled Program Operations  
tAS  
Data Polling  
PA  
555H  
PA  
Address  
CE  
tRC  
tAH  
tOES  
OE  
tWC  
tCH  
tPGM  
tWP  
WE  
tWPH  
tDH  
tOE  
tDF  
tCS  
A0H  
PD  
Status  
DOUT  
DATA  
tCE  
tBUSY  
tRB  
tDS  
tOH  
RY/BY  
Notes : 1. DQ7 is the output of the complement of the data written to the device.  
2. DOUT is the output of the data written to the device.  
3. PA : Program Address, PD : Program Data  
4. The illustration shows the last two cycles of the program command sequence.  
Figure 14. Alternate WE Controlled Program Operation Timings  
4A  
4B  
4C  
4D  
Parameter  
Symbol  
Unit  
Min  
55  
0
Max  
Min  
60  
0
Max  
Min  
65  
0
Max  
Min  
70  
0
Max  
Write Cycle Time  
Address Setup Time  
Address Hold Time  
Data Setup Time  
Data Hold Time  
CE Setup Time  
tWC  
tAS  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
us  
tAH  
30  
25  
0
35  
30  
0
35  
30  
0
35  
30  
0
tDS  
tDH  
tCS  
0
0
0
0
CE Hold Time  
tCH  
0
0
0
0
OE Setup Time  
Write Pulse Width  
tOES  
tWP  
tWPH  
tPGM  
0
0
0
0
35  
20  
35  
25  
35  
25  
35  
25  
Write Pulse Width High  
Programming Operation  
6(typ.)  
6(typ.)  
6(typ)  
6(typ)  
6(typ.)  
6(typ.)  
6(typ.)  
6(typ.)  
Accelerated Programming  
Operation  
tACCPGM  
µs  
Read Cycle Time  
tRC  
tCE  
tOE  
tDF  
55  
-
-
60  
-
-
65  
-
-
70  
-
-
ns  
ns  
ns  
ns  
Chip Enable Access Time  
Output Enable Time  
CE & OE Disable Time  
55  
20  
16  
60  
25  
16  
65  
30  
16  
70  
30  
16  
-
-
-
-
-
-
-
-
Output Hold Time from  
Address, CE or OE  
tOH  
5
-
5
-
5
-
5
-
ns  
Program/Erase Valid to RY/  
BY Delay  
tBUSY  
tRB  
35  
0
90  
-
35  
0
90  
-
35  
0
90  
-
35  
0
90  
-
ns  
ns  
Recovery Time from RY/BY  
39  
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
SWITCHING WAVEFORMS  
Alternate CE Controlled Program Operations  
tAS  
Data Polling  
555H  
PA  
PA  
Address  
WE  
tAH  
tOES  
OE  
CE  
tWC  
tPGM  
tCP  
tCPH  
tWS  
tDH  
PD  
DOUT  
Status  
A0H  
DATA  
tDS  
tBUSY  
tRB  
RY/BY  
Figure 15. Alternate CE Controlled Program Operation Timings  
Notes :  
1. DQ7 is the output of the complement of the data written to the device.  
2. DOUT is the output of the data written to the device.  
3. PA : Program Address, PD : Program Data  
4. The illustration shows the last two cycles of the program command sequence.  
4A  
4B  
4C  
4D  
Parameter  
Symbol  
Unit  
Min  
55  
0
Max  
Min  
60  
0
Max  
Min  
65  
0
Max  
Min  
70  
0
Max  
Write Cycle Time  
Address Setup Time  
Address Hold Time  
Data Setup Time  
Data Hold Time  
tWC  
tAS  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
tAH  
30  
25  
0
35  
30  
0
35  
30  
0
35  
30  
0
tDS  
tDH  
OE Setup Time  
tOES  
tWS  
tWH  
tCP  
0
0
0
0
WE Setup Time  
0
0
0
0
WE Hold Time  
0
0
0
0
CE Pulse Width  
35  
20  
40  
25  
40  
25  
40  
25  
CE Pulse Width High  
Programming Operation  
tCPH  
tPGM  
6(typ.)  
6(typ.)  
6(typ)  
6(typ)  
6(typ.)  
6(typ.)  
6(typ.)  
6(typ.)  
Accelerated Program-  
ming Operation  
tACCPGM  
tBUSY  
tRB  
µs  
ns  
ns  
Program/Erase Valid to  
RY/BY Delay  
35  
0
90  
-
35  
0
90  
-
35  
0
90  
-
35  
0
90  
-
Recovery Time from RY/  
BY  
40  
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
SWITCHING WAVEFORMS  
Chip/Block Erase Operations  
tAS  
555H for Chip Erase  
555H  
2AAH  
555H  
555H  
2AAH  
BA  
Address  
CE  
tAH  
tRC  
tOES  
OE  
tWC  
tWP  
WE  
tWPH  
tDH  
tCS  
10H for Chip Erase  
30H  
AAH  
55H  
80H  
AAH  
55H  
DATA  
RY/BY  
tDS  
Vcc  
tVCS  
Figure 16. Chip/Block Erase Operation Timings  
Note : BA : Block Address  
4A  
4B  
4C  
4D  
Parameter  
Symbol  
Unit  
Min  
55  
0
Max  
Min  
60  
0
Max  
Min  
65  
0
Max  
Min  
Max  
Write Cycle Time  
Address Setup Time  
Address Hold Time  
Data Setup Time  
Data Hold Time  
tWC  
tAS  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
70  
0
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
tAH  
30  
25  
0
35  
30  
0
35  
30  
0
35  
30  
0
tDS  
tDH  
OE Setup Time  
tOES  
tCS  
0
0
0
0
CE Setup Time  
0
0
0
0
Write Pulse Width  
tWP  
tWPH  
tRC  
35  
20  
55  
50  
35  
25  
60  
50  
35  
25  
65  
50  
35  
25  
70  
50  
Write Pulse Width High  
Read Cycle Time  
tVCS  
VCC Set Up Time  
41  
Revision 1.1  
April 2007  
K8P3215UQB  
FLASH MEMORY  
SWITCHING WAVEFORMS  
Read While Write Operations  
Read  
tRC  
Command  
Read  
tRC  
Command  
tWC  
Read  
Read  
tRC  
tWC  
tRC  
DA2  
(555H)  
DA2  
(PA)  
DA2  
(PA)  
Address  
DA1  
DA1  
DA1  
tAS  
tAS  
tAH  
tAA  
tCE  
tAHT  
CE  
OE  
tOE  
t
CEPH  
tDF  
tOES  
tOEH  
tWP  
WE  
DQ  
t
DF  
t
DH  
tDS  
Valid  
Output  
Valid  
Input  
Valid  
Output  
Valid  
Input