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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

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  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • K9F1208U0C-PCB0 现货库存
  • 数量50600 
  • 厂家SAMSUNG/三星 
  • 封装TSOP48 
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  • 深圳市金嘉锐电子有限公司

     该会员已使用本站14年以上
  • K9F1208U0C-PCB0 现货库存
  • 数量32560 
  • 厂家SAMSUNG 
  • 封装TSOP48 
  • 批号2024+ 
  • 【原装优势★★★绝对有货】
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  • 北京元坤伟业科技有限公司

     该会员已使用本站17年以上
  • K9F1208U0C-PcB0 现货库存
  • 数量5000 
  • 厂家SAMSUNG 
  • 封装TSOP 
  • 批号2024+ 
  • 百分百原装正品,现货库存
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  • 北京元坤伟业科技有限公司

     该会员已使用本站17年以上
  • K9F1208U0C-PCB0 现货库存
  • 数量5000 
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  • 批号2024+ 
  • 百分百原装正品,现货库存
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • K9F1208U0C-PCB0 现货库存
  • 数量5680 
  • 厂家Samsung 
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  • 批号24+ 
  • 假一罚万!专业内存、储存、闪存
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • K9F1208U0C-PCB0 现货库存
  • 数量5680 
  • 厂家Samsung 
  • 封装TSSOP 
  • 批号24+ 
  • 假一罚万!专业内存、储存、闪存
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  • 深圳市创德丰电子有限公司

     该会员已使用本站15年以上
  • K9F1208U0C-PCB0 现货库存
  • 数量783 
  • 厂家SAMSUNG CORPORATION 
  • 封装TSOPI48PIN 
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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • K9F1208U0C-PCB0 现货库存
  • 数量69850 
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  • 深圳市楷兴电子科技有限公司

     该会员已使用本站7年以上
  • K9F1208U0C-PCB0 现货库存
  • 数量89700 
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  • 深圳市卓越微芯电子有限公司

     该会员已使用本站12年以上
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  • 数量8500 
  • 厂家原厂 
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  • 北京力通科信电子有限公司

     该会员已使用本站10年以上
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  • 厂家SAMSUNG 
  • 封装0934+ 
  • 批号TSOP48 
  • 16元原装现货13661385246
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  • 深圳市赛科世纪电子有限公司

     该会员已使用本站11年以上
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  • 数量63820 
  • 厂家SAMSUNG 
  • 封装TSSOP48 
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  • 齐创科技(上海北京青岛)有限公司

     该会员已使用本站14年以上
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  • 数量9600 
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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
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  • 数量6980 
  • 厂家SAMSUNG 
  • 封装TSOP48 
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  • 深圳市拓森弘电子有限公司

     该会员已使用本站1年以上
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  • 数量5300 
  • 厂家SAMSUNG(三星) 
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  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
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  • 数量65000 
  • 厂家SAMSUNG 
  • 封装TSOP 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
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  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
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  • 数量36000 
  • 厂家SAMSUNG 
  • 封装TSOP-48 
  • 批号23+ 
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  • 深圳市恒达亿科技有限公司

     该会员已使用本站16年以上
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  • 数量6500 
  • 厂家SAMSUNG 
  • 封装TSOP48 
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  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
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  • 数量6000 
  • 厂家SAMSUNG 
  • 封装TSOP48 
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  • 深圳市美思瑞电子科技有限公司

     该会员已使用本站12年以上
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  • 数量11367 
  • 厂家SAMSUNG 
  • 封装TSOP-48 
  • 批号22+ 
  • 市场最低价!原厂原装假一罚十
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
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  • 数量188 
  • 厂家SAMSUNG/三星 
  • 封装NA/ 
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站15年以上
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  • 数量9600 
  • 厂家SAMSUNG/三星 
  • 封装TSOP48 
  • 批号24+ 
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  • 集好芯城

     该会员已使用本站13年以上
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  • 数量16812 
  • 厂家SAMSUNG/三星 
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
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  • 数量16380 
  • 厂家SAMSUMG 
  • 封装TSOP48 
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
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  • 数量15372 
  • 厂家SAMSUNG 
  • 封装TSSOP-.. 
  • 批号23+ 
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  • 首天国际(深圳)科技有限公司

     该会员已使用本站16年以上
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  • 数量296000 
  • 厂家SAMSUNG 
  • 封装TSOP48 
  • 批号2024+ 
  • 百分百原装正品,现货库存
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  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • K9F1208U0C-PCB0
  • 数量22000 
  • 厂家SAMSUNG/三星 
  • 封装TSOP 
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  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
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  • 数量12500 
  • 厂家SAMSUNG/三星 
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  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
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  • 数量1000 
  • 厂家SAMSUNG 
  • 封装TSOP48 
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  • 深圳市正纳电子有限公司

     该会员已使用本站15年以上
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  • 数量26700 
  • 厂家SAMSUNG(三星) 
  • 封装▊原厂封装▊ 
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
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  • 数量57237 
  • 厂家SAMSUNG 
  • 封装TSOP48 
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  • 深圳市昌和盛利电子有限公司

     该会员已使用本站11年以上
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  • 数量18682 
  • 厂家SAMSUNG【原装正品价格最低】 
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  • 深圳市集创讯科技有限公司

     该会员已使用本站5年以上
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  • 数量25000 
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  • 北京首天国际有限公司

     该会员已使用本站16年以上
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  • 数量35600 
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     该会员已使用本站15年以上
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     该会员已使用本站12年以上
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     该会员已使用本站12年以上
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     该会员已使用本站11年以上
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产品型号K9F1208U0C-PCB0的概述

K9F1208U0C-PCB0的概述 K9F1208U0C-PCB0是一款由三星电子公司开发的NAND闪存芯片,广泛应用于各种电子设备的数据存储。这种芯片具有高度的集成度和优良的性能,尤其适用于手机、数码相机、MP3播放器等消费电子产品。该芯片以其卓越的存储密度和读取速度,逐渐取代了一些传统的存储技术,成为现代消费电子产品的核心组件之一。 K9F1208U0C-PCB0的设计旨在满足行业对高速、低功耗、高存储密度的需求,其读写速度和耐用性使其在数据存储领域表现出色。作为一种非易失性存储器,K9F1208U0C-PCB0能够在断电后仍然保持存储的数据,这一特性使得它在需要持续保存数据的应用中显得尤为重要。 K9F1208U0C-PCB0的详细参数 K9F1208U0C-PCB0具有以下主要参数: - 存储容量:1.2 Gbit (Gigabit) - 封装类型:TSOP-48 - 工作电...

产品型号K9F1208U0C-PCB0的Datasheet PDF文件预览

K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
K9F1208X0C  
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,  
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.  
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,  
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,  
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL  
INFORMATION IN THIS DOCUMENT IS PROVIDED  
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.  
1. For updates or additional information about Samsung products, contact your nearest Samsung office.  
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar  
applications where Product failure could result in loss of life or personal or physical harm, or any military or  
defense application, or any governmental procurement to which special terms or provisions may apply.  
* Samsung Electronics reserves the right to change products or specification without notice.  
1
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
Document Title  
64M x 8 Bits NAND Flash Memory  
Revision History  
Revision No. History  
Draft Date  
Remark  
0.0  
0.1  
0.2  
0.3  
Initial issue.  
Nov. 10th 2005  
July 13th 2006  
Aug. 1st 2006  
Oct. 12th 2006  
Advance  
2.7V part is added  
Advance  
Advance  
Advance  
Address of Read 2 is changed (A4~A7 : Don’t care -> Fixed "Low" )  
1. Add tRPS/tRCS/tREAS parameter for status read  
2. Add nWP timing guide  
0.4  
Nov. 14th 2006  
Advance  
1. Change from tRPS/tRCS/tREAS to tRPB/tRCB/tREAB parameter for  
1.8V device busy state  
0.5  
1.0  
1.1  
Nov. 15th 2006  
Dec. 28th 2006  
June 18th 2007  
Preliminary  
Final  
1. Sequential Row Read is added  
1. tCRY is changed (50ns+tR(R/B) --> 5us)  
1. Mode selection is modified ("CE don’t care" case)  
Final  
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.  
http://www.samsung.com/Products/Semiconductor/  
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right  
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have  
any questions, please contact the SAMSUNG branch office near you.  
2
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
64M x 8 Bits NAND Flash Memory  
PRODUCT LIST  
Part Number  
K9F1208R0C-J  
K9F1208B0C-P  
K9F1208U0C-P  
K9F1208U0C-J  
Vcc Range  
1.65V ~ 1.95V  
2.5V ~ 2.9V  
Organization  
PKG Type  
FBGA  
TSOP1  
TSOP1  
FBGA  
x8  
2.7V ~ 3.6V  
FEATURES  
Voltage Supply  
Reliable CMOS Floating-Gate Technology  
- 1.8V Device(K9F1208R0C) : 1.65V ~ 1.95V  
- 2.7V Device(K9F1208B0C) : 2.5V ~ 2.9V  
- 3.3V Device(K9F1208U0C) : 2.7V ~ 3.6V  
Organization  
- Endurance  
: 100K Program/Erase Cycles  
(with 1bit/512Byte ECC)  
- Data Retention : 10 Years  
Command Register Operation  
- Memory Cell Array : (64M + 2M) x 8bits  
- Data Register : (512 + 16) x 8bits  
Automatic Program and Erase  
- Page Program : (512 + 16) x 8bits  
- Block Erase : (16K + 512)Bytes  
Page Read Operation  
Unique ID for Copyright Protection  
Package  
- K9F1208U0C-PCB0/PIB0 : Pb-Free Package  
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)  
- K9F1208X0C-JCB0/JIB0: Pb-Free Package  
63-Ball FBGA(8.5 x 13 x 1.2mmt)  
- K9F1208B0C-PCB0/PIB0 : Pb-Free Package  
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)  
- Page Size : (512 + 16)Bytes  
- Random Access  
: 15µs(Max.)  
- Serial Page Access : 42ns(Min.)  
Fast Write Cycle Time  
- Program time : 200µs(Typ.)  
- Block Erase Time : 2ms(Typ.)  
Command/Address/Data Multiplexed I/O Port  
Hardware Data Protection  
- Program/Erase Lockout During Power Transitions  
GENERAL DESCRIPTION  
Offered in 64Mx8bits, the K9F1208X0C is 512Mbit with spare 16Mbit capacity. The device is offered in 1.8V, 2.7V and 3.3V Vcc. Its  
NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be performed in  
typical 200µs on the 528-bytes and an erase operation can be performed in typical 2ms on a 16K-bytes block. Data in the page can  
be read out at 42ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input.  
The on-chip write control automates all program and erase functions including pulse repetition, where required, and internal verifica-  
tion and margining of data. Even the write-intensive systems can take advantage of the K9F1208X0Cs extended reliability of 100K  
program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.  
The K9F1208X0C is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable  
applications requiring non-volatility.  
3
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
PIN CONFIGURATION (TSOP1)  
K9F1208X0C-PCB0/PIB0  
N.C  
N.C  
N.C  
N.C  
I/O7  
I/O6  
I/O5  
I/O4  
N.C  
N.C  
N.C  
Vcc  
Vss  
N.C  
N.C  
N.C  
I/O3  
I/O2  
I/O1  
I/O0  
N.C  
N.C  
N.C  
N.C  
N.C  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
N.C  
2
N.C  
3
N.C  
4
N.C  
5
N.C  
6
R/B  
7
RE  
8
CE  
9
N.C  
10  
N.C  
11  
Vcc  
Vss  
N.C  
N.C  
CLE  
ALE  
WE  
WP  
N.C  
N.C  
N.C  
N.C  
N.C  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
PACKAGE DIMENSIONS  
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)  
48 - TSOP1 - 1220AF  
Unit :mm/Inch  
20.00±0.20  
0.787±0.008  
#1  
#48  
#24  
#25  
1.00±0.05  
0.039±0.002  
0.05  
0.002  
MIN  
1.20  
0.047  
MAX  
18.40±0.10  
0.724±0.004  
0~8°  
0.45~0.75  
0.018~0.030  
0.50  
0.020  
(
)
4
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
PIN CONFIGURATION (FBGA)  
K9F1208X0C-JCB0/JIB0  
1
2
3
4
5
6
N.C N.C  
N.C N.C  
N.C N.C  
N.C  
A
B
/WP ALE Vss /CE /WE R/B  
NC  
NC  
NC  
NC  
/RE CLE NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
C
D
E
NC  
NC  
NC  
NC NC  
NC NC  
NC NC  
F
NC I/O0 NC  
NC  
NC  
Vcc  
G
H
NC I/O1 NC VccQ I/O5 I/O7  
Vss I/O2 I/O3 I/O4 I/O6 Vss  
N.C N.C  
N.C N.C  
N.C N.C  
N.C N.C  
Top View  
5
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
63-Ball FBGA (measured in millimeters)  
Top View  
Bottom View  
#A1 INDEX MARK(OPTIONAL)  
A
8.50±0.10  
0.80 x 9= 7.20  
0.80 x 5= 4.00  
0.80  
8.50±0.10  
B
6
5
4
3
2
1
#A1  
(Datum A)  
A
B
C
D
E
F
(Datum B)  
G
H
63-0.45±0.05  
0.20  
M A B  
2.00  
Side View  
13.00±0.10  
0.10MAX  
0.45±0.05  
6
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
PIN DESCRIPTION  
Pin Name  
Pin Function  
DATA INPUTS/OUTPUTS  
I/O0 ~ I/O7  
CLE  
The I/O pins are used to input command, address and data, and to output data during read operations. The I/  
O pins float to high-z when the chip is deselected or when the outputs are disabled.  
COMMAND LATCH ENABLE  
The CLE input controls the activating path for commands sent to the command register. When active high,  
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.  
ADDRESS LATCH ENABLE  
ALE  
The ALE input controls the activating path for address to the internal address registers. Addresses are  
latched on the rising edge of WE with ALE high.  
CHIP ENABLE  
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and  
the device does not return to standby mode in program or erase opertion. Regarding CE control during read  
operation, refer to ’Page read’ section of Device operation .  
CE  
READ ENABLE  
RE  
WE  
WP  
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid  
tREA after the falling edge of RE which also increments the internal column address counter by one.  
WRITE ENABLE  
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of  
the WE pulse.  
WRITE PROTECT  
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage  
generator is reset when the WP pin is active low.  
READY/BUSY OUTPUT  
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or  
random read operation is in process and returns to high state upon completion. It is an open drain output and  
does not float to high-z condition when the chip is deselected or when outputs are disabled.  
R/B  
POWER  
Vcc  
Vss  
N.C  
VCC is the power supply for device.  
GROUND  
NO CONNECTION  
Lead is not internally connected.  
DO NOT USE  
Leave it disconnected.  
DNU  
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.  
Do not leave VCC or VSS disconnected.  
7
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
Figure 1. K9F1208X0C FUNCTIONAL BLOCK DIAGRAM  
VCC  
VSS  
X-Buffers  
A9 - A25  
512M + 16M Bits  
Latches  
NAND Flash  
ARRAY  
& Decoders  
Y-Buffers  
Latches  
A0 - A7  
& Decoders  
(512 + 16)Bytes x 131,072  
Page Register & S/A  
Y-Gating  
A8  
Command  
Command  
Register  
I/O Buffers & Latches  
Global Buffers  
VCC  
VSS  
CE  
RE  
WE  
Control Logic  
& High Voltage  
Generator  
I/0 0  
I/0 7  
Output  
Driver  
CLE ALE  
WP  
Figure 2. K9F1208X0C ARRAY ORGANIZATION  
1 Block = 32 Pages  
= (16K + 512) Bytes  
1 Page = 528 Bytes  
1 Block = 528 Bytes x 32 Pages  
= (16K + 512) Bytes  
1 Device = 528Bytes x 32Pages x 4,096 Blocks  
= 528 Mbits  
128K Pages  
(=4,096 Blocks)  
1st half Page Register  
(=256 Bytes)  
2nd half Page Register  
(=256 Bytes)  
8 bits  
512Bytes  
16 Bytes  
16 Bytes  
I/O 0 ~ I/O 7  
Page Register  
512 Bytes  
I/O 0  
A0  
I/O 1  
A1  
I/O 2  
A2  
I/O 3  
I/O 4  
I/O 5  
A5  
I/O 6  
A6  
I/O 7  
A7  
1st Cycle  
2nd Cycle  
3rd Cycle  
4th Cycle  
A3  
A12  
A20  
*L  
A4  
A13  
A21  
*L  
Column Address  
Row Address  
(Page Address)  
A9  
A10  
A18  
*L  
A11  
A19  
*L  
A14  
A22  
*L  
A15  
A23  
*L  
A16  
A24  
*L  
A17  
A25  
NOTE : Column Address : Starting Address of the Register.  
00h Command(Read) : Defines the starting address of the 1st half of the register.  
01h Command(Read) : Defines the starting address of the 2nd half of the register.  
* A8 is set to "Low" or "High" by the 00h or 01h Command.  
* L must be set to "Low".  
* The device ignores any additional input of address cycles than reguired.  
8
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
Product Introduction  
The K9F1208X0C is a 528Mbits(553,648,218 bits) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen col-  
umns are located from column address of 512 to 527. A 528-bytes data register is connected to memory cell arrays accommodating  
data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of  
16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the  
32 pages formed two NAND structures. A NAND structure consists of 16 cells. Total 135,168 NAND structures reside in a block. The  
program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory  
array consists of 4,096 separately erasable 16K-bytes blocks. It indicates that the bit by bit erase operation is prohibited on the  
K9F1208X0C.  
The K9F1208X0C has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems  
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through  
I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address  
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 64M byte physical space requires  
26 addresses, thereby requiring four cycles for byte-level addressing : 1 cycle of column address, 3 cycles of row address, in that  
order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase oper-  
ation, however, only the 3 cycles of row address are used. Device operations are selected by writing specific commands into the  
command register. Table 1 defines the specific commands of the K9F1208X0C.  
Table 1. Command Sets  
Acceptable Command  
Function  
1’st Cycle  
2’nd Cycle  
during Busy  
(1)  
Read 1  
-
00h/01h  
Read 2  
50h  
90h  
FFh  
80h  
60h  
41h  
42h  
43h  
70h  
7Ah  
-
Read ID  
-
Reset  
-
O
Page Program  
Block Erase  
Block Protect 1  
Block Protect 2  
Block Protect 3  
Read Status  
10h  
D0h  
-
-
-
-
-
O
Read Protection Status  
NOTE : 1. The 00h/01h command defines starting address of the 1st/2nd half of registers.  
After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h)  
on the next cycle.  
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.  
9
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
ABSOLUTE MAXIMUM RATINGS  
Rating  
Parameter  
Symbol  
Unit  
1.8V Device  
-0.6 to + 2.45  
-0.6 to + 2.45  
2.7V/3.3V Device  
VCC  
VIN  
-0.6 to + 4.6  
Voltage on any pin relative to VSS  
V
-0.6 to + 4.6  
VI/O  
-0.6 to Vcc + 0.3 (< 2.45V)  
-0.6 to Vcc + 0.3 (< 4.6V)  
K9F1208X0C-XCB0  
K9F1208X0C-XIB0  
K9F1208X0C-XCB0  
K9F1208X0C-XIB0  
-10 to +125  
Temperature Under  
Bias  
TBIAS  
°C  
-40 to +125  
-65 to +150  
5
Storage Temperature  
TSTG  
IOS  
°C  
mA  
Short Circuit Current  
NOTE :  
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.  
Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.  
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions  
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
RECOMMENDED OPERATING CONDITIONS  
(Voltage reference to GND at the condision of K9F1208X0C-XCB0 : TA=0 to 70°C or K9F1208X0C-XIB0 : TA=-40 to 85°C)  
1.8V(K9F1208R0C)  
2.7V(K9F1208B0C)  
3.3V(K9F1208U0C)  
Parameter  
Symbol  
Unit  
Min  
Typ.  
1.8  
0
Max  
Min  
Typ.  
2.7  
0
Max  
Min  
Typ.  
3.3  
0
Max  
VCC  
VSS  
1.65  
0
1.95  
0
2.5  
0
2.9  
0
2.7  
0
3.6  
0
V
V
Supply Voltage  
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions otherwise noted.)  
K9F1208X0C  
Uni  
t
Parameter  
Symbol  
Test Conditions  
1.8V  
2.7V  
3.3V  
Min Typ Max Min Typ Max Min Typ Max  
tRC=42ns, CE=VIL,  
IOUT=0mA  
Sequential  
Read  
ICC1  
-
8
20  
-
10 20  
-
10 20  
Operating  
Current  
Program  
Erase  
ICC2  
ICC3  
ISB1  
-
-
-
-
8
8
-
20  
20  
1
-
-
-
10 20  
10 20  
-
-
-
10 20  
10 20  
mA  
-
CE=VIH, WP=0V/VCC  
Stand-by Current(TTL)  
Stand-by Current(CMOS)  
Input Leakage Current  
Output Leakage Current  
-
1
-
1
CE=VCC-0.2, WP=0V/VCC  
VIN=0 to Vcc(max)  
ISB2  
ILI  
-
-
-
10  
-
50  
-
-
-
10 50  
-
-
-
10 50  
±10  
±10  
-
-
±10  
±10  
-
-
±10  
±10  
VCC  
µA  
ILO  
VOUT=0 to Vcc(max)  
-
VCC  
-0.4  
VCC  
-0.4  
VCC  
VCC  
+0.3  
VIH  
VIL  
Input High Voltage  
-
-
-
-
2.0  
-
-
+0.  
3
+0.3  
Input Low Voltage, All inputs  
-
-0.3  
0.4 -0.3  
0.5 -0.3  
0.8  
K9F1208R0C: IOH=-100µA  
K9F1208B0C: IOH=-100µA  
K9F1208U0C: IOH=-400µA  
VCC  
-0.1  
VCC  
V
VOH  
Output High Voltage Level  
Output Low Voltage Level  
-
-
-
-
2.4  
-
-
-0.4  
K9F1208R0C: IOL=100µA  
K9F1208B0C: IOL=100µA  
K9F1208U0C: IOL=2.1mA  
VOL  
-
-
0.1  
-
-
-
0.4  
-
-
-
0.4  
-
IOL(R/B) VOL=0.4V  
Output Low Current(R/B)  
3
4
3
4
8
10  
mA  
Notes :  
1. Typical values are measured at Vcc=3.3V, TA=25°C. And not 100% tested.  
10  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
VALID BLOCK  
Parameter  
Symbol  
Min  
Typ.  
Max  
Unit  
Valid Block Number  
NVB  
4,026  
-
4,096  
Blocks  
NOTE :  
1. The K9F1208X0C may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks  
is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or  
program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.  
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.  
3. Minimum 1,004 valid blocks are guaranteed for each contiguous 128Mb memory space.  
AC TEST CONDITION  
(K9F1208X0C-XCB0 :TA=0 to 70°C, K9F1208X0C-XIB0:TA=-40 to 85°C).  
Value  
Parameter  
K9F1208R0C  
K9F1208B0C  
0V to Vcc  
5ns  
K9F1208U0C  
0.4V to 2.4V  
5ns  
0V to VCC  
Input Pulse Levels  
Input Rise and Fall Times  
5ns  
VCC/2  
Input and Output Timing Levels  
K9F1208R0C:Output Load (Vcc:1.8V +/-10%)  
Vcc/2  
1.5V  
1 TTL GATE and  
CL=100pF  
K9F1208B0C:Output Load (Vcc:2.7V +/-10%) 1 TTL GATE and CL=30pF 1 TTL GATE and CL=30pF  
K9F1208U0C:Output Load (Vcc:3.3V +/-10%)  
K9F1208U0C:Output Load (Vcc:3.0V +/-10%)  
-
-
1 TTL GATE and CL=50pF  
CAPACITANCE(TA=25°C, VCC=1.8V/2.7V/3.3V, f=1.0MHz)  
Item  
Symbol  
Test Condition  
VIL=0V  
Min  
Max  
Unit  
pF  
Input/Output Capacitance  
Input Capacitance  
CI/O  
-
-
10  
10  
CIN  
VIN=0V  
pF  
NOTE : Capacitance is periodically sampled and not 100% tested.  
MODE SELECTION  
CLE  
H
L
ALE  
L
CE  
L
WE  
RE  
H
WP  
Mode  
Command Input  
X
Read Mode  
Write Mode  
H
L
L
H
X
Address Input (4 clocks)  
Command Input  
H
L
L
H
H
H
L
L
H
H
Address Input (4 clocks)  
L
L
H
H
Data Input  
Data Output  
L
L
L
H
H
X
X
X
X
X
X
L
L
L
H
H
X
X
X
X
X
During Read (Busy) on K9F1208X0C_P  
During Read (Busy) except on K9F1208X0C_P  
During Program (Busy)  
X
X
X
X
X
X
H
X
X
X
H
X
X
H
L
During Erase (Busy)  
X(1)  
X
X
Write Protect  
(2)  
X
Stand-by  
0V/VCC  
NOTE : 1. X can be VIL or VIH.  
2. WP should be biased to CMOS high or CMOS low for standby.  
11  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
Program / Erase Characteristics  
Parameter  
Symbol  
Min  
Typ  
Max  
500  
1
Unit  
µs  
(1)  
Program Time  
-
-
-
-
200  
tPROG  
Main Array  
Spare Array  
-
-
cycle  
cycle  
ms  
Number of Partial Program Cycles  
in the Same Page  
Nop  
2
Block Erase Time  
tBERS  
2
3
NOTE NOTE: 1.Typical Program time is defined as the time within which more than 50% of the whole pages are programmed at Vcc of 3.3V and 25’C  
AC TIMING CHARACTERISTICS FOR COMMAND / ADDRESS / DATA INPUT  
Parameter  
Symbol  
tCLS  
Min  
21  
5
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CLE setup Time  
CLE Hold Time  
CE setup Time  
CE Hold Time  
-
-
-
-
-
-
-
-
-
-
-
tCLH  
tCS  
31  
5
tCH  
(1)  
WE Pulse Width  
ALE setup Time  
ALE Hold Time  
Data setup Time  
Data Hold Time  
Write Cycle Time  
WE High Hold Time  
21  
21  
5
tWP  
tALS  
tALH  
tDS  
20  
5
tDH  
tWC  
tWH  
42  
15  
NOTE: The transition of the corresponding control pins must occur only once while WE is held low.  
12  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
AC CHARACTERISTICS FOR OPERATION  
Parameter  
Data Transfer from Cell to Register  
ALE to RE Delay  
Symbol  
tR  
Min  
-
Max  
Unit  
µs  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
ns  
ns  
ns  
15  
tAR  
10  
10  
20  
21  
-
-
CLE to RE Delay  
tCLR  
tRR  
-
Ready to RE Low  
-
RE Pulse Width  
tRP  
-
WE High to Busy  
tWB  
100  
Read Cycle Time  
tRC  
42  
-
-
RE Access Time  
tREA  
tCEA  
tRHZ  
tCHZ  
tCSD  
tOH  
30  
CE Access Time  
-
35  
RE High to Output Hi-Z  
CE High to Output Hi-Z  
CE High to ALE or CLE Don’t Care  
RE or CE High to Output hold  
RE High Hold Time  
-
30  
-
20  
10  
15  
15  
0
-
-
tREH  
tIR  
-
Output Hi-Z to RE Low  
-
WE High to RE Low  
tWHR  
tRST  
60  
-
-
5/10/500(1)  
Device resetting time(Read/Program/Erase)  
RE Pulse Width during Busy State  
Read Cycle Time during Busy State  
RE Access Time during Busy State  
(2)  
35  
50  
-
-
-
tRPB  
(2)  
tRCB  
(2)  
40  
tREAB  
Parameter  
Symbol  
Min  
Max  
100  
5
Uni  
ns  
Last RE High to Busy(at sequential read)  
tRB  
-
-
K9F1208X0C-P only  
CE High to Ready(in case of interception by CE at read)  
CE High Hold Time(at the last serial read)(4)  
tCRY  
tCEH  
µs  
100  
-
ns  
NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.  
2. This parameter (tRPB/tRCB/tREAB) must be used only for 1.8V device.  
3. The time to Ready depends on the value of the pull-up resistor tied R/B pin.  
13  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
NAND Flash Technical Notes  
Initial Invalid Block(s)  
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.  
The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid  
block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid  
block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a  
select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is  
placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.  
Identifying Initial Invalid Block(s)  
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The  
initial invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of  
every initial invalid block has non-FFh data at the column address of 517. Since the initial invalid block information is also erasable  
in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize  
the initial invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following sug-  
gested flow chart(Figure 3). Any intentional erasure of the initial invalid block information is prohibited.  
Start  
Set Block Address = 0  
Increment Block Address  
Check "FFh" at the column address 517  
*
of the 1st and 2nd page in the block  
No  
Create (or update)  
Initial Invalid Block(s) Table  
Check "FFh" ?  
Yes  
No  
Last Block ?  
Yes  
End  
Figure 3. Flow chart to create initial invalid block table.  
14  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
NAND Flash Technical Notes (Continued)  
Error in write or read operation  
Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the block  
failure rate.The following possible failure modes should be considered to implement a highly reliable system. In the case of status  
read failure after erase or program, block replacement should be done. Because program status fail during a page program does not  
affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an  
erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC  
must be employed. To improve the efficiency of memory space, it is recommended that the read failure due to single bit error should  
be reclaimed by ECC without any block replacement. The block failure rate in the qualification report does not include those  
reclaimed blocks.  
Failure Mode  
Erase Failure  
Detection and Countermeasure sequence  
Status Read after Erase --> Block Replacement  
Status Read after Program --> Block Replacement  
Verify ECC -> ECC Correction  
Write  
Read  
Program Failure  
Single Bit Failure  
: Error Correcting Code --> Hamming Code etc.  
Example) 1bit correction & 2bits detection  
ECC  
Program Flow Chart  
Start  
Write 80h  
Write Address  
Write Data  
Write 10h  
Read Status Register  
No  
I/O 6 = 1 ?  
or R/B = 1 ?  
Yes  
*
No  
Program Error  
I/O 0 = 0 ?  
Yes  
Program Completed  
: If program operation results in an error, map out  
the block including the page in error and copy the  
target data to another block.  
*
15  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
NAND Flash Technical Notes (Continued)  
Erase Flow Chart  
Read Flow Chart  
Start  
Start  
Write 60h  
Write 00h  
Write Block Address  
Write Address  
Read Data  
Write D0h  
Read Status Register  
ECC Generation  
No  
No  
I/O 6 = 1 ?  
or R/B = 1 ?  
Reclaim the Error  
Verify ECC  
Yes  
Yes  
*
No  
Page Read Completed  
Erase Error  
I/O 0 = 0 ?  
Yes  
Erase Completed  
: If erase operation results in an error, map out  
the failing block and replace it with another block.  
*
Block Replacement  
Block A  
1st  
2
{
(n-1)th  
nth  
an error occurs.  
(page)  
Buffer memory of the controller.  
Block B  
1st  
1
{
(n-1)th  
nth  
(page)  
* Step1. When an error happens in the nth page of the Block ’A’ during erase or program operation.  
* Step2. Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)  
* Step3. Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.  
* Step4. Do not further erase Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.  
16  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
Pointer Operation of K9F1208X0C  
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’  
command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets  
the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole  
page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effective  
only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command, the  
address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted  
before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting from  
’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.  
"A" area  
"B" area  
"C" area  
(00h plane)  
(01h plane)  
(50h plane)  
256 Bytes  
256 Bytes  
16 Bytes  
Table 2. Destination of the pointer  
Command  
Pointer position  
Area  
00h  
01h  
50h  
0 ~ 255 byte  
256 ~ 511 byte  
512 ~ 527 byte  
1st half array(A)  
2nd half array(B)  
spare array(C)  
"A"  
"B"  
"C"  
Internal  
Page Register  
Pointer select  
commnad  
(00h, 01h, 50h)  
Pointer  
Figure 4. Block Diagram of Pointer Operation  
(1) Command input sequence for programming ’A’ area  
The address pointer is set to ’A’ area(0~255), and sustained  
Address / Data input  
Address / Data input  
00h  
80h  
10h  
00h  
80h  
10h  
’A’,’B’,’C’ area can be programmed.  
’00h’ command can be omitted.  
It depends on how many data are inputted.  
(2) Command input sequence for programming ’B’ area  
The address pointer is set to ’B’ area(256~511), and will be reset to  
’A’ area after every program operation is executed.  
Address / Data input  
Address / Data input  
80h 10h  
01h  
80h  
10h  
01h  
’B’, ’C’ area can be programmed.  
It depends on how many data are inputted.  
’01h’ command must be rewritten before  
every program operation  
(3) Command input sequence for programming ’C’ area  
The address pointer is set to ’C’ area(512~527), and sustained  
Address / Data input  
Address / Data input  
80h 10h  
50h  
80h  
10h  
50h  
Only ’C’ area can be programmed.  
’50h’ command can be omitted.  
17  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
System Interface Using CE don’t-care.  
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal  
528bytes page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for  
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-  
ing would provide significant savings in power consumption.  
Figure 5. Program Operation with CE don’t-care.  
CLE  
CE don’t-care  
CE  
WE  
ALE  
80h  
Start Add.(4Cycle)  
Data Input  
Data Input  
10h  
I/OX  
tCH  
tCEA  
tCS  
CE  
CE  
tREA  
RE  
tWP  
WE  
I/OX  
out  
Figure 6. Read Operation with CE don’t-care.  
On K9F1208X0C-P  
CE must be held  
low during tR  
CLE  
CE don’t-care  
CE  
RE  
ALE  
tR  
R/B  
WE  
Data Output(sequential)  
I/OX  
00h  
Start Add.(4Cycle)  
18  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
* Command Latch Cycle  
CLE  
tCLH  
tCH  
tCLS  
tCS  
CE  
tWP  
WE  
tALS  
tALH  
ALE  
I/OX  
tDH  
tDS  
Command  
* Address Latch Cycle  
tCLS  
CLE  
tCS  
tWC  
tWC  
tWC  
CE  
tWP  
tWP  
tWP  
tWP  
WE  
tWH  
tALH  
tWH  
tALH  
tWH  
tALH  
tALH  
tALS  
tALS  
tALS  
tALS  
ALE  
tDH  
tDH  
tDH  
tDH  
tDS  
tDS  
tDS  
tDS  
A0~A7  
A9~A16  
A17~A24  
A25~A26  
I/OX  
19  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
* Input Data Latch Cycle  
tCLH  
CLE  
tCH  
CE  
tWC  
ALE  
tALS  
tWP  
tWP  
tWP  
WE  
tWH  
tDH  
tDH  
tDH  
tDS  
tDS  
tDS  
I/Ox  
DIN n  
DIN 0  
DIN 1  
* Serial access Cycle after Read(CLE=L, WE=H, ALE=L)  
tRC  
CE  
tCHZ*  
tOH  
tREH  
tREA  
tREA  
tREA  
RE  
tRHZ*  
tOH  
tRHZ*  
I/Ox  
Dout  
Dout  
Dout  
tRR  
R/B  
NOTES : Transition is measured ±200mV from steady state voltage with load.  
This parameter is sampled and not 100% tested.  
20  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
Status Read Cycle (During Ready State)  
tCLR  
CLE  
tCLS  
tCLH  
tCS  
CE  
tCH  
tWP  
WE  
tCEA  
tCHZ  
tOH  
tWHR  
RE  
tRP  
tRHZ  
tOH  
tDH  
tREA  
tDS  
tIR  
Status Output  
I/OX  
R/B  
70h/7Ah  
Status Read Cycle (During Busy State)  
tCLR  
CLE  
tCLS  
tCLH  
tCS  
CE  
tCH  
tWP  
WE  
tCEA  
tCHZ  
tOH  
tWHR  
RE  
tRPB  
tRHZ  
tOH  
tDH  
tREAB  
tDS  
tIR  
Status Output  
I/OX  
R/B  
70h/7Ah  
21  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
READ1 OPERATION (READ ONE PAGE)  
CLE  
1)  
tCEH  
On K9F1208X0C-P  
CE must be held  
low during tR  
CE  
tCHZ  
tOH  
tWC  
WE  
tWB  
tCRY  
tAR  
ALE  
tRHZ  
tOH  
tR  
tRC  
RE  
N Address  
tRR  
A9 ~ A16  
A17 ~ A24  
Dout N+2  
Dout N+1  
00h or 01h A0 ~ A7  
Dout N  
Dout m  
tRB  
A25  
I/OX  
R/B  
Column  
Address  
Page(Row)  
Address  
Busy  
1)  
X8 device : m = 528 , Read CMD = 00h or 01h  
NOTES : 1) is only valid on K9F1208X0C-P  
Read1 Operation (Intercepted by CE)  
CLE  
On K9F1208U0C-P  
CE must be held  
low during tR  
CE  
WE  
ALE  
RE  
tWB  
tCHZ  
tOH  
tAR  
tR  
tRC  
tRR  
A9 ~ A16 A17 ~ A24  
Dout N+2  
00h or 01h A0 ~ A7  
Dout N  
Dout N+1  
A25  
I/OX  
R/B  
Page(Row)  
Address  
Column  
Address  
Busy  
22  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
Read2 Operation (Read One Page)  
CLE  
CE  
On K9F1208X0C-P  
CE must be held  
low during tR  
WE  
ALE  
RE  
tR  
tWB  
tAR  
tRR  
Dout  
n+M  
50h  
A9 ~ A16 A17 ~ A24  
n+m  
A0 ~ A7  
A25  
I/OX  
R/B  
Selected  
Row  
M Address  
A0~A3 : Valid Address  
A4~A7 : Dont care  
16  
512  
Start  
address M  
Sequential Row Read Operation (Within a Block)  
CLE  
CE  
WE  
ALE  
RE  
Dout  
N
Dout  
N+1  
Dout  
527  
Dout  
0
Dout  
1
Dout  
527  
00h  
A0 ~ A7 A9 ~ A16  
A17 ~ A24  
A25  
I/OX  
R/B  
Ready  
Busy  
Busy  
M
M+1  
Output  
N
Output  
23  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
Page Program Operation  
CLE  
CE  
tWC  
tWC  
tWC  
WE  
ALE  
RE  
tPROG  
tWB  
Din  
N
Din  
527  
A25  
10h  
80h  
A0 ~ A7 A9 ~ A16 A17 ~ A24  
70h  
I/O0  
I/OX  
R/B  
Sequential Data  
Input Command  
Column  
Program  
Command  
1 up to 528 Byte Data  
Serial Input  
Read Status  
Command  
Page(Row)  
Address  
Address  
I/O0=0 Successful Program  
I/O0=1 Error in Program  
Block Erase Operation (Erase One Block)  
CLE  
CE  
tWC  
WE  
ALE  
RE  
tBERS  
tWB  
60h  
A9 ~ A16 A17 ~ A24  
DOh  
70h  
I/O 0  
A25  
I/OX  
R/B  
Page(Row)  
Address  
Busy  
I/O0=0 Successful Erase  
Read Status I/O0=1 Error in Erase  
Command  
Erase Setup Command  
Erase Command  
24  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
Read ID Operation  
CLE  
CE  
WE  
ALE  
RE  
tREA  
3Fh  
00h  
ECh  
76h  
5Ah  
90h  
I/OX  
Read ID Command  
Maker Code Device Code  
Address. 1cycle  
ID Defintition Table  
90 ID : Access command = 90H  
Value  
Description  
1st Byte  
2nd Byte  
ECh  
76h  
5Ah  
3Fh  
Maker Code  
Device Code  
Don’t support Copy Back Operation  
Don’t support Multi Plane Operation  
3
4
rd Byte  
th Byte  
25  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
Device Operation  
PAGE READ  
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis-  
ter along with four address cycles. Once the command is latched, it does not need to be written for the following page read operation.  
Three types of operations are available : random read, serial page read and sequential row read.  
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred  
to the data registers in less than 15µs(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the  
output of R/B pin. CE must be held low while in busy for K9F1208X0C-PXB0, while CE is don’t-care with K9F1208X0C-JXB0. If CE  
goes high before the device returns to Ready, the random read operation is interrupted and Busy returns to Ready as the defined by  
tCRY. Since the operation was aborted, the serial page read does not output valid data. Once the data in a page is loaded into the reg-  
isters, they may be read out in 42ns cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data stat-  
ing from the selected column address up to the last column address.  
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of 512  
to 527 bytes may be selectively accessed by writing the Read2 command. Addresses A0 to A3 set the starting address of the spare  
area while addresses A4 to A7 are ignored. The Read1 command(00h/01h) is needed to move the pointer back to the main area. Fig-  
ures 7 to 10 show typical sequence and timings for each read operation.  
Sequential Row Read is available only on K9F1208X0C-P :  
After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 15µs  
again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation  
is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of  
each page may be sequentially read. The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of  
a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the  
next block, read command and address must be given. Figures 9, 10 show typical sequence and timings for sequential row read  
operation.  
26  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
Figure 7. Read1 Operation  
CLE  
On K9F1208X0C-P  
CE must be held low during tR  
CE  
WE  
ALE  
tR  
R/B  
RE  
00h  
Start Add.(4Cycle)  
A0 ~ A7 & A9 ~ A25  
Data Output(Sequential)  
I/O0~7  
(00h Command)  
Main array  
(01h Command)  
1)  
1st half array 2st half array  
Data Field  
Spare Field  
Data Field  
Spare Field  
NOTE :  
1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle.  
27  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
Figure 8. Read2 Operation  
CLE  
On K9F1208X0C-P  
CE  
CE must be held low during tR  
WE  
ALE  
R/B  
RE  
tR  
50h  
Data Output(Sequential)  
Spare Field  
Start Add.(4Cycle)  
I/OX  
A0 ~ A3 & A9 ~ A25  
(A4 ~ A7 : Fixed "Low")  
Main array  
Data Field  
Spare Field  
28  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
Figure 9. Sequential Row Read1 Operation (only for K9F1208X0C-P valid within a block)  
tR  
tR  
tR  
R/B  
I/OX  
Data Output  
1st  
Data Output  
Data Output  
00h  
01h  
Start Add.(4Cycle)  
A0 ~ A7 & A9 ~ A25  
2nd  
(528 Byte)  
Nth  
(528 Byte)  
( 00h Command)  
( 01h Command)  
1st half array  
2nd half array  
1st half array  
2nd half array  
1st  
1st  
2nd  
Nth  
Block  
2nd  
Nth  
Data Field  
Spare Field  
Data Field  
Spare Field  
The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is read-  
out, the sequential read operation must be terminated by bringing CE high. When the page address moves onto  
the next block, read command and address must be given.  
Figure 10. Sequential Row Read2 Operation (only for K9F1208X0C-P valid within a block)  
tR  
tR  
tR  
R/B  
Start Add.(4Cycle)  
A0 ~ A3 & A9 ~ A25  
Data Output  
1st  
I/OX  
50h  
Data Output  
Data Output  
2nd  
(16Byte)  
Nth  
(16Byte)  
(A4 ~ A7 :  
Don’t Care)  
1st  
Block  
Nth  
Data Field  
Spare Field  
29  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
PAGE PROGRAM  
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes  
up to 528 byte, in a single page program cycle. The number of consecutive partial page programming operation within the same page  
without an intervening erase operation must not exceed 1 for main array and 2 for spare array. The addressing may be done in any  
random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded  
into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.  
Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the attached  
technical notes.  
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address input and  
then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm com-  
mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-  
gramming process. The internal write state control automatically executes the algorithms and timings necessary for program and  
verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command  
may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle  
by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are  
valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 11).  
The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in  
Read Status command mode until another valid command is written to the command register.  
Figure11. Program Operation  
tPROG  
R/B  
Pass  
I/O0~7  
80h  
Address & Data Input  
I/O0  
Fail  
10h  
70h  
A0 ~ A7 & A9 ~ A25  
528 Bytes Data  
BLOCK ERASE  
The Erase operation is done on a block(16K Bytes) basis. Block address loading is accomplished in three cycles initiated by an  
Erase Setup command(60h). Only address A14 to A26 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following  
the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command  
ensures that memory contents are not accidentally erased due to external noise conditions.  
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When  
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 8 details the sequence.  
Figure 12. Block Erase Operation  
tBERS  
R/B  
Pass  
I/OX  
60h  
I/O0  
Fail  
70h  
Address Input(3Cycle)  
Block Add. : A14 ~ A25  
D0h  
30  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
BLOCK PROTECT  
Each block is protected from programming and erasing, controlled by the protect flag written in a specified area in the block. Block  
Proctect opreation is initiated by wirting 4xh-80h-10h to the command register along with four address cycles. Only address A14 to  
A26 is valid while A0 to A13 is fixed as 00h. The data must not be loaded. Once the Block Protect opreation starts, the Read Status  
Register command may be entered, with RE and CE low, to read the status register. The system controller can detect the completion  
of Page Program operation for protecting a block by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the  
Read Status command and Reset command are valid while Block Protect operation is in progress. But, if Reset command is inputted  
while Block Protect operation is in progress, the block will not be guaranteed whether it is protected or not. When the Page Program  
operation for protecting a block is completed, the Write Status Bit(I/O 0) may be checked(Figure 13). The command register remains  
in Read Status command mode until another valid command is written to the command register.  
When programming is prohibited by 41h command, the protect flag and the data of protected block can be erased by Block Erase  
operation. Once erasing is prohibited by 42h/43h command, the protect flag and the data of protected block can not be erased. If  
80h-10h is written to command register along with four address cycles at the program protected block or at the program/erase pro-  
tected block, and if 60h-D0h is written to command register along with three address cycles at the program/erase protected block,  
the R/B pin changes to low for tR. The Block Protect operation must not be excuted on the aleady protected block. The Block Protect  
operation will be aborted by Reset command(FFh). The Block Protect operation can only be used from first block to 200th block.  
The device contains a Status Register which may be used to read out the state of the selected block. After writing 7Ah command to  
the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, which-  
ever occurs last(Figure 14). Refer to table 3 for specific Status Register definitions. The command register remains in Status Read  
mode until further commands are issued to it.  
Three commands are provided to protect the block.  
41h : Programming is prohibited  
42h : Erasing is prohibited  
43h : Both programming and erasing are prohibited  
Figure 13. Block Protect Operation  
tPROG  
R/B  
Pass  
4Xh  
80h  
Address Input(4Cycle)  
I/O0  
I/OX  
10h  
70h  
FFh  
FFh  
A0 ~ A7 : 00h Fix  
A9 ~ A13 : 00h Fix  
A14 ~ A25 : 0 to 4095  
Fail  
31  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
Figure 14. Read Block Status  
CLE  
ALE  
WE  
00h  
A0 ~ A7 A9 ~ A16  
A25  
7Ah  
Status  
A17 ~ A24  
I/OX  
A0~7 : 00h, A9~13 : 0 fixed, A14~25 : 0 to 4095  
RE  
tR  
R/B  
Table 3. Status Register Definition for 7Ah Command  
I/O  
Status  
Programming Protect  
Erasing Protect  
Not use  
Definition  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
Not protected : "0"  
Not protected : "0"  
Don’t -cared  
Protected : "1"  
Protected : "1"  
Not Use  
Don’t -cared  
Not Use  
Don’t -cared  
Not Use  
Don’t -cared  
Device Operation  
Write Protect  
Busy: "0"  
Ready : "1"  
Protected : "0"  
Not protect : "1"  
NOTE :  
1. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.  
32  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
READ STATUS  
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether  
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs  
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows  
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE  
does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register  
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read  
cycle, a read command(00h or 50h) should be given before sequential page read cycle.  
Table 4. Status Register Definition for 70h Command  
I/O  
Page Program  
Pass/Fail  
Not use  
Block Erase  
Pass/Fail  
Not use  
Read  
Not use  
Definition  
Fail : "1"  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
Pass : "0"  
Not use  
Don’t -cared  
Don’t -cared  
Don’t -cared  
Don’t -cared  
Don’t -cared  
Busy : "0"  
Not use  
Not use  
Not use  
Not Use  
Not Use  
Not Use  
Not Use  
Not Use  
Not Use  
Not Use  
Not Use  
Not Use  
Ready/Busy  
Write Protect  
Ready/Busy  
Write Protect  
Ready/Busy  
Write Protect  
Ready : "1"  
Protected : "0"  
Not Protected : "1"  
NOTE : 1. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.  
.
Read ID  
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of  
00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th cycle ID respectively. The  
command register remains in Read ID mode until further commands are issued to it. Figure 15 shows the operation sequence.  
Figure 15. Read ID Operation  
CLE  
tCEA  
CE  
WE  
tAR  
ALE  
RE  
tWHR  
tREA  
Device  
I/O0~7  
90h  
ECh  
00h  
5Ah  
3Fh  
Code  
Maker code  
Address. 1cycle  
Device  
Device Code  
K9F1208R0C  
36h  
K9F1208B0C  
K9F1208U0C  
76h  
76h  
33  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
RESET  
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random  
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no  
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and  
the Status Register is cleared to value C0h when WP is high. If the device is already in reset state a new reset command will be  
accepted by the command register. The R/B pin changes to low for tRST after the Reset command is written. Refer to Figure 16  
below.  
Figure 16. RESET Operation  
tRST  
R/B  
I/OX  
FFh  
Table 5. Device Status  
After Power-up  
After Reset  
Operation mode  
00h Command is latched  
Waiting for next command  
34  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
READY/BUSY  
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random  
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis-  
ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is  
an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and  
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 17). Its value can be  
determined by the following guidance.  
Rp  
ibusy  
1.8V device - VOL : 0.1V, VOH : Vcc-0.1V  
2.7V device - VOL : 0.4V, VOH : VccQ-0.4V  
3.3V device - VOL : 0.4V, VOH : 2.4V  
VCC  
Ready Vcc  
R/B  
VOH  
open drain output  
VOL : 0.4V, VOH : 2.4V  
CL  
VOL  
Busy  
tf  
tr  
GND  
Device  
35  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
@ Vcc = 1.8V, Ta = 25°C , CL = 30pF  
Ibusy  
300n  
3m  
1.7  
200n  
100n  
2m  
1m  
120  
0.85  
60  
90  
tr  
30  
0.57  
1.7  
0.43  
1.7  
1.7  
2K  
tf  
1.7  
4K  
1K  
3K  
Rp(ohm)  
@ Vcc = 2.7V, Ta = 25°C , CL = 30pF  
300n  
3m  
2.3  
Ibusy  
200n  
100n  
1.1  
2m  
1m  
120  
90  
tr  
60  
30  
0.75  
2.3  
2.3  
2.3  
1K  
0.55  
tf  
2.3  
4K  
2K  
3K  
Rp(ohm)  
@ Vcc = 3.3V, Ta = 25°C , CL = 100pF  
400  
2.4  
Ibusy  
300n  
3m  
300  
1.2  
200n  
100n  
200  
0.8  
2m  
1m  
tr  
100  
3.6  
0.6  
3.6  
3.6  
2K  
3.6  
tf  
4K  
1K  
3K  
Rp(ohm)  
Figure 17. Rp vs tr ,tf & Rp vs ibusy  
Rp value guidance  
VCC(Max.) - VOL(Max.)  
IOL + ΣIL  
1.85V  
Rp(min, 1.8V part) =  
=
3mA + ΣIL  
VCC(Max.) - VOL(Max.)  
2.5V  
Rp(min, 2.7V part) =  
Rp(min, 3.3V part) =  
=
=
IOL + ΣIL  
3mA + ΣIL  
VCC(Max.) - VOL(Max.)  
3.2V  
IOL + ΣIL  
8mA + ΣIL  
where IL is the sum of the input currents of all devices tied to the R/B pin.  
Rp(max) is determined by maximum permissible limit of tr  
36  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
Data Protection & Power-up sequence  
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector  
disables all functions whenever Vcc is below about 1.1V(1.8V device), 1.8V(2.7V device), 2V(3.3V device). WP pin provides hard-  
ware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 100µs is  
required before internal circuit gets ready for any command sequences as shown in Figure 18. The two step command sequence for  
program/erase provides additional software protection.  
Figure 18. AC Waveforms for Power Transition  
1.8V device : ~ 1.5V  
2.7V device : ~ 2.0V  
3.3V device : ~ 2.5V  
1.8V device : ~ 1.5V  
2.7V device : ~ 2.0V  
3.3V device : ~ 2.5V  
VCC  
High  
WP  
WE  
100µs  
37  
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
WP AC Timing guide  
Enabling WP during erase and program busy is prohibited. The erase and program operations are enabled and disabled as follows:  
Figure A-1. Program Operation  
1. Enable Mode  
WE  
I/O  
80h  
10h  
WP  
R/B  
tww(min.100ns)  
2. Disable Mode  
WE  
I/O  
80h  
10h  
WP  
R/B  
tww(min.100ns)  
Figure A-2. Erase Operation  
1. Enable Mode  
WE  
I/O  
60h  
D0h  
WP  
R/B  
tww(min.100ns)  
2. Disable Mode  
WE  
I/O  
60h  
D0h  
WP  
R/B  
tww(min.100ns)  
38  
配单直通车
K9F1208U0C-PCB0产品参数
型号:K9F1208U0C-PCB0
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Obsolete
包装说明:TSOP1, TSSOP48,.8,20
Reach Compliance Code:unknown
风险等级:5.79
Is Samacsys:N
最长访问时间:30 ns
命令用户界面:YES
数据轮询:NO
JESD-30 代码:R-PDSO-G48
JESD-609代码:e6
长度:18.4 mm
内存密度:536870912 bit
内存集成电路类型:FLASH
内存宽度:8
湿度敏感等级:3
功能数量:1
部门数/规模:4K
端子数量:48
字数:67108864 words
字数代码:64000000
工作模式:ASYNCHRONOUS
最高工作温度:70 °C
最低工作温度:
组织:64MX8
封装主体材料:PLASTIC/EPOXY
封装代码:TSOP1
封装等效代码:TSSOP48,.8,20
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE
页面大小:512 words
并行/串行:PARALLEL
峰值回流温度(摄氏度):260
电源:3/3.3 V
编程电压:3.3 V
认证状态:Not Qualified
就绪/忙碌:YES
座面最大高度:1.2 mm
部门规模:16K
最大待机电流:0.00005 A
子类别:Flash Memories
最大压摆率:0.02 mA
最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V
表面贴装:YES
技术:CMOS
温度等级:COMMERCIAL
端子面层:Tin/Bismuth (Sn97Bi3)
端子形式:GULL WING
端子节距:0.5 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
切换位:NO
类型:NAND TYPE
宽度:12 mm
Base Number Matches:1
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