K9F1G08UOE-SCBO中文资料应用文章市场行情现货热卖使用介绍-中国IC网-芯三七

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

Document Title

128M x 8 Bit / 64M x 16 Bit NAND Flash Memory

Revision History

Revision No History

Draft Date

July. 5. 2001

Nov. 5. 2001

Remark

0.0

0.1

1. Initial issue

Advance

1. Iol(R/B) of 1.8V is changed.

- min. value : 7mA --> 3mA

- Typ. value : 8mA --> 4mA

2. AC parameter is changed.

tRP(min.) : 30ns --> 25ns

3. A recovery time of minimum 1ms is required before internal circuit gets

ready for any command sequences as shown in Figure 17.

Dec. 4. 2001

---> A recovery time of minimum 10ms is required before internal circuit gets

ready for any command sequences as shown in Figure 17.

0.2

0.3

1. ALE status fault in ’Random data out in a page’ timing diagram(page 19)

is fixed.

1. tAR1, tAR2 are merged to tAR.(Page11)

(Before revision) min. tAR1 = 10ns , min. tAR2 = 50ns

(After revision) min. tAR = 10ns

Apr. 25. 2002

2. min. tCLR is changed from 50ns to 10ns.(Page11)

3. min. tREA is changed from 35ns to 30ns.(Page11)

4. min. tWC is changed from 50ns to 45ns.(Page11)

5. tRHZ is devided into tRHZ and tOH.(Page11)

- tRHZ : RE High to Output Hi-Z

- tOH : RE High to Output Hold

6. tCHZ is devided into tCHZ and tOH.(Page11)

- tCHZ : CE High to Output Hi-Z

- tOH : CE High to Output Hold

1. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 35)

2. Add the data protection Vcc guidence for 1.8V device - below about

1.1V. (Page 36)

Nov. 22.2002

0.4

1. The min. Vcc value 1.8V devices is changed.

K9F1GXXQ0M : Vcc 1.65V~1.95V --> 1.70V~1.95V

0.5

0.6

Mar. 6.2003

Mar. 13.2003

Pb-free Package is added.

K9F1G08U0M-FCB0,FIB0

K9F1G08Q0M-PCB0,PIB0

K9F1G08U0M-PCB0,PIB0

K9F1G16U0M-PCB0,PIB0

K9F1G16Q0M-PCB0,PIB0

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you

have any questions, please contact the SAMSUNG branch office near your office.

1

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

Document Title

128M x 8 Bit / 64M x 16 Bit NAND Flash Memory

Revision History

Revision No History

Draft Date

Remark

0.7

Errata is added.(Front Page)-K9F1GXXQ0M

tWC tWP tWH tRC tREH tRP tREA tCEA

Mar.17. 2003

Specification

45 25 15 50 15 25 30

45

75

Relaxed value 80 60 20 80 20 60 60

Apr. 9. 2003

Jul. 2. 2003

1. The 3rd Byte ID after 90h ID read command is don’t cared.

The 5th Byte ID after 90h ID read command is deleted.

0.8

0.9

1. 2.65V device is added.

2. Note is added.

(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for

durations of 20 ns or less.)

Aug. 5. 2003

1.0

AC parameters are changed-K9F1GXXQ0M

tWC tWP tWH tRC tREH tRP tREA tCEA

Before 45 25 15 50 15 25 30

After 80 60 20 80 20 60 60

45

75

Jan. 27. 2004

Apr. 23. 2004

Added Addressing method for program operation

1. Add the Protrusion/Burr value in WSOP1 PKG Diagram.

1. PKG(TSOP1, WSOP1) Dimension Change

1.1

1.2

1.3

May. 24. 2004

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you

have any questions, please contact the SAMSUNG branch office near your office.

2

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

128M x 8 Bit / 64M x 16 Bit NAND Flash Memory

PRODUCT LIST

Part Number

Vcc Range

Organization

PKG Type

K9F1G08Q0M-Y,P

K9F1G16Q0M-Y,P

K9F1G08D0M-Y,P

K9F1G16D0M-Y,P

K9F1G08U0M-Y,P

K9F1G16U0M-Y,P

K9F1G08U0M-V,F

X8

X16

X8

1.70 ~ 1.95V

TSOP1

2.4 ~ 2.9V

2.7 ~ 3.6V

TSOP1

X16

X8

TSOP1

X16

X8

WSOP1

FEATURES

· Voltage Supply

· Fast Write Cycle Time

-1.8V device(K9F1GXXQ0M): 1.70V~1.95V

- 2.65V device(K9F1GXXD0M) : 2.4~2.9V

-3.3V device(K9F1GXXU0M): 2.7 V ~3.6 V

- Program time : 300ms(Typ.)

- Block Erase Time : 2ms(Typ.)

· Command/Address/Data Multiplexed I/O Port

· Hardware Data Protection

· Organization

- Memory Cell Array

- Program/Erase Lockout During Power Transitions

· Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles

- Data Retention : 10 Years

-X8 device(K9F1G08X0M) : (128M + 4,096K)bit x 8bit

-X16 device(K9F1G16X0M) : (64M + 2,048K)bit x 16bit

- Data Register

-X8 device(K9F1G08X0M): (2K + 64)bit x8bit

-X16 device(K9F1G16X0M): (1K + 32)bit x16bit

- Cache Register

· Command Register Operation

· Cache Program Operation for High Performance Program

· Power-On Auto-Read Operation

-X8 device(K9F1G08X0M): (2K + 64)bit x8bit

-X16 device(K9F1G16X0M): (1K + 32)bit x16bit

· Automatic Program and Erase

- Page Program

· Intelligent Copy-Back Operation

· Unique ID for Copyright Protection

· Package :

- K9F1GXXX0M-YCB0/YIB0

-X8 device(K9F1G08X0M): (2K + 64)Byte

-X16 device(K9F1G16X0M): (1K + 32)Word

- Block Erase

48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)

- K9F1G08U0M-VCB0/VIB0

48 - Pin WSOP I (12X17X0.7mm)

-X8 device(K9F1G08X0M): (128K + 4K)Byte

-X16 device(K9F1G16X0M): (64K + 2K)Word

· Page Read Operation

- K9F1GXXX0M-PCB0/PIB0

48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package

- K9F1G08U0M-FCB0/FIB0

- Page Size

48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package

* K9F1G08U0M-V,F(WSOPI ) is the same device as

K9F1G08U0M-Y,P(TSOP1) except package type.

- X8 device(K9F1G08X0M): 2K-Byte

- X16 device(K9F1G16X0M) : 1K-Word

- Random Read : 25ms(Max.)

- Serial Access : 50ns(Min.)*

*K9F1GXXQ0M : 80ns

GENERAL DESCRIPTION

Offered in 128Mx8bit or 64Mx16bit, the K9F1GXXX0M is 1G bit with spare 32M bit capacity. Its NAND cell provides the most cost-

effective solution for the solid state mass storage market. A program operation can be performed in typical 300ms on the 2112-

byte(X8 device) or 1056-word(X16 device) page and an erase operation can be performed in typical 2ms on a 128K-byte(X8 device)

or 64K-word(X16 device) block. Data in the data page can be read out at 50ns(1.8V device : 80ns) cycle time per byte(X8 device) or

word(X16 device).. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write

controller automates all program and erase functions including pulse repetition, where required, and internal verification and margin-

ing of data. Even the write-intensive systems can take advantage of the K9F1GXXX0M¢s extended reliability of 100K program/erase

cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F1GXXX0M is an optimum solution for

large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.

3

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

PIN CONFIGURATION (TSOP1)

K9F1GXXX0M-YCB0,PCB0/YIB0,PIB0

X16 X8

X8

X16

N.C

I/O7

I/O6

I/O5

I/O4

N.C

PRE

Vcc

Vss

N.C

I/O3

I/O2

I/O1

I/O0

N.C

Vss

N.C

R/B

RE

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

N.C

R/B

RE

1

2

I/O15

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

N.C

3

4

5

6

7

8

CE

9

N.C

Vcc

Vss

N.C

CLE

ALE

WE

WP

N.C

Vcc

Vss

N.C

CLE

ALE

WE

WP

N.C

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48-pin TSOP1

Standard Type

12mm x 20mm

PRE

Vcc

N.C

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

Vss

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)

48 - TSOP1 - 1220AF

Unit :mm/Inch

20.00±0.20

0.787±0.008

#1

#48

#24

#25

1.00±0.05

0.039±0.002

0.05

0.002

MIN

1.20

0.047

MAX

18.40±0.10

0.724±0.004

0~8°

0.45~0.75

0.018~0.030

0.50

0.020

(

)

4

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

PIN CONFIGURATION (WSOP1)

K9F1G08U0M-VCB0,FCB0/VIB0,FIB0

N.C

DNU

N.C

I/O7

I/O6

I/O5

I/O4

N.C

DNU

N.C

Vcc

N.C

DNU

N.C

R/B

RE

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1

2

3

4

5

6

7

8

CE

9

DNU

N.C

Vcc

Vss

N.C

DNU

CLE

ALE

WE

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Vss

N.C

DNU

N.C

I/O3

I/O2

I/O1

I/O0

N.C

DNU

N.C

WP

N.C

DNU

N.C

PACKAGE DIMENSIONS

48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)

Unit :mm

48 - WSOP1 - 1217F

0.70 MAX

0.58±0.04

15.40±0.10

#1

#48

#24

#25

(0.01Min)

0.45~0.75

17.00±0.20

5

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

PIN DESCRIPTION

Pin Name

Pin Function

DATA INPUTS/OUTPUTS

I/O0 ~ I/O7

(K9F1G08X0M)

I/O0 ~ I/O15

The I/O pins are used to input command, address and data, and to output data during read operations. The I/

O pins float to high-z when the chip is deselected or when the outputs are disabled.

I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-

ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and

output.

(K9F1G16X0M)

COMMAND LATCH ENABLE

CLE

ALE

CE

The CLE input controls the activating path for commands sent to the command register. When active high,

commands are latched into the command register through the I/O ports on the rising edge of the WE signal.

ADDRESS LATCH ENABLE

The ALE input controls the activating path for address to the internal address registers. Addresses are

latched on the rising edge of WE with ALE high.

CHIP ENABLE

The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and

the device does not return to standby mode.

READ ENABLE

RE

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid

tREA after the falling edge of RE which also increments the internal column address counter by one.

WRITE ENABLE

WE

WP

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of

the WE pulse.

WRITE PROTECT

The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage

generator is reset when the WP pin is active low.

READY/BUSY OUTPUT

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or

random read operation is in process and returns to high state upon completion. It is an open drain output and

does not float to high-z condition when the chip is deselected or when outputs are disabled.

R/B

POWER-ON READ ENABLE

PRE

The PRE controls auto read operation executed during power-on. The power-on auto-read is enabled when

PRE pin is tied to Vcc.

POWER

Vcc

Vss

N.C

VCC is the power supply for device.

GROUND

NO CONNECTION

Lead is not internally connected.

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.

Do not leave VCC or VSS disconnected.

6

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

Figure 1-1. K9F1G08X0M (X8) Functional Block Diagram

VCC

VSS

1024M + 32M Bit

NAND Flash

ARRAY

X-Buffers

Latches

& Decoders

A12 - A27

A0 - A11

(2048 + 64)Byte x 65536

Data Register & S/A

Y-Buffers

Latches

& Decoders

Cache Register

Y-Gating

Command

Register

VCC

VSS

I/O Buffers & Latches

Global Buffers

CE

RE

WE

Control Logic

& High Voltage

Generator

I/0 0

Output

Driver

I/0 7

CLE ALE PRE

WP

Figure 2-1. K9F1G08X0M (X8) Array Organization

1 Block = 64 Pages

(128K + 4k) Byte

1 Page = (2K + 64)Bytes

1 Block = (2K + 64)B x 64 Pages

= (128K + 4K) Bytes

1 Device = (2K+64)B x 64Pages x 1024 Blocks

= 1056 Mbits

64K Pages

(=1,024 Blocks)

8 bit

2K Bytes

64 Bytes

I/O 0 ~ I/O 7

Page Register

2K Bytes

I/O 0

A0

I/O 1

A1

I/O 2

I/O 3

A3

I/O 4

A4

I/O 5

A5

I/O 6

A6

I/O 7

A7

Column Address

1st Cycle

2nd Cycle

3rd Cycle

4th Cycle

A2

A8

A9

A10

A14

A22

A11

A15

A23

*L

Row Address

A12

A20

A13

A21

A16

A24

A17

A25

A18

A26

A19

A27

NOTE : Column Address : Starting Address of the Register.

* L must be set to "Low".

* The device ignores any additional input of address cycles than reguired.

7

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

Figure 1-2. K9F1G16X0M (X16) Functional Block Diagram

VCC

VSS

1024M + 32M Bit

NAND Flash

ARRAY

X-Buffers

Latches

& Decoders

A11 - A26

A0 - A10

(512 + 64)Word x 65536

Data Register & S/A

Y-Buffers

Latches

& Decoders

Cache Register

Y-Gating

Command

Register

VCC

VSS

I/O Buffers & Latches

Global Buffers

CE

RE

WE

Control Logic

& High Voltage

Generator

I/0 0

Output

Driver

I/0 15

CLE ALE PRE

WP

Figure 2-2. K9F1G16X0M (X16) Array Organization

1 Block = 64 Pages

(64K + 2k) Word

1 Page = (1K + 32)Words

1 Block = (1K + 32)Word x 64 Pages

= (64K + 2K) Words

1 Device = (1K+32)Word x 64Pages x 1024 Blocks

= 1056 Mbits

64K Pages

(=1,024 Blocks)

16 bit

1K Words

32 Words

I/O 0 ~ I/O 15

Page Register

1K Words

I/O 0

A0

I/O 1

I/O 2

A2

I/O 3

I/O 4

A4

I/O 5

A5

I/O 6

A6

I/O 7

A7

I/O8 ~ 15

Column Address

1st Cycle

2nd Cycle

3rd Cycle

4th Cycle

A1

A9

A3

*L

Column Address

Row Address

A8

A10

A13

A21

*L

A11

A19

A12

A20

A14

A22

A15

A23

A16

A24

A17

A25

A18

A26

Row Address

NOTE : Column Address : Starting Address of the Register.

* L must be set to "Low".

* The device ignores any additional input of address cycles than reguired.

8

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

Product Introduction

The K9F1GXXX0M is a 1056Mbit(1,107,296,256 bit) memory organized as 65,536 rows(pages) by 2112x8(X8 device) or

1056x16(X16 device) columns. Spare 64(X8) or 32(X16) columns are located from column address of 2048~2111(X8 device) or

1024~1055(X16 device). A 2112-byte(X8 device) or 1056-word(X16 device) data register and a 2112-byte(X8 device) or 1056-

word(X16 device) cache register are serially connected to each other. Those serially connected registers are connected to memory

cell arrays for accommodating data transfer between the I/O buffers and memory cells during page read and page program opera-

tions. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a

different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 1081344 NAND cells

reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block

basis. The memory array consists of 1024 separately erasable 128K-byte(X8 device) or 64K-word(X16 device) blocks. It indicates

that the bit by bit erase operation is prohibited on the K9F1GXXX0M.

The K9F1GXXX0M has addresses multiplexed into 8 I/Os(X16 device case : lower 8 I/Os). This scheme dramatically reduces pin

counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and

data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch

Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some com-

mands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other

commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execu-

tion. The 128M byte(X8 device) or 64M word(X16 device) physical space requires 28(X8) or 27(X16) addresses, thereby requiring

four cycles for addressing: 2 cycles of column address, 2 cycles of row address, in that order. Page Read and Page Program need

the same four address cycles following the required command input. In Block Erase operation, however, only the two row address

cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific

commands of the K9F1GXXX0M.

The device provides cache program in a block. It is possible to write data into the cache registers while data stored in data registers

are being programmed into memory cells in cache program mode. The program performace may be dramatically improved by cache

program when there are lots of pages of data to be programmed.

The device embodies power-on auto-read feature which enables serial access of data of the 1st page without command and address

input after power-on.

In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another

page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and

data-input cycles are removed, system performance for solid-state disk application is significantly increased.

Table 1. Command Sets

Function

1st. Cycle

00h

2nd. Cycle

Acceptable Command during Busy

Read

30h

35h

-

Read for Copy Back

Read ID

00h

90h

Reset

FFh

80h

-

O

Page Program

Cache Program

Copy-Back Program

Block Erase

10h

15h

10h

D0h

-

80h

85h

60h

Random Data Input^*

Random Data Output^*

Read Status

85h

05h

E0h

70h

O

NOTE : 1. Random Data Input/Output can be executed in a page.

2. Command not specified in command sets table is not permitted to be entered to the device, which can raise erroneous operation.

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

9

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Unit

1.8V DEVICE

-0.6 to + 2.45

-0.2 to + 2.45

3.3V/2.65V DEVICE

-0.6 to + 4.6

VIN/OUT

VCC

Voltage on any pin relative to VSS

V

-0.6 to + 4.6

K9F1GXXX0M-XCB0

K9F1GXXX0M-XIB0

K9F1GXXX0M-XCB0

K9F1GXXX0M-XIB0

-10 to +125

Temperature Under

Bias

TBIAS

°C

-40 to +125

-65 to +150

5

Storage Temperature

TSTG

Ios

°C

Short Circuit Current

mA

NOTE :

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.

Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions

as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9F1GXXX0M-XCB0 :TA=0 to 70°C, K9F1GXXX0M-XIB0:TA=-40 to 85°C)

K9F1GXXQ0M(1.8V)

K9F1GXXD0M(2.65V)

K9F1GXXU0M(3.3V)

Parameter

Symbol

Unit

Min

1.70

0

Typ.

1.8

0

Max

1.95

0

Min

2.4

0

Typ.

2.65

0

Max

2.9

0

Min

2.7

0

Typ.

3.3

0

Max

3.6

0

Supply Voltage

VCC

VSS

V

10

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

K9F1GXXX0M

Parameter

Symbol

Test Conditions

1.8V

2.65V

3.3V

Unit

Min Typ Max Min Typ Max Min Typ Max

Page Read with

Operating Serial Access

tRC=50ns, CE=VIL

IOUT=0mA

ICC1

-

8

15

-

10

20

-

10

20

Current

Program

ICC2

ICC3

-

8

-

15

1

-

10

-

20

1

-

10

-

20

1

mA

Erase

Stand-by Current(TTL)

ISB1 CE=VIH, WP=PRE=0V/VCC

CE=VCC-0.2,

ISB2

Stand-by Current(CMOS)

-

10

50

-

10

50

-

10

50

WP=PRE=0V/VCC

mA

Input Leakage Current

Output Leakage Current

ILI

VIN=0 to Vcc(max)

-

±10

VCC

-

±10

-

±10

ILO

VOUT=0 to Vcc(max)

VCC

-0.4

VCC

Input High Voltage

VIH*

-

2.0

-

+0.3 -0.4

0.4 -0.3

+0.3

Input Low Voltage, All inputs VIL*

-

-0.3

0.5 -0.3

0.8

K9F1GXXQ0M :IOH=-100mA

Vcc

-0.1

VCCQ

V

Output High Voltage Level

Output Low Voltage Level

VOH K9F1GXXD0M :IOH=-100mA

K9F1GXXU0M :IOH=-400mA

-

0.4

-

2.4

-

-0.4

K9F1GXXQ0M :IOL=100uA

VOL K9F1GXXD0M :IOL=100mA

K9F1GXXU0M :IOL=2.1mA

-

0.1

-

0.4

-

K9F1GXXQ0M :VOL=0.1V

Output Low Current(R/B)

IOL(R/B)

3

4

3

4

8

10

mA

K9F1GXXD0M :VOL=0.1V

K9F1GXXU0M :VOL=0.4V

NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.

11

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

VALID BLOCK

Parameter

Symbol

Min

Typ.

Max

Unit

Valid Block Number

NVB

1004

-

1024

Blocks

NOTE :

1. The K9F1GXXX0M may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid

blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase

or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.

2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase

cycles.

AC TEST CONDITION

(K9F1GXXX0M-XCB0 :TA=0 to 70°C, K9F1GXXX0M-XIB0:TA=-40 to 85°C

K9F1GXXQ0M : Vcc=1.70V~1.95V, K9F1GXXD0M : Vcc=2.4V~2.9V , K9F1GXXU0M : Vcc=2.7V~3.6V unless otherwise noted)

Parameter

K9F1GXXQ0M

0V to Vcc

5ns

K9F1GXXD0M

0V to Vcc

5ns

K9F1GXXU0M

0.4V to 2.4V

5ns

Input Pulse Levels

Input Rise and Fall Times

Input and Output Timing Levels

Vcc/2

1.5V

K9F1GXXQ0M:Output Load (Vcc:1.8V +/-10%)

K9F1GXXD0M:Output Load (VccQ:2.65V +/-10%)1 TTL GATE and CL=30pF1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF

K9F1GXXU0M:Output Load (Vcc:3.0V +/-10%)

K9F1GXXU0M:Output Load (Vcc:3.3V +/-10%)

-

1 TTL GATE and CL=100pF

CAPACITANCE(TA=25°C, VCC=1.8V/2.65V/3.3V, f=1.0MHz)

Item

Symbol

Test Condition

Min

Max

Unit

pF

Input/Output Capacitance

Input Capacitance

CI/O

VIL=0V

-

10

CIN

VIN=0V

pF

NOTE : Capacitance is periodically sampled and not 100% tested.

MODE SELECTION

CLE

H

L

ALE

L

CE

L

WE

RE

H

WP

PRE

Mode

Command Input

X

Read Mode

Write Mode

H

L

H

X

Address Input(4clock)

Command Input

H

L

H

X

H

L

H

X

Address Input(4clock)

L

H

X

Data Input

L

H

X

Data Output

X

H

X

During Read(Busy)

During Program(Busy)

During Erase(Busy)

Write Protect

X

H

X

H

L

X⁽¹⁾

X

(2)

X

Stand-by

0V/VCC

NOTE : 1. X can be VIL or VIH.

2. WP and PRE should be biased to CMOS high or CMOS low for standby.

12

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

Program / Erase Characteristics

Parameter

Symbol

tPROG

Min

Typ

Max

700

4

Unit

ms

Program Time

-

300

Dummy Busy Time for Cache Program

tCBSY

3

-

ms

Main Array

Spare Array

-

cycles

ms

Number of Partial Program Cycles

in the Same Page

Nop

-

4

Block Erase Time

tBERS

2

3

NOTE : 1. Max. time of tCBSY depends on timing between internal program completion and data in

AC Timing Characteristics for Command / Address / Data Input

Min

Max

Parameter

Symbol

Unit

K9F1GXXQ0M K9F1GXXD0M K9F1GXXU0M K9F1GXXQ0M K9F1GXXD0M K9F1GXXU0M

CLE setup Time

CLE Hold Time

CE setup Time

CE Hold Time

tCLS

tCLH

tCS

0

10

0

10

0

-

ns

10

0

tCH

10

60

0

10

25⁽¹⁾

0

10

25⁽¹⁾

0

WE Pulse Width

ALE setup Time

ALE Hold Time

Data setup Time

Data Hold Time

Write Cycle Time

WE High Hold Time

tWP

tALS

tALH

tDS

10

20

10

80

20

10

20

10

45

15

10

20

10

45

15

tDH

tWC

tWH

NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.

AC Characteristics for Operation

Min

Max

Parameter

Symbol

Unit

K9F1GXXQ0M K9F1GXXD0M K9F1GXXU0M K9F1GXXQ0M K9F1GXXD0M K9F1GXXU0M

Data Transfer from Cell to Register

ALE to RE Delay

tR

tAR

-

10

20

60

-

10

20

25

-

25

ms

ns

10

20

25

-

CLE to RE Delay

tCLR

tRR

Ready to RE Low

-

RE Pulse Width

tRP

-

WE High to Busy

tWB

tRC

100

-

100

-

100

-

Read Cycle Time

80

-

50

-

50

-

RE Access Time

tREA

tCEA

tRHZ

tCHZ

tOH

60

75

30

20

-

30

45

30

20

-

30

45

30

20

-

CE Access Time

-

RE High to Output Hi-Z

CE High to Output Hi-Z

RE or CE High to Output hold

RE High Hold Time

Output Hi-Z to RE Low

WE High to RE Low

-

15

20

0

15

0

15

0

tREH

tIR

-

tWHR

60

-

Device Resetting Time

(Read/Program/Erase)

tRST

-

5/10/500⁽¹⁾5/10/500⁽¹⁾5/10/500⁽¹⁾

ms

NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.

13

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

NAND Flash Technical Notes

Invalid Block(s)

Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-

mation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality

level as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the perfor-

mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design

must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaran-

teed to be a valid block, does not require Error Correction up to 1K program/erase cycles.

Identifying Invalid Block(s)

All device locations are erased(FFh for X8, FFFFh for X16) except locations where the invalid block(s) information is written prior to

shipping. The invalid block(s) status is defined by the 1st byte(X8 device) or 1st word(X16 device) in the spare area. Samsung

makes sure that either the 1st or 2nd page of every invalid block has non-FFh(X8) or non-FFFFh(X16) data at the column address of

2048(X8 device) or 1024(X16 device). Since the invalid block information is also erasable in most cases, it is impossible to recover

the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original

invalid block information and create the invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of

the original invalid block information is prohibited.

Start

Set Block Address = 0

Increment Block Address

Check "FFh( or FFFFh)" at the column address

2048(X8 device) or 1024(X16 device)

of the 1st and 2nd page in the block

*

No

Check "FFh

or FFFFh" ?

Create (or update)

Invalid Block(s) Table

Yes

No

Last Block ?

Yes

End

Figure 3. Flow chart to create invalid block table.

14

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

NAND Flash Technical Notes (Continued)

Error in write or read operation

Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual

data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-

ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect

the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased

empty block and reprogramming the current target data and copying the rest of the replaced block.To improve the efficiency of mem-

ory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block

replacement. The said additional block failure rate does not include those reclaimed blocks.

Failure Mode

Detection and Countermeasure sequence

Erase Failure

Status Read after Erase --> Block Replacement

Status Read after Program --> Block Replacement

Read back ( Verify after Program) --> Block Replacement

or ECC Correction

Write

Read

Program Failure

Single Bit Failure

Verify ECC -> ECC Correction

: Error Correcting Code --> Hamming Code etc.

Example) 1bit correction & 2bit detection

ECC

Program Flow Chart

If ECC is used, this verification

operation is not needed.

Start

Write 80h

Write 00h

Write Address

Write 30h

Write Address

Write Data

Write 10h

Wait for tR Time

*

Fail

Read Status Register

Program Error

Verify Data

No

Pass

I/O 6 = 1 ?

or R/B = 1 ?

Program Completed

Yes

*

No

: If program operation results in an error, map out

the block including the page in error and copy the

target data to another block.

Program Error

I/O 0 = 0 ?

*

Yes

15

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

NAND Flash Technical Notes (Continued)

Erase Flow Chart

Read Flow Chart

Start

Write 00h

Start

Write 60h

Write Block Address

Write Address

Write 30h

Write D0h

Read Data

Read Status Register

ECC Generation

No

I/O 6 = 1 ?

or R/B = 1 ?

No

Verify ECC

Reclaim the Error

Yes

*

No

Yes

Erase Error

I/O 0 = 0 ?

Page Read Completed

Yes

Erase Completed

: If erase operation results in an error, map out

the failing block and replace it with another block.

*

Block Replacement

Block A

1st

{

(n-1)th

1

nth

an error occurs.

(page)

Buffer memory of the controller.

Block B

1st

2

{

(n-1)th

nth

(page)

* Step1

When an error happens in the nth page of the Block ’A’ during erase or program operation.

* Step2

Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’)

* Step3

Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’.

* Step4

Do not erase or program to Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.

16

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

NAND Flash Technical Notes (Continued)

Addressing for program operation

Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig-

nificant bit) pages of the block. Random page address programming is prohibited.

(64)

Page 63

Page 31

Page 63

Page 31

:

(1)

:

(32)

:

(3)

(2)

(1)

Page 2

Page 1

Page 0

(3)

(32)

(2)

Page 2

Page 1

Page 0

Data register

From the LSB page to MSB page

DATA IN: Data (1)

Data (64)

Ex.) Random page program (Prohibition)

DATA IN: Data (1)

Data (64)

17

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

System Interface Using CE don’t-care.

For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal

2112byte(X8 device) or 1056word(X16 device) data registers are utilized as separate buffers for this operation and the system

design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activat-

ing CE during the data-loading and serial access would provide significant savings in power consumption.

Figure 4. Program Operation with CE don’t-care.

CLE

CE don’t-care

CE

WE

ALE

I/Ox

80h

tCS

Address(4Cycles)

Data Input

10h

tCEA

tCH

CE

RE

CE

tREA

tWP

WE

out

I/O0~7

Figure 5. Read Operation with CE don’t-care.

CLE

CE

CE don’t-care

RE

ALE

tR

R/B

WE

I/Ox

Data Output(serial access)

00h

Address(4Cycle)

30h

18

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

NOTE

I/O

DATA

ADDRESS

Device

I/Ox

Data In/Out

~2112byte

~1056word

Col. Add1

A0~A7

Col. Add2

A8~A11

Row Add1

A12~A19

A11~A18

Row Add2

A20~A27

A19~A26

K9F1G08X0M(X8 device)

K9F1G16X0M(X16 device)

I/O 0 ~ I/O 7

I/O 0 ~ I/O 15

A0~A7

A8~A10

Command Latch Cycle

CLE

tCLH

tCLS

tCS

tCH

CE

tWP

WE

tALS

tALH

ALE

I/Ox

tDH

tDS

Command

K9F1G16X0M : I/O8~15 must be set to "0"

Address Latch Cycle

tCLS

CLE

tCS

tWC

CE

tWP

WE

tWH

tALH tALS

tWH

tALH tALS

tWH

tALH tALS

tALH

tDH

tALS

ALE

tDH

tDS

Col. Add2

Row Add1

Col. Add1

Row Add2

I/Ox

K9F1G16X0M : I/O8~15 must be set to "0"

19

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

Input Data Latch Cycle

tCLH

CLE

CE

tCH

tWC

tALS

ALE

tWP

WE

tWH

tDH

tDS

I/Ox

DIN final*

DIN 0

DIN 1

NOTES : DIN final means 2112(X8) or 1056(X16)

Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)

tCEA

CE

tCHZ*

tOH

tREH

tREA

tRP

RE

tRHZ*

tOH

I/Ox

Dout

tRC

tRR

R/B

NOTES : Transition is measured ±200mV from steady state voltage with load.

This parameter is sampled and not 100% tested.

20

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

Status Read Cycle

tCLR

CLE

tCLS

tCLH

tCS

CE

tCH

tWP

WE

RE

tCEA

tCHZ*

tOH

tWHR

tRHZ*

tOH

tDH

tREA

tDS

tIR*

I/Ox

Status Output

70h

K9F1G16X0M : I/O8~15 must be set to "0"

21

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

Read Operation

tCLR

CLE

CE

tWC

WE

ALE

RE

tWB

tAR

tRHZ

tOH

tR

tRC

tRR

Col. Add2 Row Add1 Row Add2

00h

Col. Add1

30h

Dout N

Dout N+1

Dout M

I/Ox

R/B

Column Address

Row Address

Busy

Read Operation(Intercepted by CE)

CLE

CE

WE

ALE

RE

tWB

tCHZ

tOH

tAR

tR

tRC

tRR

Row Add1 Row Add2

Dout N+2

00h

Col. Add1 Col. Add2

30h

Dout N

Dout N+1

I/Ox

R/B

Row Address

Column Address

Busy

22

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

23

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

Page Program Operation

CLE

CE

tWC

WE

tPROG

tWB

ALE

RE

Din

N

Din

M

Col. Add2 Row Add1 Row Add2

Co.l Add1

I/Ox

10h

80h

70h

I/O0

SerialData

Input Command

Program

Command

1 up to m Byte

Serial Input

Read Status

Command

Column Address

Row Address

R/B

I/O0=0 Successful Program

I/O0=1 Error in Program

X8 device : m = 2112byte

X16 device : m = 1056word

24

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

»

» »

»

25

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

»

» »

»

26

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

»

» »

»

» »

»

27

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

BLOCK ERASE OPERATION

CLE

CE

tWC

WE

tBERS

tWB

ALE

RE

I/Ox

Row Add1 Row Add2

60h

D0h

70h

I/O 0

Row Address

Busy

R/B

Auto Block Erase

Setup Command

Erase Command

I/O0=0 Successful Erase

Read Status I/O0=1 Error in Erase

Command

28

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

Read ID Operation

CLE

CE

WE

tAR

ALE

RE

tREA

Device

Code*

I/Ox

4th cyc.*

00h

ECh

XXh

90h

Read ID Command

Maker Code Device Code

Address. 1cycle

Device

Device Code*(2nd Cycle)

4th Cycle*

K9F1G08Q0M

K9F1G08D0M

K9F1G08U0M

K9F1G16Q0M

K9F1G16D0M

K9F1G16U0M

A1h

F1h

B1h

C1h

15h

55h

ID Defintition Table

90 ID : Access command = 90H

Description

1^stByte

2^ndByte

3^rdByte

4^thByte

Maker Code

Device Code

Don’t care

Page Size, Block Size, Spare Size, Organization,Serial access minimum

29

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

4th ID Data

ITEM

Description

I/O7

I/O6 I/O5 I/O4

I/O3

I/O2

I/O1 I/O0

1KB

2KB

Reserved

0

1

0

1

0

1

Page Size

(w/o redundant area )

64KB

0

1

0

1

0

1

Blcok Size

(w/o redundant area )

128KB

256KB

Reserved

Redundant Area Size

( byte/512byte)

8

16

0

1

x8

x16

0

1

Organization

50ns

25ns

Reserved

0

1

0

1

0

1

Serial Access minimum

30

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

Device Operation

PAGE READ

Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h and 30h to the com-

mand register along with four address cycles. In two consecutive read operations, the second one doesn’t need 00h command, which

four address cycles and 30h command initiates that operation.Two types of operations are available : random read, serial page read

The random read mode is enabled when the page address is changed. The 2112 bytes(X8 device) or 1056 words(X16 device) of

data within the selected page are transferred to the data registers in less than 25ms(tR). The system controller can detect the comple-

tion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be

read out in 50ns(1.8V device : 80ns) cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make

the device output the data starting from the selected column address up to the last column address.

The device may output random data in a page instead of the consecutive sequential data by writing random data output command.

The column address of next data, which is going to be out, may be changed to the address which follows random data output com-

mand. Random data output can be operated multiple times regardless of how many times it is done in a page.

Figure 6. Read Operation

CLE

CE

WE

ALE

tR

R/B

RE

I/Ox

00h

Address(4Cycle)

30h

Data Output(Serial Access)

Col Add1,2 & Row Add1,2

Data Field

Spare Field

31

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

Figure 7. Random Data Output In a Page

tR

R/B

RE

Address

4Cycles

Address

2Cycles

Data Output

E0h

I/Ox

00h

30h

05h

Col Add1,2 & Row Add1,2

Data Field

Spare Field

PAGE PROGRAM

The device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive

bytes up to 2112(X8 device) or words up to 1056(X16 device), in a single page program cycle. The number of consecutive partial

page programming operation within the same page without an intervening erase operation must not exceed 4 times for main array(X8

device:1time/512byte, X16 device:1time/256word) and 4 times for spare array(X8 device:1time/16byte ,X16 device:1time/8word).

The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which

up to 2112bytes(X8 device) or 1056words(X16 device) of data may be loaded into the data register, followed by a non-volatile pro-

gramming period where the loaded data is programmed into the appropriate cell.

The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address inputs and

then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data

input in a page. The column address of next data, which will be entered, may be changed to the address which follows random data

input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page.

The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the

serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and tim-

ings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the

Read Status Register command may be entered to read the status register. The system controller can detect the completion of a pro-

gram cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset

command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be

checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command

register remains in Read Status command mode until another valid command is written to the command register.

Figure 8. Program & Read Status Operation

tPROG

R/B

"0"

Pass

80h

Address & Data Input

I/O0

Fail

I/Ox

10h

70h

Col Add1,2 & Row Add1,2

Data

"1"

32

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

Figure 9. Random Data Input In a Page

tPROG

R/B

"0"

Pass

80h

Address & Data Input

I/O0

70h

I/Ox

85h

10h

Col Add1,2

Data

Col Add1,2 & Row Add1,2

Data

"1"

Fail

Cache Program

Cache Program is an extension of Page Program, which is executed with 2112byte(X8 device) or 1056word(X16 device) data regis-

ters, and is available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while data

stored in data register are programmed into memory cell.

After writing the first set of data up to 2112byte(X8 device) or 1056word(X16 device) into the selected cache registers, Cache Pro-

gram command (15h) instead of actual Page Program (10h) is inputted to make cache registers free and to start internal program

operation. To transfer data from cache registers to data registers, the device remains in Busy state for a short period of time(tCBSY)

and has its cache registers ready for the next data-input while the internal programming gets started with the data loaded into data

registers. Read Status command (70h) may be issued to find out when cache registers become ready by polling the Cache-Busy sta-

tus bit(I/O 6). Pass/fail status of only the previouse page is available upon the return to Ready state. When the next set of data is

inputted with the Cache Program command, tCBSY is affected by the progress of pending internal programming. The programming of

the cache registers is initiated only when the pending program cycle is finished and the data registers are available for the transfer of

data from cache registers. The status bit(I/O5) for internal Ready/Busy may be polled to identify the completion of internal program-

ming. If the system monitors the progress of programming only with R/B, the last page of the target programming sequence must be

progammed with actual Page Program command (10h).

Figure 10. Cache Program(available only within a block)

tPROG

tCBSY

R/B

Address &

Data Input

Address &

Data Input

Address &

Data Input*

Address &

Data Input

80h

70h

10h

80h

15h

80h

15h

Col Add1,2 & Row Add1,2

Data

Col Add1,2 & Row Add1,2

Data

Col Add1,2 & Row Add1,2

Data

Col Add1,2 & Row Add1,2

Data

33

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if

the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after com-

pletion of the previous cycle, which can be expressed as the following formula.

tPROG= Program time for the last page+ Program time for the ( last -1 )th page

- (Program command cycle time + Last page data loading time)

Copy-Back Program

The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory.

Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The ben-

efit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned

free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copy-

ing-program with the address of destination page. A read operation with "35h" command and the address of the source page moves

the whole 2112byte(X8 device) or 1056word(X16 device) data into the internal data buffer. As soon as the device returns to Ready

state, Page-Copy Data-input command (85h) with the address cycles of destination page followed may be written. The Program

Confirm command (10h) is required to actually begin the programming operation. Data input cycle for modifying a portion or multiple

distant portions of the source page is allowed as shown in Figure 12. "When there is a program-failure at Copy-Back operation,

error is reported by pass/fail status. But if the soure page has a bit error for charge loss, accumulated copy-back

operations could also accumulate bit errors. For this reason, two bit ECC is recommended for copy-back operation."

Figure 11. Page Copy-Back program Operation

tR

tPROG

R/B

I/Ox

Add.(4Cycles)

Pass

00h

35h

Add.(4Cycles)

10h

I/O0

Fail

85h

70h

Col. Add1,2 & Row Add1,2

Destination Address

Col. Add1,2 & Row Add1,2

Source Address

Figure 12. Page Copy-Back program Operation with Random Data Input

tPROG

tR

R/B

Add.(4Cycles)

Add.(2Cycles)

Col Add1,2

I/Ox

35h

Add.(4Cycles)

70h

00h

85h

Data

85h

Data

10h

Col. Add1,2 & Row Add1,2

Source Address

Col. Add1,2 & Row Add1,2

Destination Address

There is no limitation for the number of repetition.

34

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

BLOCK ERASE

The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup com-

mand(60h). Only address A18 to A27(X8) or A17 to A26(X16) is valid while A12 to A17(X8) or A11 to A16(X16) is ignored. The Erase

Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup

followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions.

At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When

the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.

Figure 13. Block Erase Operation

tBERS

R/B

"0"

Pass

60h

I/O0

Fail

70h

Address Input(2Cycle)

I/Ox

D0h

"1"

Block Add. : A12 ~ A27 (X8)

or A11 ~ A26 (X16)

READ STATUS

The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether

the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs

the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows

the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE

does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register

remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read

cycle, the read command(00h) should be given before starting read cycles.

Table2. Read Staus Register Definition

I/O No.

I/O 0

Page Program

Pass/Fail

Block Erase

Pass/Fail

Not use

Cache Prorgam

Pass/Fail(N)

Pass/Fail(N-1)

Not use

Read

Not use

Definition

Pass : "0"

"0"

Fail : "1"

I/O 1

Not use

I/O 2

Not use

I/O 3

Not Use

"0"

I/O 4

Not Use

"0"

I/O 5

Ready/Busy

Write Protect

Ready/Busy

Write Protect

True Ready/Busy

Ready/Busy

Write Protect

Ready/Busy

Write Protect

Busy : "0"

Protected:"0"

Ready : "1"

I/O 6

I/O 7

Not Protected:"1"

I/O 8~15

(X16 device

only)

Not use

Don’t -care

NOTE : 1. True Ready/Busy represents internal program operation status which is being executed in cache program mode.

2. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.

35

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

Read ID

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of

00h. Four read cycles sequentially output the manufacturer code(ECh), and the device code and XXh, 4th cycle ID, respectively. The

command register remains in Read ID mode until further commands are issued to it. Figure 14 shows the operation sequence.

Figure 14. Read ID Operation

tCLR

CLE

CE

tCEA

WE

ALE

RE

tAR

tWHR

Device

Code*

tREA

I/OX

90h

00h

Address. 1cycle

ECh

XXh

4th Cyc.*

Maker code

Device code

Device

Device Code*(2nd Cycle)

4th Cycle*

K9F1G08Q0M

K9F1G08D0M

K9F1G08U0M

K9F1G16Q0M

K9F1G16D0M

K9F1G16U0M

A1h

F1h

B1h

C1h

15h

55h

RESET

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random

read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no

longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and

the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation.If the device is

already in reset state a new reset command will be accepted by the command register. The R/B pin transitions to low for tRST after

the Reset command is written. Refer to Figure 15 below.

Figure 15. RESET Operation

tRST

R/B

I/OX

FFh

Table3. Device Status

After Power-up

After Reset

PRE status

High

First page data access is ready

Low

Waiting for next command

Operation Mode

00h command is latched

36

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

Power-On Auto-Read

The device is designed to offer automatic reading of the first page without command and address input sequence during power-on.

An internal voltage detector enables auto-page read functions when Vcc reaches about 1.8V. PRE pin controls activation of auto-

page read function. Auto-page read function is enabled only when PRE pin is tied to Vcc. Serial access may be done after power-on

without latency. Power-On Auto Read mode is available only on 3.3V device(K9F1GXXU0M).

Figure 15. Power-On Auto-Read (3.3V device only)

~ 1.8V

VCC

CLE

CE

WE

ALE

PRE

R/B

tR

RE

I/OX

1st

2nd

3rd

....

n th

37

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

READY/BUSY

The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random

read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis-

ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is

an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and

current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 16). Its value can be

determined by the following guidance.

Rp

ibusy

VCC

1.8V device - VOL : 0.1V, VOH : VCCq-0.1V

2.65V device - VOL : 0.4V, VOH : Vccq-0.4V

3.3V device - VOL : 0.4V, VOH : 2.4V

Ready Vcc

R/B

VOH

open drain output

C_L

VOL

Busy

tf

tr

GND

Device

Figure 16. Rp vs tr ,tf & Rp vs ibusy

38

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

@ Vcc = 1.8V, Ta = 25°C , C_L= 30pF

Ibusy

300n

3m

1.7

200n

100n

2m

1m

120

0.85

60

90

tr

30

0.57

1.7

0.43

1.7

2K

tf

1.7

4K

1K

3K

Rp(ohm)

@ Vcc = 2.65V, Ta = 25°C , C_L= 30pF

300n

3m

2.3

Ibusy

200n

100n

1.1

2m

1m

120

90

tr

60

30

0.75

2.3

0.55

tf

2.3

4K

1K

2K

3K

Rp(ohm)

@ Vcc = 3.3V, Ta = 25°C , C_L= 100pF

400

2.4

Ibusy

300n

3m

300

1.2

200n

100n

200

0.8

2m

1m

tr

100

3.6

0.6

3.6

2K

3.6

tf

4K

1K

3K

Rp value guidance

Rp(ohm)

VCC(Max.) - VOL(Max.)

1.85V

Rp(min, 1.8V part) =

=

IOL + SIL

3mA + SIL

VCC(Max.) - VOL(Max.)

2.5V

Rp(min, 2.65V part) =

Rp(min, 3.3V part) =

=

IOL + SIL

3mA + SIL

VCC(Max.) - VOL(Max.)

3.2V

IOL + SIL

8mA + SIL

where IL is the sum of the input currents of all devices tied to the R/B pin.

Rp(max) is determined by maximum permissible limit of tr

39

K9F1G08Q0M K9F1G16Q0M

K9F1G08D0M

K9F1G16D0M

K9F1G08U0M K9F1G16U0M

FLASH MEMORY

Data Protection & Power up sequence

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector

disables all functions whenever Vcc is below about 1.1V(1.8V device), 1.8V(2.65V device), 2V(3.3V device). WP pin provides hard-

ware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10ms is

required before internal circuit gets ready for any command sequences as shown in Figure 17. The two step command sequence for

program/erase provides additional software protection.

Figure 17. AC Waveforms for Power Transition

1.8V device : ~ 1.5V

2.65V device : ~ 2.0V

3.3V device : ~ 2.5V

1.8V device : ~ 1.5V

2.65V device : ~ 2.0V

3.3V device : ~ 2.5V

VCC

High

WP

WE

10ms

40

型号:	K9F1G16D0M-PCB0
是否Rohs认证：	符合
生命周期：	Obsolete
IHS 制造商：	SAMSUNG SEMICONDUCTOR INC
包装说明：	TSSOP, TSSOP48,.8,20
Reach Compliance Code：	compliant
风险等级：	5.84
最长访问时间：	30 ns
命令用户界面：	YES
数据轮询：	NO
JESD-30 代码：	R-PDSO-G48
内存密度：	1073741824 bit
内存集成电路类型：	FLASH
内存宽度：	16
部门数/规模：	1K
端子数量：	48
字数：	67108864 words
字数代码：	64000000
最高工作温度：	70 °C
最低工作温度：
组织：	64MX16
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP48,.8,20
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
页面大小：	1K words
并行/串行：	PARALLEL
电源：	2.7 V
认证状态：	Not Qualified
就绪/忙碌：	YES
部门规模：	64K
最大待机电流：	0.00005 A
子类别：	Flash Memories
最大压摆率：	0.02 mA
标称供电电压 (Vsup)：	2.7 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	DUAL
切换位：	NO

电子百科

产品导航

产品型号K9F1G08UOE-SCBO的概述

产品型号K9F1G16D0M的Datasheet PDF文件预览

K9F1G08UOE-SCBO相关产品

K9F1G08UOE-SCBO相关文章

IC37:专业IC行业平台