KA555D芯片引脚定义引脚图及功能IC贸易商引脚图技术参数-中国IC网-芯三七

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产品型号KA555D的概述

芯片KA555D的概述 KA555D是一款广泛使用的定时器集成电路，其设计基于经典的555定时器架构。该芯片因其多功能性和易于使用的特性，已成为电子工程师和爱好者的首选之一。作为一个多用途的定时器，KA555D可以用于多种应用，包括定时器、脉冲发生器以及振荡器等。其广泛的应用范围使得它在工业控制、信号发生以及音频应用中非常受欢迎。 KA555D采用双斜率输出，可工作于单稳态和双稳态模式。这使得用户能够根据需要选择不同的操作模式，从而实现丰富的功能。该芯片的设计使其在消费电子产品中具有极好的适用性，如定时开关、声音报警器等。芯片KA555D的详细参数 KA555D的关键参数如下： - 工作电压范围：4.5V至15V - 最大工作电流：200mA - 频率范围：从几赫兹到几千赫兹 - 温度范围：-55°C至+125°C - 输出电压范围：接近供应电压 - 耗电量：较低，适合长时间供电的应...

产品型号KA555D的Datasheet PDF文件预览

www.fairchildsemi.com

KA555

Single Timer

Features

Description

• High Current Drive Capability (200mA)

• Adjustable Duty Cycle

• Temperature Stability of 0.005%/°C

• Timing From Msec to Hours

The KA555 is a highly stable controller capable of

producing accurate timing pulses. With monos table

operation, the time delay is controlled by one external

resistor and one capacitor. With astable operation, the

frequency and duty cycle are accurately controlled with two

external resistors and one capacitor.

• Turn Off Time Less Than 2Msec

Applications

8-DIP

• Precision Timing

• Pulse Generation

• Time Delay Generation

• Sequential Timing

8-SOP

Internal Block Diagram

Vcc

GND

Comp.

Discharging Tr.

Trigger

Discharge

Threshold

OutPut

Stage

Output

F/F

Comp.

Control

Voltage

Reset

Vref

Rev. 1.0.2

KA555

Absolute Maximum Ratings (T = 25°C)

Parameter

Symbol

Value

Unit

Supply Voltage

Lead Temperature (Soldering 10sec)

Power Dissipation

300

600

°C

LEAD

Operating Temperature Range

KA555/KA555I

0 ~ +70 / -40 ~ +85

- 65 ~ +150

°C

OPR

Storage Temperature Range

STG

KA555

Electrical Characteristics

(T = 25°C, V

= 5 ~ 15V, unless otherwise specified)

Parameter

Symbol

Conditions

Min.

Typ. Max.

Unit

Supply Voltage

4.5

= 5V, R = ∞

Supply Current *¹(Low Stable)

= 15V, R = ∞

7.5

Timing Error *²(Monos Table)

Initial Accuracy

Drift with Temperature

Drift with Supply Voltage

ACCUR

∆t/∆T

∆t/∆V

1.0

0.1

3.0

0.5

ppm/°C

%/V

R = 1KΩ to100KΩ

C = 0.1µF

Timing Error *²(Astable)

Initial Accuracy

Drift with Temperature

Drift with Supply Voltage

ACCUR

∆t/∆T

∆t/∆V

R = 1KΩ to 100KΩ

2.25

150

0.3

ppm/°C

%/V

C = 0.1µF

= 15V

= 5V

= 15 V

= 5V

9.0

2.6

10.0

3.33

10.0

3.33

0.1

11.0

4.0

Control Voltage

Threshold Voltage

Threshold Current *³

Trigger Voltage

0.25

2.2

5.6

2.0

1.0

0.4

µA

= 5V

= 15V

= 0V

1.1

4.5

1.67

Trigger Current

Reset Voltage

Reset Current

0.01

0.7

µA

0.4

RST

0.1

= 15V

= 10mA

= 50mA

0.06

0.3

0.25

0.75

SINK

Low Output Voltage

High Output Voltage

= 5V

= 5mA

SINK

0.05

0.35

= 15V

= 200mA

= 100mA

12.5

SOURCE

12.75 13.3

= 5V

= 100mA

2.75

3.3

100

SOURCE

Rise Time of Output

Fall Time of Output

Discharge Leakage Current

100

LKG

Notes:

1. Supply current when output is high is typically 1mA less at V

= 5V

2. Tested at V

= 5.0V and V

= 15V

3. This will determine maximum value of R + R for 15V operation, the max. total R = 20MΩ, and for 5V operation the max. total

R = 6.7MΩ

KA555

Application Information

Table1 below is the basic operating table of 555 timer:

Table 1. Basic Operating Table

Threshold Voltage

Trigger Voltage

Discharging Tr.

(Pin7)

Reset(Pin4)

Output(Pin3)

(V )(Pin6)

(V )(Pin2)

Don't care

Low

High

Low

> 2Vcc / 3

Vcc / 3 < V < 2 Vcc / 3 Vcc / 3 < V < 2 Vcc / 3

< Vcc / 3

High

OFF

When the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold voltage or

the trigger voltage. Only when the high signal is applied to the reset terminal, timer's output changes according to threshold

voltage and trigger voltage.

When the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal discharge Tr.

turns on, lowering the threshold voltage to below 1/3 of the supply voltage. During this time, the timer output is maintained

low. Later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply voltage, the timer's internal

discharge Tr. turns off, increasing the threshold voltage and driving the timer output again at high.

1. Monos Table Operation

+Vcc

10²

10¹

10⁰

RESET

Vcc

Trigger

DISCH

TRIG

OUT

THRES

CONT

10^-1

10^-2

10^-3

GND

10^-5

10^-4

10^-3

10^-2

10^-1

10⁰

10¹

10²

Time Delay(s)

Figure 2. Resistance and Capacitance vs.

Time delay(t )

Figure 1. Monoatable Circuit

Figure 3. Waveforms of Monostable Operation

KA555

Figure 1 illustrates a monos table circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage falls

below Vcc/3. When the trigger pulse voltage applied to the #2 pin falls below Vcc/3 while the timer output is low, the timer's

internal flip-flop turns the discharging Tr. off and causes the timer output to become high by charging the external capacitor

C1and setting the flip-flop output at the same time.

The voltage across the external capacitor C1, V increases exponentially with the time constant t=R *C and reaches 2Vcc/3

at td=1.1R *C. Hence, capacitor C1 is charged through resistor R . The greater the time constant R C, the longer it takes

for the V to reach 2Vcc/3. In other words, the time constant R C controls the output pulse width.

When the applied voltage to the capacitor C1 reaches 2Vcc/3, the comparator on the trigger terminal resets the flip-flop,

turning the discharging Tr. on. At this time, C1 begins to discharge and the timer output converts to low.

In this way, the timer operating in monos table repeats the above process. Figure 2 shows the time constant relationship based

on R and C. Figure 3 shows the general waveforms during monos table operation.

It must be noted that, for normal operation, the trigger pulse voltage needs to maintain a minimum of Vcc/3 before the timer

output turns low. That is, although the output remains unaffected even if a different trigger pulse is applied while the output is

high, it may be affected and the waveform not operate properly if the trigger pulse voltage at the end of the output pulse

remains at below Vcc/3. Figure 4 shows such timer output abnormality.

Figure 4. Waveforms of Monos table Operation (abnormal)

2. Astable Operation

+Vcc

100

(R_A+2R_B)

RESET

Vcc

DISCH

TRIG

OUT

0.1

THRES

CONT

0.01

GND

1E-3

100m

100

10k

100k

Frequency(Hz)

Figure 6. Capacitance and Resistance vs. Frequency

Figure 5. Astable Circuit

KA555

Figure 7. Waveforms of Astable Operation

An astable timer operation is achieved by adding resistor R to Figure 1 and configuring as shown on Figure 5. In astable

operation, the trigger terminal and the threshold terminal are connected so that a self-trigger is formed, operating as a multi

vibrator. When the timer output is high, its internal discharging Tr. turns off and the V increases by exponential

function with the time constant (R +R )*C.

When the V , or the threshold voltage, reaches 2Vcc/3, the comparator output on the trigger terminal becomes high,

resetting the F/F and causing the timer output to become low. This in turn turns on the discharging Tr. and the C1 discharges

through the discharging channel formed by R and the discharging Tr. When the V falls below Vcc/3, the comparator

output on the trigger terminal becomes high and the timer output becomes high again. The discharging Tr. turns off and the

rises again.

In the above process, the section where the timer output is high is the time it takes for the V to rise from Vcc/3 to 2Vcc/3,

and the section where the timer output is low is the time it takes for the V to drop from 2Vcc/3 to Vcc/3. When timer output

is high, the equivalent circuit for charging capacitor C1 is as follows:

R_A

R_B

Vcc

Vc1(0-)=Vcc/3

– V(0-)

(1)

(2)

−−−−−−− −−−−−−−−−−−−−−−−−−

R + R

(0+) = V

⁄ 3

- –

−−−−−−−−−−−−−−−−−−−−−−

(R + R )C1

(t) = V

1 – −e

(3)

Since the duration of the timer output high state(t ) is the amount of time it takes for the V (t) to reach 2Vcc/3,

KA555

- –

−−−−−−−−−−−−−−−−−−−−−−

(R + R )C1

(t) = −V

1 – −e

= V

(4)

= C (R + R )In2 = 0.693(R + R )C

(5)

The equivalent circuit for discharging capacitor C1 when timer output is low as follows:

R_B

V_C1(0-)=2Vcc/3

R_D

+ R

+ −−−−−−−−−−−−−V

= 0

(6)

(7)

−−−−−−−−

-−−−−−−−−−−−−−−−−−−−−−−

(R + R )C1

(t) = −V

Since the duration of the timer output low state(t ) is the amount of time it takes for the V (t) to reach Vcc/3,

−−−−−−−−−−−−−−−−−−−−−−

(R + R )C1

= −V

−V

(8)

= C (R + R )In2 = 0.693(R + R )C

(9)

Since R is normally R >> R although related to the size of discharging Tr.,

t_L=0.693R C

(10)

B 1

Consequently, if the timer operates in astable, the period is the same with

'T=t +t =0.693(RA+R )C +0.693R C =0.693(R +2R )C ' because the period is the sum of the charge time and discharge

B 1

time. And since frequency is the reciprocal of the period, the following applies.

−

1.44

frequency,

f =

(11)

−−−−−−−−−−−−−−−−−−−−−−−−

(R + 2R )C

3. Frequency divider

By adjusting the length of the timing cycle, the basic circuit of Figure 1 can be made to operate as a frequency divider. Figure

8. illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle.

KA555

Figure 8. Waveforms of Frequency Divider Operation

4. Pulse Width Modulation

The timer output waveform may be changed by modulating the control voltage applied to the timer's pin 5 and changing the

reference of the timer's internal comparators. Figure 9. illustrates the pulse width modulation circuit.

When the continuous trigger pulse train is applied in the monos table mode, the timer output width is modulated according to

the signal applied to the control terminal. Sine wave as well as other waveforms may be applied as a signal to the control

terminal. Figure 10 shows an example of pulse width modulation waveform.

+Vcc

RESET

Vcc

Trigger

Output

DISCH

TRIG

THRES

CONT

OUT

Input

GND

Figure 9. Circuit for Pulse Width Modulation

Figure 10. Waveforms of Pulse Width Modulation

5. Pulse Position Modulation

If the modulating signal is applied to the control terminal while the timer is connected for astable operation as in Figure 11, the

timer becomes a pulse position modulator.

In the pulse position modulator, the reference of the timer's internal comparators is modulated which in turn modulates the

timer output according to the modulation signal applied to the control terminal.

Figure 12 illustrates a sine wave for modulation signal and the resulting output pulse position modulation : however, any wave

shape could be used.

KA555

+Vcc

Vcc

RESET

DISCH

TRIG

THRES

CONT

Output

OUT

Modulation

GND

Figure 12. Waveforms of pulse position modulation

Figure 11. Circuit for Pulse Position Modulation

6. Linear Ramp

When the pull-up resistor RA in the monos table circuit shown in Figure 1 is replaced with constant current source, the V

increases linearly, generating a linear ramp. Figure 13 shows the linear ramp generating circuit and Figure 14 illustrates the

generated linear ramp waveforms.

+Vcc

RESET

Vcc

DISCH

TRIG

OUT

THRES

CONT

Output

GND

Figure 14. Waveforms of Linear Ramp

In Figure 13, current source is created by PNP transistor Q1 and resistor R1, R2, and R .

Figure 13. Circuit for Linear Ramp

– V

(12)

−−−−−−−−−−−−−−−−

Here, V

E is

= V

+ −−−−−−−−−−−−−V

(13)

+ R

For example, if Vcc=15V, R =20kΩ, R1=5kW, R2=10kΩ, and V =0.7V,

V =0.7V+10V=10.7V

Ic=(15-10.7)/20k=0.215mA

When the trigger is started in a timer configured as shown in Figure 13, the current flowing to capacitor C1 becomes a constant

current generated by PNP transistor and resistors.

KA555

Hence, the V is a linear ramp function as shown in Figure 14. The gradient S of the linear ramp function is defined as

follows:

p – p

S =

(14)

−−−−−−−−−

Here the Vp-p is the peak-to-peak voltage.

If the electric charge amount accumulated in the capacitor is divided by the capacitance, the V comes out as follows:

V=Q/C

(15)

The above equation divided on both sides by T gives us

−−

Q ⁄ T

−−−−−−−

(16)

and may be simplified into the following equation.

S=I/C (17)

In other words, the gradient of the linear ramp function appearing across the capacitor can be obtained by using the constant

current flowing through the capacitor.

If the constant current flow through the capacitor is 0.215mA and the capacitance is 0.02uF, the gradient of the ramp function

at both ends of the capacitor is S=0.215m/0.022u=9.77V/ms.

KA555

Mechanical Dimensions

Package

Dimensions in millimeters

8-DIP

6.40 ±0.20

0.252 ±0.008

3.30 ±0.30

0.130 ±0.012

5.08

MAX

0.200

7.62

3.40 ±0.20

0.134 ±0.008

0.300

0.33

MIN

0.013

KA555

Mechanical Dimensions ^(Continued)

Package

Dimensions in millimeters

8-SOP

0.1~0.25

MIN

0.004~0.001

1.55 ±0.20

0.061 ±0.008

6.00 ±0.30

0.236 ±0.012

1.80

0.071

MAX

3.95 ±0.20

0.156 ±0.008

5.72

0.225

0.50 ±0.20

0.020 ±0.008

KA555

Ordering Information

Product Number

KA555

Package

8-DIP

Operating Temperature

0 ~ +70°C

KA555D

8-SOP

8-DIP

KA555I

-40 ~ +85°C

KA555ID

8-SOP

KA555

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY

PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER

DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES

OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR

CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, and (c) whose failure to

perform when properly used in accordance with

instructions for use provided in the labeling, can be

reasonably expected to result in a significant injury of the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

7/16/02 0.0m 001

Stock#DSxxxxxxxx

2002 Fairchild Semiconductor Corporation

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KA555D产品参数

型号:	KA555D
是否无铅：	不含铅
生命周期：	Active
零件包装代码：	SOIC
包装说明：	SOP-8
针数：	8
Reach Compliance Code：	unknown
风险等级：	5.7
其他特性：	CAN ALSO OPERATE FROM A 15V NOMINAL SUPPLY
模拟集成电路 - 其他类型：	PULSE; RECTANGULAR
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3
长度：	4.92 mm
湿度敏感等级：	1
功能数量：	1
端子数量：	8
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
认证状态：	COMMERCIAL
座面最大高度：	1.8 mm
最大供电电压 (Vsup)：	16 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
温度等级：	COMMERCIAL
端子面层：	MATTE TIN
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.95 mm
Base Number Matches：	1

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