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KH25L8006E

KH25L1606E

KH25L8006E, KH25L1606E

DATASHEET

P/N: PM1591

REV. 1.0, SEP. 03, 2010

1

KH25L8006E

KH25L1606E

Contents

FEATURES ..................................................................................................................................................................5

GENERAL DESCRIPTION .........................................................................................................................................6

PIN CONFIGURATIONS .............................................................................................................................................7

PIN DESCRIPTION......................................................................................................................................................7

BLOCK DIAGRAM.......................................................................................................................................................8

MEMORY ORGANIZATION.........................................................................................................................................9

Table 1-1. Memory Organization (8Mb)............................................................................................................... 9

Table 1-2. Memory Organization (16Mb)............................................................................................................. 9

DEVICE OPERATION................................................................................................................................................10

Figure 1.

Serial Modes Supported....................................................................................................... 10

DATA PROTECTION.................................................................................................................................................. 11

Table 2. Protected Area Sizes ............................................................................................................................ 12

Table 3. 512 bit Secured OTP Deﬁnition ........................................................................................................... 13

HOLD FEATURES .....................................................................................................................................................14

Figure 2. Hold Condition Operation

........................................................................................................ 14

COMMAND DESCRIPTION.......................................................................................................................................15

Table 4. COMMAND DEFINITION ..................................................................................................................... 15

(1) Write Enable (WREN)...................................................................................................................................16

(2) Write Disable (WRDI)....................................................................................................................................16

(3) Read Status Register (RDSR) ...................................................................................................................... 16

(4) Write Status Register (WRSR)...................................................................................................................... 17

Table 5. Protection Modes..................................................................................................................................18

(5) Read Data Bytes (READ) ............................................................................................................................. 19

(6) Read Data Bytes at Higher Speed (FAST_READ) .......................................................................................19

(7) Dual Output Mode (DREAD)......................................................................................................................... 19

(8) Sector Erase (SE).........................................................................................................................................19

(9) Block Erase (BE)...........................................................................................................................................20

(10) Chip Erase (CE)..........................................................................................................................................20

(11) Page Program (PP).....................................................................................................................................20

(12) Deep Power-down (DP).............................................................................................................................. 21

(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES) ............................................. 21

(14) Read Identiﬁcation (RDID).......................................................................................................................... 22

(15) Read Electronic Manufacturer ID & Device ID (REMS)..............................................................................22

Table 6. ID DEFINITIONS .................................................................................................................................22

(16) Enter Secured OTP (ENSO)....................................................................................................................... 22

(17) Exit Secured OTP (EXSO).......................................................................................................................... 22

(18) Read Security Register (RDSCUR) ............................................................................................................ 23

Table 7. SECURITY REGISTER DEFINITION................................................................................................... 23

P/N: PM1591

REV. 1.0, SEP. 03, 2010

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KH25L8006E

KH25L1606E

(19) Write Security Register (WRSCUR)............................................................................................................ 23

POWER-ON STATE...................................................................................................................................................24

ELECTRICAL SPECIFICATIONS..............................................................................................................................25

ABSOLUTE MAXIMUM RATINGS..................................................................................................................... 25

Figure 3.Maximum Negative Overshoot Waveform ...........................................................................................25

CAPACITANCE TA = 25 C, f = 1.0 MHz............................................................................................................. 25

°

Figure 4. Maximum Positive Overshoot Waveform............................................................................................25

Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL..............................................................26

Figure 6. OUTPUT LOADING ........................................................................................................................... 26

Table 8. DC CHARACTERISTICS...................................................................................................................... 27

Table 9. AC CHARACTERISTICS...................................................................................................................... 28

Timing Analysis........................................................................................................................................................29

Figure 7. Serial Input Timing .............................................................................................................................. 29

Figure 8. Output Timing......................................................................................................................................29

Figure 9. Hold Timing .........................................................................................................................................30

Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 ............................................... 30

Figure 11. Write Enable (WREN) Sequence (Command 06) .............................................................................31

Figure 12. Write Disable (WRDI) Sequence (Command 04)..............................................................................31

Figure 13. Read Status Register (RDSR) Sequence (Command 05) ................................................................32

Figure 14. Write Status Register (WRSR) Sequence (Command 01)...............................................................32

Figure 15. Read Data Bytes (READ) Sequence (Command 03) ......................................................................32

Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B)................................................... 33

Figure 17. Dual Output Read Mode Sequence (Command 3B).........................................................................34

Figure 18. Sector Erase (SE) Sequence (Command 20)..................................................................................34

Figure 19. Block Erase (BE) Sequence (Command D8)...................................................................................34

Figure 20. Chip Erase (CE) Sequence (Command 60 or C7)...........................................................................35

Figure 21. Page Program (PP) Sequence (Command 02)................................................................................35

Figure 22. Deep Power-down (DP) Sequence (Command B9).........................................................................36

Figure 23. Release from Deep Power-down (RDP) Sequence (Command AB) ............................................... 36

Figure 24. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)3 6

Figure 25. Read Identiﬁcation (RDID) Sequence (Command 9F)......................................................................37

Figure 26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF).................... 37

Figure 27. Read Security Register (RDSCUR) Sequence (Command 2B)........................................................38

Figure 28. Write Security Register (WRSCUR) Sequence (Command 2F) .......................................................38

Figure 29. Power-up Timing ............................................................................................................................... 39

Table 10. Power-Up Timing ............................................................................................................................... 39

OPERATING CONDITIONS.......................................................................................................................................40

Figure 30. AC Timing at Device Power-Up......................................................................................................... 40

Figure 31. Power-Down Sequence .................................................................................................................... 41

P/N: PM1591

REV. 1.0, SEP. 03, 2010

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KH25L8006E

KH25L1606E

ERASE AND PROGRAMMING PERFORMANCE....................................................................................................42

DATA RETENTION ....................................................................................................................................................42

LATCH-UP CHARACTERISTICS..............................................................................................................................42

ORDERING INFORMATION......................................................................................................................................43

PART NAME DESCRIPTION.....................................................................................................................................44

PACKAGE INFORMATION........................................................................................................................................45

P/N: PM1591

REV. 1.0, SEP. 03, 2010

4

KH25L8006E

KH25L1606E

8M-BIT [x 1 / x 2] CMOS SERIAL FLASH

16M-BIT [x 1 / x 2] CMOS SERIAL FLASH

FEATURES

GENERAL

• Single Power Supply Operation

- 2.7 to 3.6 volt for read, erase, and program operations

• Serial Peripheral Interface compatible -- Mode 0 and Mode 3

• 8M: 8,388,608 x 1 bit structure or 4,194,304 x 2 bits (Dual Output mode) structure

16M: 16,777,216 x 1 bit structure or 8,388,608 x 2 bits (Dual Output mode) structure

• 256 Equal Sectors with 4K byte each (8Mb)

512 Equal Sectors with 4K byte each (16Mb)

- Any Sector can be erased individually

• 16 Equal Blocks with 64K byte each (8Mb)

32 Equal Blocks with 64K byte each (16Mb)

- Any Block can be erased individually

• Program Capability

- Byte base

- Page base (256 bytes)

• Latch-up protected to 100mA from -1V to Vcc +1V

PERFORMANCE

• High Performance

- Fast access time: 86MHz serial clock

- Serial clock of Dual Output mode : 80MHz

- Fast program time: 1.4ms(typ.) and 5ms(max.)/page

- Byte program time: 9us (typical)

- Fast erase time: 60ms(typ.) /sector ; 0.7s(typ.) /block

• Low Power Consumption

- Low active read current: 16Mb: 25mA(max.) at 86MHz; 8Mb: 12mA(max.) at 86MHz

- Low active programming current: 20mA (max.)

- Low active erase current: 20mA (max.)

- Low standby current: 25uA (max.)

- Deep power-down mode 5uA (typical)

• Typical 100,000 erase/program cycles

• 20 years of data retention

SOFTWARE FEATURES

• Input Data Format

- 1-byte Command code

• Advanced Security Features

- Block lock protection

The BP3-BP0(16Mb) ; BP2-BP0(8Mb) status bit deﬁnes the size of the area to be software protection against

program and erase instructions

- Additional 512 bit secured OTP for unique identiﬁer

• Auto Erase and Auto Program Algorithm

Automatically erases and veriﬁes data at selected sector

Automatically programs and veriﬁes data at selected page by an internal algorithm that automatically times the

program pulse widths (Any page to be programed should have page in the erased state ﬁrst)

-

P/N: PM1591

REV. 1.0, SEP. 03, 2010

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KH25L8006E

KH25L1606E

• Status Register Feature

• Electronic Identiﬁcation

JEDEC 1-byte manufacturer ID and 2-byte device ID

- RES command for 1-byte Device ID

-

- REMS commands for 1-byte manufacturer ID and 1-byte device ID

HARDWARE FEATURES

• PACKAGE

8-pin SOP (200mil)

8-pin PDIP (300mil)

- All Pb-free devices are RoHS Compliant

-

GENERAL DESCRIPTION

The device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus.

The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access

to the device is enabled by CS# input.

When it is in Dual Output read mode, the SI and SO pins become SIO0 and SIO1 pins for data output.

The device provides sequential read operation on whole chip.

After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the speci-

ﬁed page or sector/block locations will be executed. Program command is executed on byte basis, or page basis,

or word basis for Continuously program mode, and erase command is executes on sector, or block, or whole chip

basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read

command can be issued to detect completion status of a program or erase operation via WIP bit.

Advanced security features enhance the protection and security functions, please see security features section for

more details.

When the device is not in operation and CS# is high, it is put in standby mode.

The device utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after typical

100,000 program and erase cycles.

P/N: PM1591

REV. 1.0, SEP. 03, 2010

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KH25L8006E

KH25L1606E

PIN DESCRIPTION

PIN CONFIGURATIONS

8-PIN SOP (200mil)

SYMBOL DESCRIPTION

CS#

Chip Select

Serial Data Input (for 1 x I/O)/ Serial Data

Input & Output (for Dual Output mode)

Serial Data Output (for 1 x I/O)/ Serial Data

Output (for Dual Output mode)

SI/SIO0

1

2

3

4

CS#

SO/SIO1

WP#

VCC

8

7

6

5

HOLD#

SCLK

SO/SIO1

GND

SI/SIO0

SCLK Clock Input

WP# Write protection

Hold, to pause the device without

deselecting the device

HOLD#

VCC

+ 3.3V Power Supply

8-PIN PDIP (300mil)

GND Ground

1

2

3

4

VCC

CS#

SO/SIO1

WP#

8

7

6

5

HOLD#

SCLK

SI/SIO0

GND

P/N: PM1591

REV. 1.0, SEP. 03, 2010

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KH25L8006E

KH25L1606E

BLOCK DIAGRAM

Address

Generator

Memory Array

Page Buffer

Data

Register

SI/SIO0

Y-Decoder

SO/SIO1

SRAM

Buffer

Sense

Amplifier

CS#,

WP#,

HOLD#

Mode

Logic

State

Machine

HV

Generator

SCLK

Clock Generator

Output

Buffer

P/N: PM1591

REV. 1.0, SEP. 03, 2010

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KH25L8006E

KH25L1606E

MEMORY ORGANIZATION

Table 1-1. Memory Organization (8Mb)

Table 1-2. Memory Organization (16Mb)

Block

Sector

255

:

Address Range

0FF000h 0FFFFFh

Block

Sector

511

:

Address Range

1FF000h 1FFFFFh

15

:

31

:

240

239

:

0F0000h

0EF000h

:

0F0FFFh

0EFFFFh

:

496

495

:

1F0000h

1EF000h

:

1F0FFFh

1EFFFFh

:

14

30

224

0E0000h

0E0FFFh

480

1E0000h

1E0FFFh

:

15

:

00F000h

:

00FFFFh

:

15

:

00F000h

:

00FFFFh

:

3

2

1

0

003000h

002000h

001000h

000000h

003FFFh

002FFFh

001FFFh

000FFFh

3

2

1

0

003000h

002000h

001000h

000000h

003FFFh

002FFFh

001FFFh

000FFFh

0

P/N: PM1591

REV. 1.0, SEP. 03, 2010

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KH25L8006E

KH25L1606E

DEVICE OPERATION

1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-

eration.

2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode

until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. The CS# falling time needs to

follow tCHCL spec.

3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until

next CS# rising edge. The CS# rising time needs to follow tCLCH spec.

4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK.

The difference of Serial mode 0 and mode 3 is shown in Figure 1.

5. For the following instructions:RDID, RDSR, RDSCUR, READ, FAST_READ, DREAD, RES, and REMS the shift-

ed-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS#

can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP, DP, ENSO, EXSO,and

WRSCUR, the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not

executed.

6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect-

ed and not affect the current operation of Write Status Register, Program, Erase.

Figure 1.

Serial Modes Supported

CPOL CPHA

shift in

shift out

SCLK

(Serial mode 0)

0

1

0

1

(Serial mode 3)

SI

MSB

SO

MSB

Note:

CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not

transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is

supported.

P/N: PM1591

REV. 1.0, SEP. 03, 2010

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KH25L8006E

KH25L1606E

DATA PROTECTION

The device is designed to offer protection against accidental erasure or programming caused by spurious system

level signals that may exist during power transition. During power up the device automatically resets the state ma-

chine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only

occurs after successful completion of speciﬁc command sequences. The device also incorporates several features

to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.

•

Valid command length checking: The command length will be checked whether it is at byte base and completed

on byte boundary.

• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before

other command to change data. The WEL bit will return to reset stage under following situation:

- Power-up

- Write Disable (WRDI) command completion

- Write Status Register (WRSR) command completion

- Page Program (PP) command completion

- Sector Erase (SE) command completion

- Block Erase (BE) command completion

- Chip Erase (CE) command completion

•

Deep Power Down Mode: By entering deep power down mode, the ﬂash device also is under protected from

writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig-

nature command (RES).

Advanced Security Features: there are some protection and security features which protect content from inad-

vertent write and hostile access.

I. Block lock protection

- The Software Protected Mode (SPM):

KH25L8006E: use (BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The proected area

deﬁnition is shown as table of "Protected Area Sizes", the protected areas are more ﬂexible which may protect

various area by setting value of BP0-BP2 bits.

KH25L1606E: use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The proect-

ed area deﬁnition is shown as table of "Protected Area Sizes", the protected areas are more ﬂexible which may

protect various area by setting value of BP0-BP3 bits.

Please refer to table of "protected area sizes".

- The Hardware Proteced Mode (HPM) uses WP# to protect the KH25L8006E:BP2-BP0 / KH25L1606E:BP3-

BP0 bits and SRWD bit.

P/N: PM1591

REV. 1.0, SEP. 03, 2010

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KH25L1606E

Table 2. Protected Area Sizes

Status bit

Protect Level

BP2

0

BP1

0

BP0

0

KH25L8006E (8Mb)

0 (none)

0

1

1 (1block, block 15th)

2 (2blocks, block 14th-15th)

3 (3blocks, block 12th-15th)

4 (4blocks, block 8th-15th)

5 (All)

0

1

0

1

0

1

0

1

0

6 (All)

1

7 (All)

Status bit

Protect Level

BP3

BP2

BP1

BP0

KH25L1606E (16Mb)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0 (none)

0

1

0

1

0

1

0

1

0

1

0

1

1 (1block, block 31th)

2 (2blocks, block 30th-31th)

3 (4blocks, block 28th-31th)

4 (8blocks, block 24th-31th)

5 (16blocks, block 16th-31th)

6 (32blocks, all)

7 (32blocks, all)

8 (32blocks, all)

9 (32blocks, all)

10 (16blocks, block 0th-15th)

11 (24blocks, block 0th-23th)

12 (28blocks, block 0th-27th)

13 (30blocks, block 0th-29th)

14 (31blocks, block 0th-30th)

15 (32blocks, all)

P/N: PM1591

REV. 1.0, SEP. 03, 2010

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KH25L8006E

KH25L1606E

II. Additional 512 bit secured OTP for unique identiﬁer: to provide 512 bit one-time program area for setting

device unique serial number - Which may be set by factory or system customer. Please refer to table 3. 512 bit-

secured OTP deﬁnition.

- Security register bit 0 indicates whether the chip is locked by factory or not.

- To program the 512 bit secured OTP by entering 512 bit secured OTP mode (with ENSO command), and going

through normal program procedure, and then exiting 512 bit secured OTP mode by writing EXSO command.

- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)

command to set customer lock-down bit1 as "1". Please refer to table of "security register deﬁnition" for security

register bit deﬁnition and table of "512 bit secured OTP deﬁnition" for address range deﬁnition.

- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 512 bit se-

cured OTP mode, array access is not allowed.

Table 3. 512 bit Secured OTP Deﬁnition

Address range

xxxx00~xxxx0F

xxxx10~xxxx3F

Size

Standard Factory Lock

ESN (electrical serial number)

N/A

Customer Lock

128-bit

384-bit

Determined by customer

P/N: PM1591

REV. 1.0, SEP. 03, 2010

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HOLD FEATURES

HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the

operation of write status register, programming, or erasing in progress.

The operation of HOLD requires Chip Select (CS#) keeping low and starts on falling edge of HOLD# pin signal while

Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Se-

rial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock (SCLK)

signal is being low (if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low),

see Figure 2.

Figure 2. Hold Condition Operation

CS#

SCLK

HOLD#

Hold

Condition

(standard)

Condition

(non-standard)

The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care

during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of

the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low.

P/N: PM1591

REV. 1.0, SEP. 03, 2010

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KH25L1606E

COMMAND DESCRIPTION

Table 4. COMMAND DEFINITION

DREAD

RDSR

WRSR

FAST READ

(fast read

data)

Command WREN (write WRDI (write

READ (read

(Double

Output Mode

command)

3B (hex)

AD1

(read status (write status

(byte)

enable)

disable)

data)

register)

05 (hex)

register)

01 (hex)

1st byte

2nd byte

3rd byte

4th byte

5th byte

06 (hex)

04 (hex)

03 (hex)

AD1

0B (hex)

AD1

AD2

AD3

AD2

AD3

Dummy

AD2

AD3

Dummy

sets the (WEL) resets the

write enable (WEL) write

to read out to write new n bytes read n bytes read n bytes read

the values values to the out until CS# out until CS# out by Dual

latch bit

enable latch of the status status register goes high

goes high

Output until

CS# goes

high

Action

bit

register

RDP (Release

from deep

power down)

Command SE (sector

BE (block

erase)

CE (chip

erase)

PP (page

program)

DP (Deep

power down)

RES (read

electronic ID)

(byte)

erase)

1st byte

2nd byte

3rd byte

4th byte

5th byte

20 (hex)

AD1

AD2

52 or D8 (hex) 60 or C7 (hex)

02 (hex)

AD1

AD2

B9 (hex)

AB (hex)

AD1

AD2

AD3

x

AD3

to erase the to erase the

to erase

to program enters deep release from to read out

selected

sector

selected

block

whole chip the selected power down deep power 1-byte Device

Action

page

mode

down mode

ID

REMS (read

electronic

manufacturer secured OTP) secured OTP)

& device ID)

RDID

(read identiﬁc-

ation)

RDSCUR

(read security (write security

WRSCUR

Command

(byte)

ENSO (enter EXSO (exit

register)

1st byte

2nd byte

3rd byte

4th byte

5th byte

9F (hex)

90 (hex)

B1 (hex)

C1 (hex)

2B (hex)

2F (hex)

x

ADD (Note 1)

outputs

JEDEC

ID: 1-byte

Manufact-urer

ID & 2-byte

Device ID

output the

to enter

to exit the 512 to read value

to set the

Manufacturer the 512 bit bit secured

ID & Device secured OTP OTP mode

of security lock-down bit

register

as "1" (once

lock-down,

cannot be

updated)

Action

ID

mode

Note 1: ADD=00H will output the manufacturer ID ﬁrst and ADD=01H will output device ID ﬁrst.

Note 2: It is not recommended to adopt any other code not in the command deﬁnition table, which will potentially

enter the hidden mode.

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(1) Write Enable (WREN)

The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE,

BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN in-

struction setting the WEL bit.

The sequence is shown as Figure 11.

(2) Write Disable (WRDI)

The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.

The sequence is shown as Figure 12.

The WEL bit is reset by following situations:

- Power-up

- Write Disable (WRDI) instruction completion

- Write Status Register (WRSR) instruction completion

- Page Program (PP) instruction completion

- Sector Erase (SE) instruction completion

- Block Erase (BE) instruction completion

- Chip Erase (CE) instruction completion

(3) Read Status Register (RDSR)

The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in

program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)

bit before sending a new instruction when a program, erase, or write status register operation is in progress.

The sequence is shown as Figure 13.

The deﬁnition of the status register bits is as below:

WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write

status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status

register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status

register cycle.

WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable

latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/

erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de-

vice will not accept program/erase/write status register instruction. The program/erase command will be ignored and

not affect value of WEL bit if it is applied to a protected memory area.

BP3, BP2, BP1, BP0 bits. The Block Protect (BP3-BP0(16Mb) ; BP2-BP0(8Mb)) bits, non-volatile bits, indicate the

protected area(as deﬁned in table 2) of the device to against the program/erase instruction without hardware pro-

tection mode being set. To write the Block Protect (BP3-BP0(16Mb) ; BP2-BP0(8Mb)) bits requires the Write Status

Register (WRSR) instruction to be executed. Those bits deﬁne the protected area of the memory to against Page

Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits

set to 0, the CE instruction can be executed).

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SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection

(WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and

WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no

longer accepted for execution and the SRWD bit and Block Protect bits (BP3-BP0(16Mb) ; BP2-BP0(8Mb)) are read

only.

Status Register for KH25L8006E

bit7

bit6

bit5

bit4

BP2

(level of

protected

block)

bit3

BP1

(level of

protected

block)

bit2

BP0

(level of

protected

block)

bit1

bit0

SRWD (status

register write

protect)

WEL

(write enable

latch)

WIP

(write in

progress bit)

0

1=write

enable

0=not write 0=not in write

1=write

operation

1=status

register write

disable

0

(note 1)

enable

operation

Non-volatile

bit

Non-volatile Non-volatile Non-volatile

volatile bit

bit

note 1: see the table "Protected Area Size".

Status Register for KH25L1606E

bit7

bit6

bit5

BP3

(level of

protected

block)

bit4

BP2

(level of

protected

block)

bit3

BP1

(level of

protected

block)

bit2

BP0

(level of

protected

block)

bit1

bit0

SRWD (status

register write

protect)

WEL

(write enable

latch)

WIP

(write in

progress bit)

0

1=write

enable

0=not write 0=not in write

1=write

operation

1=status

register write

disable

0

(note 1)

enable

operation

Non-volatile

bit

Non-volatile Non-volatile Non-volatile Non-volatile

bit bit bit bit

volatile bit

note 1: see the table "Protected Area Size".

(4) Write Status Register (WRSR)

The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the

Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ad-

vance. The WRSR instruction can change the value of Block Protect (BP3-BP0(16Mb) ; BP2-BP0(8Mb)) bits to de-

ﬁne the protected area of memory (as shown in table 1). The WRSR also can set or reset the Status Register Write

Disable (SRWD) bit in accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be execut-

ed once the Hardware Protected Mode (HPM) is entered.

The sequence is shown as Figure 14.

The WRSR instruction has no effect on b6, b1, b0 of the status register.

The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.

The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write

in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1

during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)

bit is reset.

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Table 5. Protection Modes

Mode

Status register condition

WP# and SRWD bit status

Memory

Status register can be written

in (WEL bit is set to "1") and

the SRWD, BP3-BP0(16Mb) ;

BP2-BP0(8Mb)

Software protection

mode (SPM)

WP#=1 and SRWD bit=0, or

WP#=0 and SRWD bit=0, or

WP#=1 and SRWD=1

The protected area

cannot

be program or erase.

bits can be changed

The SRWD, BP3-BP0(16Mb) ;

BP2-BP0(8Mb) of

status register bits cannot be

changed

The protected area

cannot

be program or erase.

Hardware protection

mode (HPM)

WP#=0, SRWD bit=1

Note:

1. As deﬁned by the values in the Block Protect (BP3-BP0(16Mb) ; BP2-BP0(8Mb)) bits of the Status Register, as

shown in Table 1.

As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).

Software Protected Mode (SPM):

-

When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change

the values of SRWD, BP3-BP0(16Mb) ; BP2-BP0(8Mb). The protected area, which is deﬁned by BP3-

BP0(16Mb) ; BP2-BP0(8Mb) is at software protected mode (SPM).

-

When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of

SRWD, BP3-BP0(16Mb) ; BP2-BP0(8Mb). The protected area, which is deﬁned by BP3-BP0(16Mb) ; BP2-

BP0(8Mb), is at software protected mode (SPM)

Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously

been set. It is rejected to write the Status Register and not be executed.

Hardware Protected Mode (HPM):

-

When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected

mode (HPM). The data of the protected area is protected by software protected mode by BP3-BP0(16Mb) ; BP2-

BP0(8Mb) and hardware protected mode by the WP# to against data modiﬁcation.

Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered.

If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use

software protected mode via BP3-BP0(16Mb) ; BP2-BP0(8Mb).

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(5) Read Data Bytes (READ)

The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on

the falling edge of SCLK at a maximum frequency fR. The ﬁrst address byte can be at any location. The address

is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can

be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been

reached.

The sequence is shown as Figure 15.

(6) Read Data Bytes at Higher Speed (FAST_READ)

The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and

data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The ﬁrst address byte can be at

any location. The address is automatically increased to the next higher address after each byte data is shifted out,

so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when

the highest address has been reached.

The sequence is shown as Figure 16.

While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-

pact on the Program/Erase/Write Status Register current cycle.

(7) Dual Output Mode (DREAD)

The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising

edge of SCLK, and data of every two bits(interleave on 1I/2O pins) shift out on the falling edge of SCLK at a maxi-

mum frequency fT. The ﬁrst address byte can be at any location. The address is automatically increased to the next

higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruc-

tion. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruc-

tion, the data out will perform as 2-bit instead of previous 1-bit.

The sequence is shown as Figure 17.

While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

The DREAD only perform read operation. Program/Erase /Read ID/Read status/Read ID....operation do not support

DREAD throughputs.

(8) Sector Erase (SE)

The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for

any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit be-

fore sending the Sector Erase (SE). Any address of the sector (see table 3) is a valid address for Sector Erase (SE)

instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in);

otherwise, the instruction will be rejected and not executed.

Address bits [Am-A12] (Am is the most signiﬁcant address) select the sector address.

The sequence is shown as Figure 18.

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The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the

tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the

page is protected by BP3-BP0(16Mb) ; BP2-BP0(8Mb) bits, the Sector Erase (SE) instruction will not be executed

on the page.

(9) Block Erase (BE)

The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for

64K-byte sector erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)

bit before sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE)

instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in);

otherwise, the instruction will be rejected and not executed.

The sequence is shown as Figure 19.

The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the

tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the

page is protected by BP3-BP0(16Mb) ; BP2-BP0(8Mb) bits, the Block Erase (BE) instruction will not be executed on

the page.

(10) Chip Erase (CE)

The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-

tion must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the

sector (see table 3) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte

boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not ex-

ecuted.

The sequence is shown as Figure 20.

The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE

timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is

protected by BP3-BP0(16Mb) ; BP2-BP0(8Mb) bits, the Chip Erase (CE) instruction will not be executed. It will be

only executed when BP3-BP0(16Mb) ; BP2-BP0(8Mb) all set to "0".

(11) Page Program (PP)

The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction

must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). If the eight least sig-

niﬁcant address bits (A7-A0) are not all 0, all transmitted data which goes beyond the end of the current page are

programmed from the start address if the same page (from the address whose 8 least signiﬁcant address bits (A7-

A0) are all 0). The CS# must keep during the whole Page Program cycle. The CS# must go high exactly at the

byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not

executed. If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request

page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed

at the request address of the page without effect on other address of the same page.

The sequence is shown as Figure 21.

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KH25L8006E

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The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the

tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the

page is protected by BP3-BP0(16Mb) ; BP2-BP0(8Mb) bits, the Page Program (PP) instruction will not be executed.

(12) Deep Power-down (DP)

The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to enter-

ing the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode

requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not ac-

tive and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep

power-down mode. It's different from Standby mode.

The sequence is shown as Figure 22.

Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)

and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Power-

down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby

mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction

code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay

of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.

(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES)

The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip

Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the

Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in

the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Se-

lect (CS#) must remain High for at least tRES2(max), as speciﬁed in Table 9. Once in the Stand-by Power mode, the

device waits to be selected, so that it can receive, decode and execute instructions.

RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID

Deﬁnitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design,

please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed,

only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/

write cycle in progress.

The sequence is shown in Figure 23 and Figure 24.

The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-

edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously

in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in

Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least

tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute

instruction.

The RDP instruction is for releasing from Deep Power Down Mode.

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(14) Read Identiﬁcation (RDID)

The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC

Manufacturer ID and Device ID are listed as table of "ID Deﬁnitions".

The sequence is shown as Figure 25.

While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cy-

cle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.

(15) Read Electronic Manufacturer ID & Device ID (REMS)

The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the

JEDEC assigned manufacturer ID and the speciﬁc device ID.

The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initi-

ated by driving the CS# pin low and shift the instruction code "90h" or "EFh" followed by two dummy bytes and one

bytes address (A7~A0). After which, the Manufacturer ID for MXIC and the Device ID are shifted out on the falling

edge of SCLK with most signiﬁcant bit (MSB) ﬁrst as shown in Figure 26. The Device ID values are listed in Table of

ID Deﬁnitions. If the one-byte address is initially set to 01h, then the device ID will be read ﬁrst and then followed by

the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other.

The instruction is completed by driving CS# high.

Table 6. ID DEFINITIONS

Command Type

KH25L8006E

KH25L1606E

manufacturer

memory

density

14

manufacturer

memory

density

15

memory type

ID

C2

ID

C2

RDID Command

20

electronic ID

13

20

electronic ID

14

RES Command

REMS

manufacturer

device ID

13

device ID

14

ID

C2

ID

C2

(16) Enter Secured OTP (ENSO)

The ENSO instruction is for entering the additional 512 bit secured OTP mode. The additional 512 bit secured OTP

is independent from main array, which may use to store unique serial number for system identiﬁer. After entering the

Secured OTP mode, and then follow standard read or program, procedure to read out the data or update data. The

Secured OTP data cannot be updated again once it is lock-down.

Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once se-

curity OTP is lock down, only read related commands are valid.

(17) Exit Secured OTP (EXSO)

The EXSO instruction is for exiting the additional 512 bit secured OTP mode.

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(18) Read Security Register (RDSCUR)

The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read

at any time (even in program/erase/write status register/write security register condition) and continuously.

The deﬁnition of the Security Register bits is as below:

Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or

not. When it is "0", it indicates non- factory lock; "1" indicates factory- lock.

Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for custom-

er lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 512 bit Secured OTP

area cannot be update any more. While it is in 512 bit secured OTP mode, array access is not allowed.

Table 7. SECURITY REGISTER DEFINITION

bit7

bit6

bit5

bit4

bit3

x

bit2

x

bit1

bit0

LDSO

(indicate if

lock-down

Secured OTP

indicator bit

x

0 = not lockdown

1 = lock-down

(cannot

program/erase

OTP)

0 = nonfactory

lock

1 = factory

lock

reserved

volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit

non-volatile bit

(19) Write Security Register (WRSCUR)

The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN

instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change the values

of bit1 (LDSO bit) for customer to lock-down the 512 bit Secured OTP area. Once the LDSO bit is set to "1", the Se-

cured OTP area cannot be updated any more.

The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.

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POWER-ON STATE

The device is at below states when power-up:

- Standby mode ( please note it is not deep power-down mode)

- Write Enable Latch (WEL) bit is reset

The device must not be selected during power-up and power-down stage unless the VCC achieves below correct

level:

- VCC minimum at power-up stage and then after a delay of tVSL

- GND at power-down

Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.

An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change

during power up state.

For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not

guaranteed. The read, write, erase, and program command should be sent after the below time delay:

- tVSL after VCC reached VCC minimum level

The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.

Please refer to the ﬁgure of "power-up timing".

Note:

- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend-

ed.(generally around 0.1uF)

INITIAL DELIVERY STATE

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status

Register contains 00h (all Status Register bits are 0).

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ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

RATING

VALUE

Ambient Operating Temperature

Storage Temperature

Applied Input Voltage

Applied Output Voltage

VCC to Ground Potential

Commercial grade

0 C to 70 C

° °

-65°C to 150°C

-0.5V to 4.6V

NOTICE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the

device. This is stress rating only and functional operational sections of this speciﬁcation is not implied. Exposure

to absolute maximum rating conditions for extended period may affect reliability.

2. Speciﬁcations contained within the following tables are subject to change.

3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Fig-

ure 3 and 4.

Figure 3.Maximum Negative Overshoot Waveform

Figure 4. Maximum Positive Overshoot Waveform

20ns

Vss

Vcc + 2.0V

Vss-2.0V

Vcc

20ns

CAPACITANCE TA = 25 C, f = 1.0 MHz

°

SYMBOL

CIN

COUT

PARAMETER

Input Capacitance

Output Capacitance

MIN.

TYP

MAX.

6

8

UNIT

pF

CONDITIONS

VIN = 0V

VOUT = 0V

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Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL

Input timing referance level

0.8VCC

Output timing referance level

0.7VCC

AC

Measurement

Level

0.5VCC

0.3VCC

0.2VCC

Note: Input pulse rise and fall time are <5ns

Figure 6. OUTPUT LOADING

DEVICE UNDER

TEST

2.7K ohm

+3.3V

CL

6.2K ohm

DIODES=IN3064

OR EQUIVALENT

CL=30pF/15pF Including jig capacitance

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Table 8. DC CHARACTERISTICS

SYMBOL PARAMETER

Notes

MIN.

TYP.

MAX.

UNITS TEST CONDITIONS

VCC = VCC Max,

uA

ILI

Input Load Current

1

± 2

VIN = VCC or GND

VCC = VCC Max,

uA

ILO

Output Leakage Current

1

± 2

25

VIN = VCC or GND

VIN = VCC or GND,

ISB1 VCC Standby Current

uA

CS# = VCC

8Mb

16Mb

8Mb

5

10

20

12

uA

Deep Power-down

Current

VIN = VCC or GND,

CS# = VCC

ISB2

uA

f=86MHz

mA

1

fT=80MHz (2 x I/O read)

SCLK=0.1VCC/0.9VCC,

SO=Open

16Mb

25

mA

f=66MHz,

SCLK=0.1VCC/0.9VCC,

SO=Open

8Mb

16Mb

8Mb

1

12

20

4

mA

ICC1 VCC Read

f=33MHz,

SCLK=0.1VCC/0.9VCC,

SO=Open

16Mb

10

Program in Progress,

CS# = VCC

ICC2 VCC Program Current (PP)

1

20

mA

VCC Write Status

ICC3 Register (WRSR)

Current

8Mb

16Mb

8Mb

1

15

20

15

20

mA

Program status register

in progress, CS#=VCC

VCC Sector Erase

ICC4

Erase in Progress,

CS#=VCC

Current (SE)

16Mb

Erase in Progress,

CS#=VCC

ICC5 VCC Chip Erase Current (CE)

VIL

VIH

VOL

Input Low Voltage

Input High Voltage

Output Low Voltage

-0.5

0.3VCC

VCC+0.4

0.4

V

0.7VCC

IOL = 1.6mA

IOH = -100uA

VOH Output High Voltage

VCC-0.2

Notes :

1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).

2. Not 100% tested.

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Table 9. AC CHARACTERISTICS

Symbol Alt. Parameter

Min.

Typ.

Max.

Unit

Clock Frequency for the following instructions:

fSCLK

fC FAST_READ, PP, SE, BE, CE, DP, RES, RDP,

WREN, WRDI, RDID, RDSR, WRSR

DC

86

MHz

fRSCLK

fTSCLK

fR Clock Frequency for READ instructions

fT Clock Frequency for 2READ instructions

DC

5.5

13

5.5

13

0.1

5

33

80

MHz

ns

fC=86MHz

fR=33MHz

fC=86MHz

fR=33MHz

tCH(1) tCLH Clock High Time

tCL(1)

tCLL Clock Low Time

Clock Rise Time (3) (peak to peak)

Clock Fall Time (3) (peak to peak)

ns

tCLCH(2)

tCHCL(2)

V/ns

ns

tSLCH tCSS CS# Active Setup Time (relative to SCLK)

tCHSL CS# Not Active Hold Time (relative to SCLK)

tDVCH tDSU Data In Setup Time

5

2

tCHDX

tCHSH

tSHCH

tDH Data In Hold Time

5

15

40

ns

CS# Active Hold Time (relative to SCLK)

CS# Not Active Setup Time (relative to SCLK)

Read

tSHSL tCSH CS# Deselect Time

Write

ns

tSHQZ(2) tDIS Output Disable Time

6

ns

tCLQV

tCLQX

tHLCH

tCHHH

tHHCH

tCHHL

tV Clock Low to Output Valid, Loading 30pF/15pF

tHO Output Hold Time

8/6

ns

0

5

ns

HOLD# Setup Time (relative to SCLK)

HOLD# Hold Time (relative to SCLK)

HOLD Setup Time (relative to SCLK)

HOLD Hold Time (relative to SCLK)

ns

tHHQX(2) tLZ HOLD to Output Low-Z

tHLQZ(2) tHZ HOLD# to Output High-Z

6

ns

tWHSL(4)

tSHWL (4)

tDP(2)

Write Protect Setup Time

Write Protect Hold Time

20

100

ns

us

CS# High to Deep Power-down Mode

CS# High to Standby Mode without Electronic Signature

Read

CS# High to Standby Mode with Electronic Signature

Read

10

tRES1(2)

tRES2(2)

8.8

us

8.8

tW

Write Status Register Cycle Time

Byte-Program

Page Program Cycle Time

Sector Erase Cycle Time

5

9

1.4

60

0.7

7

40

300

5

300

2

ms

us

ms

s

tBP

tPP

tSE

tBE

Block Erase Cycle Time

8Mb

15

30

s

tCE

Chip Erase Cycle Time

16Mb

14

Notes:

1. tCH + tCL must be greater than or equal to 1/ fC. For Fast Read, tCL/tCH=5.5/5.5.

2. Value guaranteed by characterization, not 100% tested in production.

3. Expressed as a slew-rate.

4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

5. Test condition is shown as Figure 5.

6. The CS# rising time needs to follow tCLCH spec and CS# falling time needs to follow tCHCL spec.

P/N: PM1591

REV. 1.0, SEP. 03, 2010

28

KH25L8006E

KH25L1606E

Timing Analysis

Figure 7. Serial Input Timing

tSHSL

tSHCH

tCHCL

CS#

tCHSL

tSLCH

tCHSH

SCLK

tDVCH

tCHDX

tCLCH

MSB

LSB

SI

High-Z

SO

Figure 8. Output Timing

P/N: PM1591

REV. 1.0, SEP. 03, 2010

29

KH25L8006E

KH25L1606E

Figure 9. Hold Timing

CS#

tHLCH

tCHHH

tCHHL

tHLQZ

tHHCH

SCLK

tHHQX

SO

HOLD#

* SI is "don't care" during HOLD operation.

Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1

WP#

tSHWL

tWHSL

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12

13 14

15

SCLK

01

SI

High-Z

SO

P/N: PM1591

REV. 1.0, SEP. 03, 2010

30

KH25L8006E

KH25L1606E

Figure 11. Write Enable (WREN) Sequence (Command 06)

CS#

0

1

2

3

4

5

6

7

SCLK

Command

06

SI

High-Z

SO

Figure 12. Write Disable (WRDI) Sequence (Command 04)

CS#

0

1

2

3

4

5

6

7

SCLK

Command

04

SI

High-Z

SO

P/N: PM1591

REV. 1.0, SEP. 03, 2010

31

KH25L8006E

KH25L1606E

Figure 13. Read Status Register (RDSR) Sequence (Command 05)

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

SCLK

SI

command

05

Status Register Out

High-Z

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

Figure 14. Write Status Register (WRSR) Sequence (Command 01)

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

SCLK

command

01

Status

Register In

SI

7

6

5

4

3

2

0

1

MSB

High-Z

SO

Figure 15. Read Data Bytes (READ) Sequence (Command 03)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

SCLK

command

03

24-Bit Address

23 22 21

MSB

3

2

1

0

SI

Data Out 1

Data Out 2

High-Z

2

7

6

5

4

3

1

7

0

SO

MSB

P/N: PM1591

REV. 1.0, SEP. 03, 2010

32

KH25L8006E

KH25L1606E

Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

SCLK

Command

0B

24 BIT ADDRESS

SI

23 22 21

3

2

1

0

High-Z

SO

CS#

47

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCLK

Dummy Byte

7

6

5

4

3

2

0

1

SI

DATA OUT 2

DATA OUT 1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

SO

MSB

P/N: PM1591

REV. 1.0, SEP. 03, 2010

33

KH25L8006E

KH25L1606E

Figure 17. Dual Output Read Mode Sequence (Command 3B)

CS#

0

1

2

3

4

5

6

7

8

9

10 11

30 31 32

39 40 41 42 43

SCLK

8 dummy

cycle

8 Bit Instruction

24 BIT Address

Data Output

data

address

bit23, bit22, bit21...bit0

3B(hex)

dummy

SI/SO0

bit6, bit4, bit2...bit0, bit6, bit4....

High Impedance

data

SO/SO1

bit7, bit5, bit3...bit1, bit7, bit5....

Figure 18. Sector Erase (SE) Sequence (Command 20)

CS#

0

1

2

3

4

5

6

7

8

9

29 30 31

SCLK

Command

20

24 Bit Address

SI

23 22

MSB

2

1

0

Note: SE command is 20(hex).

Figure 19. Block Erase (BE) Sequence (Command D8)

Note: BE command is D8(hex).

P/N: PM1591

REV. 1.0, SEP. 03, 2010

34

KH25L8006E

KH25L1606E

Figure 20. Chip Erase (CE) Sequence (Command 60 or C7)

CS#

0

1

2

3

4

5

6

7

SCLK

Command

60 or C7

SI

Note: CE command is 60(hex) or C7(hex).

Figure 21. Page Program (PP) Sequence (Command 02)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

SCLK

Command

02

24-Bit Address

Data Byte 1

23 22 21

MSB

3

2

1

0

7

6

5

4

3

2

0

1

SI

MSB

CS#

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

SCLK

Data Byte 2

Data Byte 3

Data Byte 256

7

6

5

4

3

2

0

7

6

5

4

3

2

0

7

6

5

4

3

2

0

1

SI

MSB

P/N: PM1591

REV. 1.0, SEP. 03, 2010

35

KH25L8006E

KH25L1606E

Figure 22. Deep Power-down (DP) Sequence (Command B9)

CS#

t_DP

0

1

2

3

4

5

6

7

SCLK

SI

Command

B9

Stand-by Mode

Deep Power-down Mode

Figure 23. Release from Deep Power-down (RDP) Sequence (Command AB)

CS#

t

RES1

0

1

2

3

4

5

6

7

SCLK

SI

Command

AB

High-Z

SO

Deep Power-down Mode

Stand-by Mode

Figure 24. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38

SCLK

Command

AB

t_RES2

3 Dummy Bytes

SI

23 22 21

MSB

3

2

1

0

Electronic Signature Out

High-Z

7

6

5

4

3

2

0

1

SO

MSB

Deep Power-down Mode

Stand-by Mode

P/N: PM1591

REV. 1.0, SEP. 03, 2010

36

KH25L8006E

KH25L1606E

Figure 25. Read Identiﬁcation (RDID) Sequence (Command 9F)

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18

28 29 30 31

SCLK

SI

Command

9F

Manufacturer Identification

Device Identification

High-Z

SO

7

6

5

3

2

1

0

15 14 13

MSB

3

2

1

0

MSB

Figure 26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF)

CS#

0

1

2

3

4

5

6

7

8

9 10

SCLK

Command

90

2 Dummy Bytes

SI

15 14 13

3

2

1

0

High-Z

SO

CS#

47

28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCLK

ADD (1)

7

6

5

4

3

2

0

1

SI

Manufacturer ID

Device ID

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

SO

MSB

Notes:

(1) ADD=00H will output the manufacturer's ID ﬁrst and ADD=01H will output device ID ﬁrst

(2) Instruction is either 90(hex) or EF(hex).

P/N: PM1591

REV. 1.0, SEP. 03, 2010

37

KH25L8006E

KH25L1606E

Figure 27. Read Security Register (RDSCUR) Sequence (Command 2B)

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

SCLK

SI

command

2B

Security Register Out

High-Z

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

Figure 28. Write Security Register (WRSCUR) Sequence (Command 2F)

CS#

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

SCLK

Security

Register In

command

2F

SI

7

6

5

4

3

2

0

1

MSB

High-Z

SO

P/N: PM1591

REV. 1.0, SEP. 03, 2010

38

KH25L8006E

KH25L1606E

Figure 29. Power-up Timing

V

CC

V

(max)

CC

Chip Selection is Not Allowed

V

(min)

CC

Device is fully accessible

tVSL

time

Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V.

Table 10. Power-Up Timing

Symbol

Parameter

Min.

Max.

Unit

tVSL(1)

VCC(min) to CS# low

200

us

Note: 1. The parameter is characterized only.

P/N: PM1591

REV. 1.0, SEP. 03, 2010

39

KH25L8006E

KH25L1606E

OPERATING CONDITIONS

At Device Power-Up and Power-Down

AC timing illustrated in Figure 30 and Figure 31 are the supply voltages and the control signals at device power-up

and power-down. If the timing in the ﬁgures is ignored, the device will not operate correctly.

During power-up and power down, CS# need to follow the voltage applied on VCC to keep the device not be se-

lected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.

Figure 30. AC Timing at Device Power-Up

VCC(min)

VCC

GND

tVR

tSHSL

CS#

tSHCH

tSLCH

tCHSL

tCHSH

SCLK

tDVCH

tCHCL

tCHDX

tCLCH

MSB IN

LSB IN

SI

High Impedance

SO

Symbol

Parameter

Notes

Min.

20

Max.

500000

Unit

tVR

VCC Rise Time

1

us/V

Notes :

1. Sampled, not 100% tested.

2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the ﬁgure, please refer to

"AC CHARACTERISTICS" table.

P/N: PM1591

REV. 1.0, SEP. 03, 2010

40

KH25L8006E

KH25L1606E

Figure 31. Power-Down Sequence

During power down, CS# need to follow the voltage drop on VCC to avoid mis-operation.

VCC

CS#

SCLK

P/N: PM1591

REV. 1.0, SEP. 03, 2010

41

KH25L8006E

KH25L1606E

ERASE AND PROGRAMMING PERFORMANCE

PARAMETER

Min.

TYP. (1)

Max. (2)

UNIT

ms

s

Write Status Register Time

Sector Erase Time

Block Erase Time

5

60

40

300

2

0.7

7

8Mb

15

30

300

5

s

Chip Erase Time

16Mb

14

s

Byte Program Time (via page program command)

Page Program Time

9

us

1.4

100,000

ms

cycles

Erase/Program Cycle

Note:

1. Typical program and erase time assumes the following conditions: 25 C, 3.3V, and checker board pattern.

°

2. Under worst conditions of 70 C and 2.7V.

°

3. System-level overhead is the time required to execute the ﬁrst-bus-cycle sequence for the programming com-

mand.

4. Erase/Program cycles comply with JEDEC JESD-47 & A117 standard.

DATA RETENTION

PARAMETER

Condition

Min.

Max.

UNIT

Data retention

55˚C

20

years

LATCH-UP CHARACTERISTICS

MIN.

MAX.

Input Voltage with respect to GND on all power pins, SI, CS#

Input Voltage with respect to GND on SO

Current

-1.0V

2 VCCmax

VCC + 1.0V

+100mA

-100mA

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

P/N: PM1591

REV. 1.0, SEP. 03, 2010

42

KH25L8006E

KH25L1606E

ORDERING INFORMATION

8Mb

OPERATING

CURRENT

MAX. (mA)

STANDBY

CURRENT

MAX. (uA)

CLOCK

PART NO.

Temperature

PACKAGE

Remark

(MHz)

8-SOP

(200mil)

8-PDIP

(300mil)

KH25L8006EM2C-12G

KH25L8006EPC-12G

86

12

25

0 C~70 C

Pb-free

°

86

0 C~70 C

° °

16Mb

OPERATING

CURRENT

MAX. (mA)

STANDBY

CURRENT

MAX. (uA)

CLOCK

(MHz)

PART NO.

Temperature

PACKAGE

Remark

8-SOP

KH25L1606EM2C-12G

86

25

0 C~70 C

Pb-free

°

(200mil)

P/N: PM1591

REV. 1.0, SEP. 03, 2010

43

KH25L8006E

KH25L1606E

PART NAME DESCRIPTION

P/N: PM1591

REV. 1.0, SEP. 03, 2010

44

KH25L8006E

KH25L1606E

PACKAGE INFORMATION

P/N: PM1591

REV. 1.0, SEP. 03, 2010

45

KH25L8006E

KH25L1606E

P/N: PM1591

REV. 1.0, SEP. 03, 2010

46

KH25L8006E

KH25L1606E

Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which

the failure of a single component could cause death, personal injury, severe physical damage, or other substan-

tial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft

and military application. Macronix and its suppliers will not be liable to you and/or any third party for any claims,

injuries or damages that may be incurred due to use of Macronix's products in the prohibited applications.

Logo, KH, KH logo are trademarks or registered trademarks of Macronix International Co., Ltd. The names

and brands of other companies are for identiﬁcation purposes only and may be claimed as the property of the

respective companies.

For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and speciﬁcations without notice.

P/N: PM1591

REV. 1.0, SEP. 03, 2010

47

型号:	KH2C-20B
生命周期：	Active
IHS 制造商：	IDEC CORP
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8536.50.90.65
风险等级：	5.77
执行器类型：	KEYLOCK
主体高度：	34.4932 mm
中心触点镀层：	SILVER
触点（交流）最大额定R负载：	1A@125VAC
最大触点电流（交流）：	1 A
最大触点电流（直流）：	1 A
触点（直流）最大额定R负载：	1A@30VDC
触点电阻：	0.05 m Ω
最大触点电压（交流）：	125 V
最大触点电压（直流）：	30 V
介质耐电压：	2500VAC V
电气寿命：	30000 Cycle(s)
末端触点镀层：	SILVER
分度角：	90 deg
绝缘电阻：	100000000 Ω
制造商序列号：	KH
安装特点：	PANEL MOUNT
位置数：	2
最高工作温度：	50 °C
最低工作温度：	-25 °C
可焊性：	HAND
表面贴装：	NO
开关动作：	MAINTAINED
开关功能：	DPDT
开关类型：	KEYLOCK SWITCH
端子长度：	0.079 inch
端接类型：	QUICK CONNECT

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