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产品型号KM68512ALT-7L的概述

KM68512ALT-7L芯片概述 KM68512ALT-7L是一款由韩国三星电子公司（Samsung Electronics）设计和制造的静态RAM（SRAM）芯片。该芯片广泛应用于各种电子设备，如计算机、通讯设备、工业控制和消费电子产品。KM68512ALT-7L的存储容量为512K位，能够以较高的速度进行数据访问，其设计特性使其在处理器高速缓存、数据缓冲和其他需要快速存取存储的场合中特别有用。 KM68512ALT-7L的详细参数 KM68512ALT-7L拥有一系列重要的参数，值得注意的是： - 存储类型：静态随机存取存储器（SRAM） - 存储容量：512K位（64K字 x 8位） - 访问时间：7纳秒（ns），为芯片的读写操作提供了极高的速度 - 电源电压：典型工作电压为5V，工作在-40°C至85°C的温度范围内 - 封装形式：提供多种封装选择，包括DIP、SOP等 - ...

产品型号KM68512ALT-7L的Datasheet PDF文件预览

KM68512A Family

CMOS SRAM

Document Title

64Kx8 bit Low Power CMOS Static RAM

Revision History

Revision No.

History

Draft Data

Remark

0.0

Initial draft

Novemer 28, 1993

May 13, 1994

Design target

Preliminary

Final

0.1

1.0

2.0

Revision

Finalize

December 1, 1994

August 12, 1995

Revision

Final

- Add 45ns part with 30pf test load.

3.0

4.0

Revision

April 15, 1996

Final

- Change Data Sheet format :

One data sheets for industrial and commercial product

Revision

January 9, 1998

- Change Data Sheet format

- Remove 45ns part from commercial product and 100ns part

from industrial product

- Remove low power part form TSOP package

The attached data, sheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

Revision 4.0

January 1997

KM68512A Family

CMOS SRAM

64Kx8 bit Low Power CMOS Static RAM

FEATURES

GENERAL DESCRIPTION

· Process Technology: Poly Load

· Organization: 64Kx8

The KM68512A families are fabricated by SAMSUNG¢s

advanced CMOS process technology. The families support

various operating temperature ranges and have various

package types for user flexibility of system design. The

families also support low data retention voltage for battery

back-up operation with low data retention current.

· Power Supply Voltage: 4.5~5.5V

· Low Data Retention Voltage: 2V(Min)

· Three state output and TTL Compatible

· Package Type: 32-SOP-525, 32-TSOP1-0820F

PRODUCT FAMILY

Power Dissipation

Product Family Operating Temperature

VCC Range

Speed

PKG Type

Standby

(ISB1, Max)

Operating

(ICC2, Max)

KM68512AL

100mA

20mA

Commercial (0~70°C)

55/70ns

70ns

KM68512AL-L

32-SOP

32-TSOP1-F

4.5 to 5.5V

70mA

KM68512ALI

100mA

50mA

Industrial (-40~85°C)

KM68512ALI-L

PIN DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

VCC

A15

CS2

N.C

Clk gen.

Precharge circuit.

N.C

A14

A12

A11

A10

CS1

I/O8

I/O7

I/O6

I/O5

I/O4

VSS

I/O3

I/O2

I/O1

A13

CS2

A15

VCC

A14

A12

Memory array

512 rows

128´ 8 columns

Row

select

A11

32-SOP

32-TSOP

Type1 - Forward

A12

A13

A14

A15

A10

CS1

I/O8

I/O7

I/O6

I/O5

I/O4

I/O1

I/O2

I/O3

VSS

Data

cont

I/O Circuit

I/O1

I/O8

Column select

Data

cont

Name

CS1, CS2

Function

A0 A1 A2 A8 A9 A10 A11

Chip Select Inputs

Output Enable Input

Write Enable Input

Address Inputs

Data Inputs/Outputs

Power

CS1

CS2

Control

Logic

A0~A15

I/O1~I/O8

Vcc

Vss

Ground

N.C

No Connection

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Revision 4.0

January 1997

KM68512A Family

CMOS SRAM

PRODUCT LIST

Commercial Temperature Products(0~70°C)

Industrial Temperature Products(-40~85°C)

Part Name

Function

Part Name

Function

KM68512ALG-5

KM68512ALG-5L

KM68512ALG-7

KM68512ALG-7L

32-SOP, 55ns, L-pwr

32-SOP, 55ns, LL-pwr

32-SOP, 70ns, L-pwr

32-SOP, 70ns, LL-pwr

KM68512ALGI-7

KM68512ALGI-7L

32-SOP, 70ns, L-pwr

32-SOP, 70ns, LL-pwr

KM68512ALTI-7L

32-TSOP1-F, 70ns, LL-pwr

KM68512ALT-5L

KM68512ALT-7L

32-TSOP1-F, 55ns, LL-pwr

32-TSOP1-F, 70ns, LL-pwr

FUNCTIONAL DESCRIPTION

CS1

CS2

I/O Pin

High-Z

Dout

Mode

Power

Standby

Active

X¹⁾

Deselected

Output Disabled

Read

X¹⁾

Active

X¹⁾

Din

Write

Active

1. X means don¢t care.(Must be low or high state)

ABSOLUTE MAXIMUM RATINGS¹⁾

Item

Symbol

VIN,VOUT

VCC

Ratings

-0.5 to 7.0

1.0

Unit

Remark

Voltage on any pin relative to Vss

Voltage on Vcc supply relative to Vss

Power Dissipation

Storage temperature

TSTG

-65 to 150

0 to 70

°C

KM68512A

KM68512AI

Operating Temperature

-40 to 85

Soldering temperature and time

TSOLDER

260°C, 10sec(Lead Only)

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Revision 4.0

January 1997

KM68512A Family

CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS¹⁾

Item

Symbol

Vcc

Min

4.5

Typ

Max

5.5

Unit

Supply voltage

Ground

5.0

Vss

Vcc+0.5V²⁾

0.8

Input high voltage

Input low voltage

VIH

2.2

-0.5³⁾

VIL

Note

1. Commercial Product : TA=0 to 70°C, unless otherwise specified

Industrial Product : TA=-40 to 85°C, unless otherwise specified

2. Overshoot : V_CC+3.0V in case of pulse width£30ns

3. Undershoot : -3.0V in case of pulse width£30ns

4. Overshoot and undershoot are sampled, not 100% tested

CAPACITANCE¹⁾(f=1MHz, TA=25°C)

Item

Input capacitance

Symbol

CIN

Test Condition

VIN=0V

Min

Max

Unit

Input/Output capacitance

CIO

VIO=0V

1. Capacitance is sampled, not 100% tested

DC AND OPERATING CHARACTERISTICS

Item

Symbol

ILI

Min Typ Max Unit

Test Conditions

Input leakage current

VIN=Vss to Vcc

-1

Output leakage current

Operating power supply current

ILO

CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc

IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL

ICC

15 mA

10 mA

Cycle time=1ms, 100% duty, IIO=0mA

CS1£0.2V, CS2³ VCC-0.2V, VIN£0.2V or VIN³ Vcc -0.2V

ICC1

Average operating current

Cycle time=Min, 100% duty, IIO=0mA, CS¹=VIL, CS2=VIH, VIN=VIH or VIL

ICC2

VOL

VOH

ISB

70 mA

Output low voltage

Output high voltage

Standby Current(TTL)

IOL=2.1mA

0.4

IOH=-1.0mA

2.4

CS1=VIH, CS2=VIL, Other inputs =VIH or VIL

Low Power

Low Low Power

100

KM68512AL/L-L

Standby

Current

CS1³ Vcc-0.2V, CS2³ Vcc-0.2V or CS2£0.2V

Other inputs =0 ~ Vcc

ISB1

Low Power

Low Low Power

100

(CMOS)

KM68512ALI/LI-L

Revision 4.0

January 1997

KM68512A Family

CMOS SRAM

AC OPERATING CONDITIONS

TEST CONDITIONS( Test Load and Input/Output Reference)

Input pulse level : 0.8 to 2.4V

Input rising and falling time : 5ns

Input and output reference voltage :1.5V

Output load(see right) : CL=100pF+1TTL

1. Including scope and jig capacitance

AC CHARACTERISTICS (Vcc=4.5~5.5V, KM68512A Family:TA=0 to 70°C, KM68512AI Family:TA=-40 to 85°C)

Speed Bins

Parameter List

Symbol

Units

55ns

70ns

Min

Max

Min

Max

Read cycle time

tRC

tAA

Address access time

Chip select to output

tCO1, tCO2

tOE

Output enable to valid output

Chip select to low-Z output

Output enable to low-Z output

Chip disable to high-Z output

Output disable to high-Z output

Output hold from address change

Write cycle time

Read

tLZ

tOLZ

tHZ

tOHZ

tOH

tWC

tCW

tAS

Chip select to end of write

Address set-up time

Address valid to end of write

Write pulse width

tAW

tWP

Write

Write recovery time

tWR

tWHZ

tDW

tDH

Write to output high-Z

Data to write time overlap

Data hold from write time

End write to output low-Z

tOW

DATA RETENTION CHARACTERISTICS

Item

Symbol

Min

Typ

Max

Unit

Test Condition

Vcc for data retention

VDR

IDR

2.0

5.5

CS1 ³ Vcc-0.2V

L-Ver

LL-Ver

0.5

KM68512AL/L-L

KM68512ALI/LI-L

Vcc=3.0V CS1³ Vcc-0.2V

CS2³ Vcc-0.2V or CS2£0.2V

Data retention current

L-Ver

LL-Ver

Data retention set-up time

Recovery time

tSDR

tRDR

See data retention waveform

1. CS¹³ Vcc-0.2V, CS2³ Vcc-0.2V( CS1 controlled) or CS2£0.2V(CS2 controlled).

Revision 4.0

January 1997

KM68512A Family

CMOS SRAM

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, WE=VIH)

tRC

Address

tAA

tOH

Data Valid

Data Out

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tOH

tAA

tCO1

CS1

tHZ(1,2)

CS2

tCO2

tOE

tOHZ

tOLZ

tLZ

High-Z

Data out

Data Valid

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

Revision 4.0

January 1997

KM68512A Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

tWC

Address

tCW(2)

tWR(4)

CS1

tAW

CS2

tCW(2)

tWP(1)

tAS(3)

tDW

tDH

Data Valid

Data in

tWHZ

tOW

Data Undefined

Data out

TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)

tWC

Address

CS1

tCW(2)

tAS(3)

tWR(4)

tAW

CS2

tWP(1)

tDW

tDH

Data in

Data out

Data Valid

High-Z

Revision 4.0

January 1997

KM68512A Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)

tWC

Address

CS1

tAS(3)

tCW(2)

tWR(4)

tAW

CS2

tCW(2)

tWP(1)

tDH

tDW

Data Valid

Data in

High-Z

Data out

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,

CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,

tWP is measured from the begining of write to the end of write.

2. tCW is measured from the CS¹going low or CS2 going high to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS¹or WE going high tWR(2)

applied in case a write ends as CS2 going to low.

DATA RETENTION WAVE FORM

CS1 controlled

Data Retention Mode

tSDR

tRDR

VCC

4.5V

2.2V

VDR

CS1³ VCC - 0.2V

CS1

GND

CS2 controlled

Data Retention Mode

VCC

4.5V

CS2

tSDR

tRDR

VDR

CS2£0.2V

0.4V

GND

Revision 4.0

January 1997

KM68512A Family

CMOS SRAM

PACKAGE DIMENSIONS

Units: millimeter(Inch)

32 PIN SMALL OUTLINE PACKAGE (525mil)

0~8°

#32

#17

14.12±0.30

0.556±0.012

11.43±0.20

0.450±0.008

#16

2.74±0.20

20.87

MAX

0.108±0.008

0.80±0.20

0.822

+0.10

-0.05

+0.004

-0.002

0.20

0.031±0.008

3.00

MAX

0.008

0.118

20.47±0.20

0.806±0.008

0.10 MAX

0.004 MAX

+0.100

-0.050

0.41

0.71

0.028

1.27

0.050

+0.004

-0.002

(

)

0.05

MIN

0.016

0.002

32-THIN SMALL OUTLINE PACKAGE TYPE I (0820F)

+0.10

-0.05

20.00±0.20

0.787±0.008

0.20

0.008^+0.004

-0.002

#32

0.25

(

)

0.010

MAX

8.40

0.331

0.50

0.0197

#16

#17

1.00±0.10

0.039±0.004

0.05

0.002

MIN

1.20

MAX

0.047

0.25

0.010

18.40±0.10

0.724±0.004

TYP

+0.10

-0.05

0.15

0.006^+0.004

-0.002

0~8°

0.50

0.020

0.45 ~0.75

0.018 ~0.030

(

)

Revision 4.0

January 1997

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