KS8721B现货热卖使用介绍供应商报价哪里找芯片批发报价-中国IC网-芯三七

KS8721B/BT

Micrel

KS8721B/BT

2.5V 10/100BasTX/FX MII Physical Layer Transceiver

Rev. 2.2

General Description

Features

Operating at 2.5 volts to meet low voltage and low power

requirements, the KS8721B/BT is a 10BaseT/100BaseTX/

FX Physical Layer Transceiver, which provides an MII to

transmit and receive data. It contains the 10BaseT Physical

Medium Attachment (PMA), Physical Medium Dependent

(PMD), and Physical Coding Sub-layer (PCS) functions.

Moreover, the KS8721B/BT has on-chip 10BaseT output

filtering, which eliminates the need for external filters and

allows a single set of line magnetics to be used to meet

requirements for both 100BaseTX and 10BaseT.

• Single chip 100BaseTX/100BaseFX/10BaseT physical

layer solution

• 2.5V CMOS design, power consumption <200mW

(excluding output driver current )

• Fully compliant to IEEE 802.3u standard

• Supports Media Independent Interface (MII) and

Reduced MII (RMII)

• Supports 10BaseT, 100BaseTX and 100BaseFX with

Far_End_Fault Detection

• Supports power down mode and power saving mode

• Configurable through MII serial management ports or via

external control pins

• Supports auto-negotiation and manual selection for

10/100Mbps speed and full/half-duplex mode

• On-chip built-in analog front end filtering for both

100BaseTX and 10BaseT

TheKS8721B/BTcanautomaticallyconfigureitselffor100or

10Mbpsandfullorhalfduplexoperation, usingon-chipAuto-

Negotiation algorithm. It is an ideal choice of physical layer

transceiver for 100BaseTX/10BaseT applications.

Data sheets and support documentation can be found on

Micrel’s web site at www.micrel.com.

Functional Diagram

4B/5B Encoder

NRZ/NRZI

MLT3 Encoder

TXD3

TXD2

TXD1

TXD0

TXER

TXC

Scrambler

10/100

Pulse

Shaper

TX+

TX-

Parallel/Serial

Transmitter

Parallel/Serial

Manchester Encoder

TXEN

CRS

COL

MII/RMII

Registers

and

Controller

Interface

Adaptive EQ

RX+

RX-

Base Line

Wander Correction

MLT3 Decoder

NRZI/NRZ

4B/5B Decoder

Descrambler

Clock

Recovery

MDIO

MDC

RXD3

RXD2

RXD1

RXD0

RXER

RXDV

RXC

Serial/Parallel

Auto

Negotiation

10BaseT

Receiver

Manchester Decoder

Serial/Parallel

Power

Down or

Saving

LINK

COL

FDX

SPD

LED

Driver

XI

PLL

XO

PWRDWN

Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com

August 2003

1

KS8721B/BT

Micrel

Features (continued)

Ordering Information

• LED outputs for link, activity, full/half duplex, collision

and speed

• Supports back to back, FX to TX for media converter

applications

• Supports MDI/MDI-X auto crossover

• 2.5V/3.3V tolerance on I/O

• Commercial temperature range: 0°C to +70°C

• Industrial temperature range: –40°C to +85°C

• Available in 48-pin SSOP and TQFP

Part Number Temperature Range Package

KS8721B

0°C to +70°C

–40°C to +85°C

0°C to +70°C

48-Pin SSOP

KS8721BI

KSZ8721B

KS8721BT

KSZ8721BT

48-Pin SSOP Lead Free

48-Pin TQFP

48-Pin TQFP Lead Free

KS8721B/BT

2

August 2003

KS8721B/BT

Micrel

Revision History

Revision Date

Summary of Changes

1.0

2.0

2/29/02

4/01/02

Document Origination (Preliminary)

Update timing Spec from page 33 to page 37

Change Revision ID from 1000 to 1001

Add new control register bit, Control Register 0 Bit 0, to control transmit enable/disable

Add 8h register map on the table

Editorial Change on FXSD/FXEN pin34

Change on duplex pin38 0=half and 1=full duplex

Change on the 10BT MII transmit timing 1.0us to 2.5us and Tlat 2.5us to 4BT

Add the TEST description mode on pin26

2.1

1/31/03

Add part number ordering information & remove pinout diagram

Edited pin description on the IO cloumn

Change the company logo, disclaimer, & contact info

Editorial changes on Stapping option description

Change on Register0h bit0, 1=disable and 0=enable

Add remote fault register4h bit13.

Add normal operating condition table & Thermal data for SSOP48 table

Add Reset Timing table & Transformer Lists

Add 48 TQFP pinout diagram & RMII AC Charateristics

Add ordering info for 48 Pin TQFP package, KS8721B/BTI industrial temperature, KSY8721B/KSY8721BT

environmentally friendly part number

2.2

8/29/03

Change part number from KS8721B to KS8721B/BT.

Change ordering info. from “KSY” to “KSZ” for lead free.

Change pin name from RMII_LPBK to RMII_BTB

Convert to new format.

August 2003

3

KS8721B/BT

Micrel

Table Of Contents

Pin Description ............................................................................................................................................................ 6

Strapping Option ......................................................................................................................................................... 9

Pin Configuration ...................................................................................................................................................... 10

Introduction

........................................................................................................................................................... 11

100BaseTX Transmit ........................................................................................................................................... 11

100BaseTX Receive ............................................................................................................................................ 11

PLL Clock Synthesizer......................................................................................................................................... 11

Scrambler/De-scrambler (100BaseTX only) ........................................................................................................ 11

10BaseT Transmit ............................................................................................................................................... 11

10BaseT Receive ................................................................................................................................................ 11

SQE and Jabber Function (10Base only) ............................................................................................................ 11

Auto-Negotiation .................................................................................................................................................. 11

MII Management Interface ................................................................................................................................... 12

MII Data Interface ................................................................................................................................................ 12

Transmit Clock ............................................................................................................................................. 12

Receive Clock .............................................................................................................................................. 12

Transmit Enable ........................................................................................................................................... 12

Receive Data Valid ...................................................................................................................................... 12

Error Signals ................................................................................................................................................ 12

Carrier Sense ............................................................................................................................................... 12

Collision ....................................................................................................................................................... 13

RMII Signal Definition .......................................................................................................................................... 13

Reference Clock .................................................................................................................................................. 13

Carrier Sense/Receive Data Valid ....................................................................................................................... 13

Receive Data ....................................................................................................................................................... 13

Transmit Enable................................................................................................................................................... 13

Transmit Data ...................................................................................................................................................... 14

Collision Detection ............................................................................................................................................... 14

RX_ER

........................................................................................................................................................... 14

RMII AC Characteristics ...................................................................................................................................... 14

Auto Crossover (Auto MDI/MDI-X) ...................................................................................................................... 15

Power Management............................................................................................................................................. 16

100BT FX Mode................................................................................................................................................... 16

Media Converter Option....................................................................................................................................... 16

Register Map ........................................................................................................................................................... 17

Register 0h: Basic Conrol ................................................................................................................................... 17

Register 1h: Basic Status.................................................................................................................................... 18

Register 2h: PHY Identifier 1 .............................................................................................................................. 18

Register 3h: PHY Identifier 2 .............................................................................................................................. 18

Register 4h: Auto-Negotiation Advertisement ..................................................................................................... 18

Register 5h: Auto-Negotiation Link Partner Ability .............................................................................................. 18

Register 6h: Auto-Negotiation Expansion ........................................................................................................... 19

Register 7h: Auto-Negotiation Next Page ........................................................................................................... 19

Register 8h: Link Partner Next Page Ability ........................................................................................................ 19

Register 15h: RXER Counter .............................................................................................................................. 20

Register 1bh: Interrupt Control/Status Register .................................................................................................. 20

Register 1fh: 100BaseTX PHY Controller ........................................................................................................... 20

KS8721B/BT

4

August 2003

KS8721B/BT

Micrel

Absolute Maximum Ratings ..................................................................................................................................... 22

Operating Ratings ..................................................................................................................................................... 22

Electrical Characteristics.......................................................................................................................................... 22

Timing Diagrams ....................................................................................................................................................... 24

Selection of Isolation Transformers ........................................................................................................................ 30

Selection of Reference Crystals............................................................................................................................... 30

Package Outline and Dimensions ............................................................................................................................ 31

August 2003

5

KS8721B/BT

Micrel

Pin Description

Pin Number

Pin Name

Type^{(Note 1)}

Pin Function

1

MDIO

MDC

I/O

Management Interface (MII) Data I/O: This pin requires an external 10K pull-up

resistor.

2

3

I

Management Interface (MII) Clock Input: This pin is synchronous to the MDIO

data interface

RXD3/

PHYAD1

Ipd/O

MII Receive Data Output: RXD [3..0], these bits are synchronous with RXCLK.

When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII.

RXD [3..0] is invalid when RXDV is de-asserted. The pull-up/pull-down value is

latched as PHYADDR [1] during reset. See “Strapping Options” section for

details.

4

5

6

RXD2/

PHYAD2

Ipd/O

MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [2]

during reset. See “Strapping Options” section for details.

RXD1/

PHYAD3

MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [3]

during reset. See “Strapping Options” section for details.

RXD0/

PHYAD4

MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [4]

during reset. See “Strapping Options” section for details.

7

8

9

VDDIO

GND

Pwr

GND

Ipd/O

Digital IO 2.5 /3.3V tolerance power supply.

Ground.

RXDV/

CRSDV/

MII Receive Data Valid Output: The pull-up/pull-down value is latched as

pcs_lpbk during reset. See “Strapping Options” section for details.

PCS_LPBK

10

11

RXC

O

MII Receive Clock Output: Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps.

RXER/ISO

Ipd/O

MII Receive Error Output: The pull-up/pull-down value is latched as ISOLATE

during reset. See “Strapping Options” section for details.

12

13

14

15

GND

VDDC

TXER

GND

Pwr

Ground.

Digital core 2.5V only power supply.

MII Transmit Error Input.

Ipd

TXC/

Ipu/O

MII Transmit Clock Output: RMII Reference Clock Input.

REFCLK

16

17

18

19

20

21

TXEN

TXD0

Ipd

MII Transmit Enable Input

MII Transmit Data Input

TXD1

Ipd

TXD2

Ipd

TXD3

Ipd

COL/RMII

Ipd/O

MII Collision Detect Output: The pull-up/pull-down value is latched as RMII select

during reset. See “Strapping Options” section for details.

24

VDDIO

Pwr

Digital IO 2.5/3.3V tolerance power supply.

Note 1. Pwr = power supply

GND = ground

I = input

O = output

I/O = bi-directional

Gnd = ground

Ipu = input w/ internal pull-up

Ipd = input w/ internal pull-down

Ipd/O = input w/ internal pull-down during reset, output pin otherwise

Ipu/O = input w/ internal pull-up during reset, output pin otherwise

PU = strap pin pull-up

PD = strap pin pull-down

NC = No connect

KS8721B/BT

6

August 2003

KS8721B/BT

Micrel

Pin Number

Pin Name

Type^{(Note 1)}Pin Function

25

INT#/

Ipu/O

Management Interface (MII) Interrupt Out: Latched as PHYAD[0] during power up

PHYAD0

/reset. See “Strapping Options” section for details.

22

CRS/

RMII_BTB

Ipd/O

MII Carrier Sense Output: The pull-up/pull-down value is latched as RMII BTB

during reset when RMII mode is selected. See “Strapping Options” section

for details.

23

26

GND

Ground.

LED0/TEST

Ipu/O

Link/Activity LED Output:

Lnk/Act

No Link

Link

Pin State

LED Definition

“off”

H

L

“on”

Act

—

“Toggle”

The external pull-down enable test mode and only used for the factory test.

27

LED1/

SPD100/

noFEF

Ipu/O

Speed LED Output: Latched as SPEED (Register 0, bit 13) during power-up/reset.

See “Strapping Options” section for details.

Speed

10BT

Pin State

LED Definition

H

L

“off”

“on”

100BT

28

29

LED2/

DUPLEX

Ipu/O

Full-duplex LED Output: Latched as DUPLEX (register 0h, bit 8) during power-up/

reset. See “Strapping Options” section for details.

Duplex

Half

Pin State

LED Definition

H

L

“off”

“on”

Full

LED3/

NWAYEN

Collision LED Output: Latched as ANEG_EN (register 0h, bit 12) during power-up/

reset. See “Strapping Options” section for details.

Collison

Pin State

LED Definition

No Collision

Collision

H

L

“off”

“on”

30

31

32

33

34

PD#

VDDRX

RX-

Ipu

Power Down. 1 = Normal operation, 0=Power down, Active low.

Analog 2.5V power supply.

Pwr

I

Receive Input: Differential receive input pins for FX, 100BaseTX or 10BaseT.

Receive Input: Differential receive input pin for FX, 100BaseTX or 10BaseT.

RX+

I

FXSD/FXEN

Ipd/O

Fiber Mode Enable / Signal Detect in Fiber Mode. If FXEN = 0, FX mode is

disable. The default is “0”. See “100BT FX Mode” section for more details.

35

36

GND

Ground.

Note 1. Pwr = power supply

GND = ground

I = input

O = output

I/O = bi-directional

Ipu = input w/ internal pull-up

Ipd = input w/ internal pull-down

Ipd/O = input w/ internal pull-down during reset, output pin otherwise

Ipu/O = input w/ internal pull-up during reset, output pin otherwise

PU = strap pin pull-up

PD = strap pin pull-down

NC = No connect

August 2003

7

KS8721B/BT

Micrel

Pin Number

Pin Name

REXT

VDDRCV

GND

Type^{(Note 1)}Pin Function

37

38

39

40

41

42

43

44

45

46

47

48

I

External resistor (6.49kΩ) connects to REXT and GNDRX.

Pwr

GND

O

Analog 2.5V power supply.

Ground

TX-

Transmit Outputs: Differential transmit output for 100BaseTX/FX or 10BaseT.

TX+

O

Transmit Outputs: Differential transmit output for FX, 100BaseTX/FX or 10BaseT.

Transmitter 2.5V power supply.

VDDTX

GND

Pwr

GND

O

Ground.

GND

Ground.

XO

XTAL feedback: Used with XI for Xtal application.

Crystal Oscillator Input: Input for a crystal or an external 25MHz clock

Analog PLL 2.5V power supply.

XI

I

VDDPLL

RST#

Pwr

Ipu

Chip Reset: Active low, minimum of 50µs pulse is required

Note 1. Pwr = power supply

GND = ground

I = input

O = output

I/O = bi-directional

Ipu = input w/ internal pull-up

Ipd = input w/ internal pull-down

Ipd/O = input w/ internal pull-down during reset, output pin otherwise

Ipu/O = input w/ internal pull-up during reset, output pin otherwise

PU = strap pin pull-up

PD = strap pin pull-down

NC = No connect

KS8721B/BT

8

August 2003

KS8721B/BT

Micrel

Strapping Options^{(Note 1)}

Pin Number

Pin Name

Type^{(Note 2)}Description

6,5,

4,3

PHYAD[4:1]/

RXD[0:3]

Ipd/O

Ipu/O

PHY Address latched at power-up/reset. The default PHY address is 00001.

25

PHYAD0/

INT#

9

PCS_LPBK/

RXDV

Ipd/O

Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.

11

21

22

ISO/RXER

RMII/COL

Ipd/O

Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.

Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.

Enable RMII_BTB mode at power-up/reset. PD (default) = Disable, PU = Enable.

RMII_BTB

CRS

27

SPD100/

No FEF/

LED1

Ipu/O

Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default)

= 100Mbps. If SPD100 is asserted during power-up/reset, this pin also latched as

the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0

means no Far_End _Fault.)

28

DUPLEX/

LED2

Ipu/O

Latched into Register 0h bit 8 during power-up/reset. PD = Half duplex, PU

(default) = Full duplex. If Duplex is pulled up during reset, this pin also latched as

the Duplex support in register 4h.

29

30

NWAYEN/

LED3

Ipu/O

Ipu

Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/

reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.

PD#

Power Down Enable. PU (default) = Normal operation, PD = Power down mode.

Note 1. Strap-in is latched during power-up or reset.

Note 2. Ipu = input w/ internal pull-up

Ipd = input w/ internal pull-down

Ipd/O = input w/ internal pull-down during reset, output pin otherwise

Ipu/O = input w/ internal pull-up during reset, output pin otherwise

PU = strap pin pull-up

PD = strap pin pull-down

August 2003

9

KS8721B/BT

Micrel

Pin Configuration

MDIO

MDC

1

2

3

4

5

6

7

8

9

48 RST#

47 VDDPLL

46 XI

R3D3/PHYAD1

RXD2/PHYAD2

RXD1/PHYAD3

RXD0/PHYAD4

VDDIO

45 XO

44 GND

43 GND

42 VDDTX

41 TX+

GND

RXDV/PCS_LPBK

40 TX-

RXC 10

RXER/ISO 11

GND 12

39 GND

38 VDDRCV

37 REXT

48 47 46 45 44 43 42 4140 39 38 37

36

35

34

33

32

31

30

29

28

27

GND

FXSD/FXEN

RX+

RX—

VDDRX

MDIO

MDC

1

2

3

4

5

6

7

8

9

VDDC 13

36 GND

RXD3/PHYAD1

RXD2/PHYAD2

RXD1/PHYAD3

RXD0/PHYAD4

VDDIO

GND

RXDV/PCS_LPBK

RXC

TXER 14

35 GND

TXC/REF_CLK 15

TXEN 16

34 FXSD/FXEN

33 RX+

PD#

LED3/NWAYEN

LED2/DUPLEX

LED1/SPD100

LED0/TEST

INT#/PHYAD0

TXD0 17

32 RX-

10

11

12

TXD1 18

31 VDDRX

30 PD#

26

25

RXER/ISO

GND

TXD2 19

TXD3 20

29 LED3/NWAYEN

28 LED2/DUPLEX

27 LED1/SPD100

26 LED0/TEST

25 INT#/PHYAD0

13 14 15 16 17 18 19 20 21 22 23 24

COL/RMII 21

CRS/RMII_BTB 22

GND 23

VDDIO 24

48-Pin TQFP (TQ)

48-Pin SSOP (SM)

KS8721B/BT

10

August 2003

KS8721B/BT

Micrel

Introduction

100BaseTX Transmit

The 100BaseTX transmit function performs parallel to serial conversion, NRZ to NRZI conversion, MLT-3 encoding and

transmission. The circuitry starts with a parallel to serial conversion, which converts the 25MHz, 4-bit nibbles into a 125 MHz

serial bit stream. The incoming data is clocked in at the positive edge of the TXC signal. The serialized data is further converted

from NRZ to NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 6.49kΩ

resistorforthe1:1transformerratio. Ithasatypicalrise/falltimesof4nsandcompliestotheANSITP-PMDstandardregarding

amplitude balance, overshoot and timing jitters. The wave-shaped 10BaseT output driver is also incorporated into the

100BaseTX driver.

100BaseTX Receive

The 100BaseTX receive function performs adaptive equalization, DC restoration, MLT-3 to NRZI conversion, data and clock

recovery, NRZI to NRZ conversion, and serial to parallel conversion. The receiving side starts with the equalization filter to

compensate inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion are a

function of the length of the cable, the equalizer has to adjust its characteristic to optimize the performance. In this design, the

variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable

characteristics, then tunes itself for optimization. This is an ongoing process and can self adjust against the environmental

changes such as temperature variations.

The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to

compensate effect of base line wander and improve the dynamic range. The differential data conversion circuit converts the

MLT3 format back to NRZI. The slicing threshold is also adaptive.

The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to

converttheNRZIsignalintotheNRZformat.Finally,theNRZserialdataisconvertedto4-bitparallel4Bnibbles.Asynchronized

25MHz RXC is generated so that the 4B nibbles is clocked out at the negative edge of RCK25 and is valid for the receiver at

the positive edge. When no valid data is present, the clock recovery circuit is locked to the 25MHz reference clock and both

TXC and RXC clocks continue to run.

PLL Clock Synthesizer

TheKS8721B/BTgenerates125MHz,25MHzand20MHzclocksforsystemtiming.Aninternalcrystaloscillatorcircuitprovides

the reference clock for the synthesizer.

Scrambler/De-scrambler (100BaseTX only)

The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander.

10BaseT Transmit

When TXEN (transmit enable) goes high, data encoding and transmission will begin. The KS8721B/BT will continue to encode

and transmit data as long as TXEN remains high. The data transmission will end when TXEN goes low. The last transition

occurs at the boundary of the bit cell if the last bit is zero, or at the center of the bit cell if the last bit is one. The output driver

is incorporated into the 100Base driver to allow transmission with the same magnetics. They are internally wave-shaped and

pre-emphasized into outputs with a typical 2.5V amplitude. The harmonic contents are at least 27dB below the fundamental

when driven by an all-ones Manchester-encoded signal.

10BaseT Receive

On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a

PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A

squelch circuit rejects signals with levels less than 300mV or with short pulse widths in order to prevent noises at the RX+ or

RX- input from falsely trigger the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal

and the KS8721B/BT decodes a data frame. This activates the carrier sense (CRS) ad RXDV signals and makes the receive

data (RXD) available. The receive clock is maintained active during idle periods in between data reception.

SQE and Jabber Function (10BaseT only)

In 10BaseT operation, a short pulse will be put out on the COL pin after each packet is transmitted. This is required as a test

of the 10BaseT transmit/receive path and is called SQE test. The 10BaseT transmitter will be disabled and COL will go high

if TXEN is High for more than 20ms (Jabbering). If TXEN then goes low for more than 250ms, the 10BaseT transmitter will be

re-enabled and COL will go Low.

Auto-Negotiation

The KS8721B/BT performs auto-negotiation by hardware strapping option (pin 29) or software (Register 0.12). It will

automatically choose its mode of operation by advertising its abilities and comparing them with those received from its link

partner whenever auto-negotiation is enabled. It can also be configured to advertise 100BaseTX or 10BaseT in either full- or

half-duplex mode (please refer to “Auto-Negotiation” ). The auto-negotiation is disabled in the FX mode.

August 2003

11

KS8721B/BT

Micrel

During auto-negotiation, the contents of Register 4, coded in Fast Link Pulse (FLP), will be sent to its link partner under the

conditionsofpower-on,link-lossorre-start.Atthesametime,theKS8721B/BTwillmonitorincomingdatatodetermineitsmode

of operation. Parallel detection circuit will be enabled as soon as either 10BaseT NLP (Normal Link Pulse) or 100BaseTX idle

is detected. The operation mode is configured based on the following priority:

Priority 1: 100BaseTX, full-duplex

Priority 2: 100BaseTX, half-duplex

Priority 3: 10BaseT, full-duplex

Priority 4: 10BaseT, half-duplex

When the KS8721B/BT receives a burst of FLP from its link partner with 3 identical link code words (ignoring acknowledge bit),

it will store these code words in Register 5 and wait for the next 3 identical code words. Once the KS8721B/BT detects the

second code words, it then configures itself according to above-mentioned priority. In addition, the KS8721B/BT also checks

100BaseTXidleor10BaseTNLPsymbol. Ifeitherisdetected, theKS8721B/BTautomaticallyconfigurestomatchthedetected

operating speed.

MII Management Interface

The KS8721B/BT supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input / Output

(MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KS8721B/BT. The MDIO

interface consists of the following:

• A physical connection including a data line (MDIO), a clock line (MDC) and an optional interrupt line (INTRPT)

• A specific protocol that runs across the above-mentioned physical connection and it also allows one controller to

communicate with multiple KS8721B/BT devices. Each KS8721B/BT assigned an MII address between 0 and 31

by the PHYAD inputs.

• An internal addressable set of fourteen 16-bit MDIO registers. Register [0:6] are required and their functions are

specified by the IEEE 802.3 specifications. Additional registers are provided for expanded functionality.

TheINTPRTpinfunctionsasamanagementdatainterruptintheMII. AnactiveLoworHighinthispinindicatesastatuschange

ontheKS8721B/BTbasedon1fh.9levelcontrol.Registerbitsat1bh[15:8]aretheinterruptenablebits.Registerbitsat1bh[7:0]

are the interrupt condition bits. This interrupt is cleared by reading Register 1bh.

MII Data Interface

The data interface consists of separate channels for transmitting data from a 10/100 802.3 compliant Media Access Controller

(MAC) to the KS8721B/BT, and for receiving data from the line. Normal data transmission is implemented in 4B Nibble Mode

(4-bit wide nibbles).

Transmit Clock (TXC): The transmit clock is normally generated by the KS8721B/BT from an external 25MHz reference

source at the X1 input. The transmit data and control signals must always be synchronized to the TXC by the MAC. The

KS8721B/BT normally samples these signals on the rising edge of the TXC.

Receive Clock (RXC): For 100BaseTX links, the receive clock is continuously recovered from the line. If the link goes down,

and auto-negotiation is disabled, the receive clock operates off the master input clock (X1 or TXC). For 10BaseT links, the

receive clock is recovered from the line while carrier is active, and operates from the master input clock when the line is idle.

The KS8721B/BT synchronizes the receive data and control signals on the falling edge of RXC in order to stabilize the signals

at the rising edge of the clock with 10ns setup and hold times.

Transmit Enable: The MAC must assert TXEN at the same time as the first nibble of the preamble, and de-assert TXEN after

the last bit of the packet.

Receive Data Valid: The KS8721B/BT asserts RXDV when it receives a valid packet. Line operating speed and MII mode

will determine timing changes in the following way:

• For 100BaseTX link with the MII in 4B mode, RXDV is asserted from the first nibble of the preamble to the last nibble

of the data packet.

• For 10BaseT links, the entire preamble is truncated. RXDV is asserted with the first nibble of the SFD “ 5D” and

remains asserted until the end of the packet.

Error Signals: Whenever the KS8721B/BT receives an error symbol from the network, it asserts RXER and drives “1110”

(4B) on the RXD pins. When the MAC asserts TXER, the KS8721B/BT will drive “H” symbols (a Transmit Error define in the

IEEE 802.3 4B/5B code group) out on the line to force signaling errors.

Carrier Sense (CRS): For 100TX links, a start-of-stream delimiter, or /J/K symbol pair causes assertion of Carrier Sense

(CRS). An end-of-stream delimiter, or /T/R symbol pair causes de-assertion of CRS. The PMA layer will also de-assert CRS

if IDLE symbols are received without /T/R, yet in this case RXER will be asserted for one clock cycle when CRS is de-asserted.

For 10T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an end-of-frame (EOF)

marker.

KS8721B/BT

12

August 2003

KS8721B/BT

Micrel

Collision: Whenever the line state is half-duplex and the transmitter and receiver are active at the same time, the KS8721B/

BT asserts its collision signal, which is asynchronous to any clock.

RMII (Reduced MII) Data Interface

RMII interface specifies a low pin count (Reduced) Media Independent Interface (RMII) intended for use between Ethernet

PHYs and Switch or Repeater ASICs. It is fully compliant with IEEE 802.3u [2].

This interface has the following characteristics:

• It is capable of supporting 10Mbps and 100Mbps data rates.

• A single clock reference is sourced from the MAC to PHY (or from an external source).

• It provides independent 2-bit wide (di-bit) transmit and receive data paths.

• It uses TTL signal levels, compatible with common digital CMOS ASIC processes.

RMII Signal Definition

Direction

Signal Name

(w/ respect to the PHY)

(w/ respect to the MAC)

Use

REF_CLK

Input

Input or Output

Synchronous clock reference for receive, transmit and

control interface

CRS_DV

RXD[1:0]

TX_EN

Output

Input

Carrier Sense/Receive Data Valid

Receive Data

Input

Output

Transit Enable

TXD[1:0]

RX_ER

Input

Output

Transit Data

Output

Input (Not Required)

Receive Error

Note 1. Unused MII signals, TXD[3:2], TXER need to tie to GND when RMII is using.

Reference Clock (REF_CLK)

REF_CLK is a continuous 50MHz clock that provides the timing reference for CRS_DV, RXD[1:0], TX_EN, TXD[1:0], and

RX_E. REF_CLK is sourced by the MAC or an external source. Switch implementations may choose to provide REF_CLK as

an input or an output depending on whether they provide a REF_CLK output or rely on an external clock distribution device.

Each PHY device shall have an input corresponding to this clock but may use a single clock input for multiple PHYs

implemented on a single IC.

Carrier Sense/Receive Data Valid (CRS_DV)

CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is, in

10BASE-Tmode,whensquelchispassedorin100BASE-Xmodewhen2non-contiguouszeroesin10bitsaredetectedcarrier

is said to be detected.

Loss of carrier shall result in the de-assertion of CRS_DV synchronous to REF_CLK. So long as carrier criteria are being met,

CRS_DV shall remain asserted continuously from the first recovered di-bit of the frame through the final recovered di-bit and

shall be negated prior to the first REF_CLK that follows the final di-bit.

ThedataonRXD[1:0]isconsideredvalidonceCRS_DVisasserted.However,sincetheassertionofCRS_DVisasynchronous

relative to REF_CLK, the data on RXD[1:0] shall be “00” until proper receive signal decoding takes place (see definition of

RXD[1:0] behavior).

Receive Data [1:0] (RXD[1:0])

RXD[1:0] shall transition synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers

two bits of recovered data from the PHY. In some cases (e.g. before data recovery or during error conditions) a pre-determined

value for RXD[1:0] is transferred instead of recovered data. RXD[1:0] shall be “00” to indicate idle when CRS_DV is de-

asserted. Values of RXD[1:0] other than “00” when CRS_DV is de-asserted are reserved for out-of-band signalling (to be

defined). Values other than “00” on RXD[1:0] while CRS_DV is de-asserted shall be ignored by the MAC/repeater. Upon

assertion of CRS_DV, the PHY shall ensure that RXD[1:0]=00 until proper receive decoding takes place.

Transmit Enable (TX_EN)

Transmit Enable TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] on the RMII for trans-mission. TX_EN shall

be asserted synchronously with the first nibble of the preamble and shall remain asserted while all di-bits to be transmitted are

presented to the RMII. TX_EN shall be negated prior to the first REF_CLK following the final di-bit of a frame. TX_EN shall

transition synchronously with respect to REF_CLK.

August 2003

13

KS8721B/BT

Micrel

Transmit Data [1:0] (TXD[1:0])

Transmit Data TXD[1:0] shall transition synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are

accepted for transmission by the PHY. TXD[1:0] shall be “00” to indicate idle when TX_EN is de-asserted. Values of TXD[1:0]

other than “00” when TX_EN is de-asserted are reserved for out-of-band signalling (to be defined). Values other than “00” on

TXD[1:0] while TX_EN is deasserted shall be ignored by the PHY.

Collision Detection

Since the definition of CRS_DV and TX_EN both contain an accurate indication of the start of frame, the MAC can reliably

regenerate the COL signal of the MII by ANDing TX_EN and CRS_DV.

During the IPG time following the successful transmission of a frame, the COL signal is asserted by some transceivers as a

self-test. The Signal Quality Error (SQE) function will not be supported by the reduced MII due to the lack of the COL signal.

Historically, SQE was present to indicate that a transceiver located physically remote from the MAC was functioning. Since

the reduced MII only supports chip-to-chip connections on a PCB, SQE functionality is not required.

RX_ER

The PHY shall provide RX_ER as an output according to the rules specified in IEEE 802.3u [2] (see Clause 24, Figure 24-11

- Receive State Diagram). RX_ER shall be asserted for one or more REF_CLK periods to indicate that an error (e.g. a coding

error or any error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sublayer) was

detectedsomewhereintheframepresentlybeingtransferredfromthePHY.RX_ERshalltransitionsynchronouslywithrespect

to REF_CLK. While CRS_DV is de-asserted, RX_ER shall have no effect on the MAC.

RMII AC Characteristics

Symbol

Parameter

Min

Typ

Max

Units

MHz

%

REF_CLK Frequency

REF_CLK Duty Cycle

50

35

4

65

t_SU

t_H

TXD[1:0]. TX_EN, RXD[1:0], CRS_DV,

RX_ER Data Set-Up to REF_CLK Rising

ns

TXD[1:0]. TX_EN, RXD[1:0], CRS_DV,

RXER Data Hold from REF_CLK

Rising Edge

2

ns

KS8721B/BT

14

August 2003

KS8721B/BT

Micrel

Auto Crossover (Auto MDI/MDI-X)

Automatic MDI/MDI-X configuration is intended to eliminate the need for crossover cables between similar devices. The

assignment of pin-outs for a 10/100 BASE-T crossover function cable is shown below.

This feature can eliminate the confusion in real applications so both straight cable and crossover cable can be used. This

feature is controlled by register 1f:13. See “Register 1fh–100BaseTX PHY Controller” section for details.

10/100 Base-T

Media Dependent Interface

10/100 Base-T

Media Dependent Interface

1

Transmit Pair

Receive Pair

2

3

4

Receive Pair

Transmit Pair

5

6

7

8

6

7

8

Modular Connector

(RJ45)

Modular Connector

(RJ45)

HUB

(Repeater or Switch)

NIC

Figure 1. Straight Through Cable

10/100 BASE-T

Media Dependent Interface

10/100 Base-T

Media Dependent Interface

1

Receive Pair

2

3

4

Transmit Pair

5

6

7

8

6

7

8

Modular Connector (RJ45)

HUB

(Repeater or Switch)

HUB

(Repeater or Switch)

Figure 2. Crossover Cable

August 2003

15

KS8721B/BT

Micrel

Power Management

The KS8721B/BT offers the following modes for power management:

• Power Down Mode: This mode can be achieved by writing to Register 0.11 or pulling pin 30 PD# Low.

• Power Saving Mode: This mode can be disabled by writing to Register 1fh.10. The KS8721B/BT will then turn off

everything except for the Energy Detect and PLL circuits when the cable is not installed. In other words, the

KS8721B/BT will shutdown most of the internal circuits to save power if there is no link. Power saving mode will be

in his most effective state when auto-negotiation mode is enable.

100BT FX Mode

100BT FX mode is activated when FXSD/FXEN is higher 0.6V (This pin has a default pull down). Under this mode, the auto-

negotiation and auto-MDIX features are disabled.

In fiber operation FXSD pin should connect to the SD (signal detect) output of the fiber module. The internal threshold of FXSD

is around 1/2 V

±50mV (1.25V ±0.05V). Above this level, it is considered fiber signal detected, and the operation is

DD

summarized in the following table:

FXSD/FXEN

Condition

Less than 0.6V

100TX mode

Less than 1.25V,

FX mode

but greater than 0.6V

No signal detected

FEF generated

Greater than 1.25

FX mode

signal detected

Table 1. 100BT FX Mode

To ensure a proper operation, the swing of fiber module SD should cover the threshold variation. A resistive voltage divider

is recommended to adjust the SD voltage range.

FEF (Far End Fault), repetition of a special pattern which consists of 84-one and 1-zero, is generated under “FX mode with

no signal detected.” The purpose of FEF is to notify the sender of a faulty link. When receiving a FEF, the LINK will go down

toindicateafault,evenwithfibersignaldetected.ThetransmitterdoesnotaffectbyreceivingaFEFandstillsendsoutitsnormal

transmit pattern from MAC. FEF can be disabled by strapping pin 27 low. Refer to “Strapping Options” section.

Media Converter Operation

KS8721B/BT is capable of performing media conversion with 2 parts in a back to back RMII loop-back mode as indicated in

the diagram. Both parts are in RMII mode and with RMII BTB asserted (pin 21 and 22 strapped high). One part is operating

at TX mode and the other in FX mode. Both parts can share a common 50MHz oscillator.

Under this operation, auto-negotiation on the TX side will prohibit 10baseT link up. TXD2, active High, can disable transmitter

and set it at tri-state. RXD2 serves as energy detection can indicate if there is line signal detected. TXD3 should tied low and

RXD3 let float. Please contact Micrel FAE for Application Note.

Vcc

21 22

Rx +/-

Tx +/-

RxD

KS8721B

TxD

TxC/

Ref_CLK

OSC

50 MHz

TxC/

Ref_CLK

FTx

FRx

TxD

KS8721B

(Fiber Mode)

RxD

34

21 22

Vcc

To the SD pin of the

Fiber Module

Figure 3. Fiber Module

KS8721B/BT

16

August 2003

KS8721B/BT

Micrel

Register Map

Register No.

Description

0h

1h

Basic Control Register

Basic Status Register

2h

PHY Identifier I

3h

PHY Identifier II

4h

Auto-Negotiation Advertisement Register

Auto-Negotiation Link Partner Ability Register

Auto-Negotiation Expansion Register

Auto-Negotiation Next Page Register

Link Partner Next Page Ability

RXER Counter Register

5h

6h

7h

8h

15h

1bh

1fh

Interrupt Control/Status Register

100BaseTX PHY Control Register

Address

Name

Description

Mode^{(Note 1)}Default

Register 0h - Basic Control

0.15

0.14

0.13

Reset

1 = software reset. Bit is self-clearing

RW/SC

RW

0

Loop-back

1 = loop-back mode; 0 = normal operation

Speed Select (LSB)

1 = 100Mbps; 0 = 10Mbps

RW

Set by

Ignored if Auto-Negotiation is enabled (0.12 = 1)

SPD100

0.12

Auto-Negotiation Enable

1 = enable auto-negotiation process (override 0.13 and 0.8)

0 = disable auto-negotiation process

RW

Set by

NWAYEN

0.11

0.10

Power Down

Isolate

1 = power down mode; 0 = normal operation

RW

0

1 = electrical isolation of PHY from MII and TX+/TX-

0 = normal operation

Set by ISO

0.9

0.8

Restart Auto-Negotiation 1 = restart auto-negotiation process

0 = normal operation. Bit is self-clearing

RW/SC

RW

0

Duplex Mode

1 = full duplex; 0 = half duplex

Set by

DUPLEX

0.7

Collision Test

Reserved

1 = enable COL test; 0 = disable COL test

RW

RO

0

0.6:1

0.0

Disable

Transmitter

0 = enable transmitter

1 = disable transmitter

R/W

Register 1h - Basic Status

1.15

1.14

100BaseT4

1 = T4 capable; 0 = not T4 capable

RO

0

1

100BaseTX Full Duplex

1 = capable of 100BaseX full duplex

0 = not capable of 100BaseX full duplex

1.13

1.12

1.11

100BaseTX Half Duplex

10BaseT Full Duplex

10BaseT Half Duplex

1 = capable of 100BaseX half duplex

0 = not capable of 100BaseX half duplex

RO

1

1 = 10Mbps with full duplex

0 = no 10Mbps with full duplex capability

1 = 10Mbps with half duplex

0 = no 10Mbps with half duplex capability

Note 1. RW: Read/Write, RO: Read only, SC: Self clear, LH: Latch High, LL: Latch Low. Some of the default values are set by strap-in. See

“Srapping Options.”

August 2003

17

KS8721B/BT

Micrel

Address Name

Description

Mode^{(Note 1)}Default

1.10:7

1.6

Reserved

No Preamble

RO

0

1

0

1 = preamble suppression; 0 = normal preamble

1.5

Auto-Negotiation Complete 1 = auto-negotiation process completed

0 = auto-negotiation process not completed

1.4

1.3

Remote Fault

1 = remote fault; 0 = no remote fault

RO/LH

RO

0

1

Auto-Negotiation Ability

1 = capable to perform auto-negotiation

0 = unable to perform auto-negotiation

1.2

1.1

1.0

Link Status

1 = link is up; 0 = link is down

RO/LL

0

1

Jabber Detect

Extended Capability

1 = jabber detected; 0 = jabber not detected. Default is Low RO/LH

1 = supports extended capabilities registers RO

Register 2h - PHY Identifier 1

2.15:0 PHY ID Number

Assigned to the 3rd through 18th bits of the Organizationally RO

0022h

Unique Identifier (OUI). Micrel’s OUI is 0010A1 (hex)

Register 3h - PHY Identifier 2

3.15:10

PHY ID Number

Assigned to the 19th through 24th bits of the Organizationally RO

000101

Unique Identifier (OUI). Micrel’s OUI is 0010A1 (hex)

3.9:4

3.3:0

Model Number

Six bit manufacturer’s model number

Four bit manufacturer’s model number

RO

100001

1001

Revision Number

Register 4h - Auto-Negotiation Advertisement

4.15

4.14

4.13

1 = next page capable; 0 = no next page capability.

1 = remote fault supported; 0 = no remote fault

RW

RO

RW

RO

RW

RO

RW

0

Remote Fault

4.12 : 11 Reserved

4.10

4.9

Pause

1 = pause function supported; 0 = no pause function

1 = T4 capable; 0 = no T4 capability

100BaseT4

4.8

100BaseTX Full Duplex

1 = TX with full duplex; 0 = no TX full duplex capability

Set by

SPD100 &

DUPLEX

4.7

4.6

100BaseTX

1 = TX capable; 0 = no TX capability

RW

Set by

SPD100

10BaseT Full Duplex

1 = 10Mbps with full duplex

Set by

0 = no 10Mbps full duplex capability

DUPLEX

4.5

10BaseT

1 = 10Mbps capable; 0 = no 10Mbps capability

[00001] = IEEE 802.3

RW

1

4.4:0

Selector Field

00001

Register 5h - Auto-Negotiation Link Partner Ability

5.15

5.14

RO

0

Acknowledge

1 = link code word received from partner

0 = link code word not yet received

RO

0

5.13

5.12

Remote Fault

Reserved

1 = remote fault detected; 0 = no remote fault

Note 1. RW: Read/Write, RO: Read only, SC: Self clear, LH: Latch High, LL: Latch Low. Some of the default values are set by strap-in. See

“Srapping Options.”

KS8721B/BT

18

August 2003

KS8721B/BT

Micrel

Address Name

Description

Mode^{(Note 1)}Default

5.11:10

Pause

5.10 5 .11

RO

0

No PAUSE

0

1

Asymmetric PAUSE (link partner)

1

0

Symmetric PAUSE

1

Symmetric & Asymmetric PAUSE (local device)

5.9

5.8

5.7

5.6

100 BaseT4

1 = T4 capable; 0 = no T4 capability

RO

0

100BaseTX Full Duplex

100BaseTX

1 = TX with full duplex; 0 = no TX full duplex capability

1 = TX capable; 0 = no TX capability

10BaseT Full Duplex

1 = 10Mbps with full duplex

0 = no 10Mbps full duplex capability

5.5

10BaseT

1 = 10Mbps capable; 0 = no 10Mbps capability

[00001] = IEEE 802.3

RO

0

5.4:0

Selector Field

00001

Register 6h - Auto-Negotiation Expansion

6.15:5

6.4

Reserved

RO

0

Parallel Detection Fault

1 = fault detected by parallel detection

0 = no fault detected by parallel detection.

RO/LH

6.3

6.2

Link Partner Next

Page Able

1 = link partner has next page capability

0 = link partner does not have next page capability

RO

0

1

Next Page Able

1 = local device has next page capability

0 = local device does not have next page capability

6.1

6.0

Page Received

1 = new page received; 0 = new page not yet received

RO/LH

RO

0

Link Partner

1 = link partner has auto-negotiation capability

Auto-Negotiation Able

0 = link partner does not have auto-negotiation capability

Register 7h - Auto-Negotiation Next Page

7.15

7.14

7.13

7.12

1 = message page; 0 = unformatted page

RW

RO

RW

0

1

0

Reserved

Message Page

Acknowledge2

1 = will comply with message

0 = cannot comply with message

7.11

Toggle

1 = previous value of the transmitted link code word

equaled logic One; 0 = logic Zero

RO

0

7.10:0

Message Field

11-bit wide field to encode 2048 messages

RW

001

Register 8h - Link Partner Next Page Ability

8.15

8.14

RO

0

Acknowledge

1 = successful receipt of link word

0 = no successful receipt of link word

8.13

8.12

Message Page

Acknowledge2

1 = Message Page; 0 = Unformatted Page

RO

0

1 = able to act on the information

0 = not able to act on the information

8.11

Toggle

1 = previous value of transmitted Link Code Word equal

to logic zero; 0 = previous value of transmitted Link Code

Word equal to logic one

RO

0

8.10:0

Message Field

RO

0

Note 1. RW: Read/Write, RO: Read only, SC: Self clear, LH: Latch High, LL: Latch Low. Some of the default values are set by strap-in. See

“Srapping Options.”

August 2003

19

KS8721B/BT

Micrel

Address Name

Description

Mode^{(Note 1)}Default

Register 15h - RXER Counter

15.15:0

RXER Counter

RX Error counter for the RX_ER in each package

RO

0000

Register 1bh - Interrupt Control/Status Register

1b.15

1b.14

Jabber Interrupt Enable

1 = Enable Jabber Interrupt; 0=Disable Jabber Interrupt

RW

0

Receive Error

Interrupt Enable

1 = Enable Receive Error Interrupt

0 = Disable Receive Error Interrupt

1b.13

1b.12

1b.11

1b.10

1b.9

1b.8

1b.7

1b.6

1b.5

1b.4

1b.3

1b.2

1b.1

1b.0

Page Received

Interrupt Enable

1 = Enable Page Received Interrupt

0 = Disable Page Received Interrupt

RW

RO

0

Parallel Detect Fault

Interrupt Enable

1 = Enable Parallel Detect Fault Interrupt

0 = Disable Parallel Detect Fault Interrupt

Link Partner Acknowledge 1 = Enable Link Partner Acknowledge Interrupt

Interrupt Enable

0 = Disable Link Partner Acknowledge Interrupt

Link Down

Interrupt Enable

1 = Enable Link Down Interrupt

0 = Disable Link Down Interrupt

Remote Fault

Interrupt Enable

1 = Enable Remote Fault Interrupt

0 = Disable Remote Fault Interrupt

Link Up Interrupt Enable

1 = Enable Link Up Interrupt

0 = Disable Link Up Interrupt

Jabber Interrupt

1 = Jabber Interrupt Occurred

0 = Jabber Interrupt Does Not Occurred

Receive Error Interrupt

Page Receive Interrupt

1 = Receive Error Occurred

0 = Receive Error Does Not Occurred

1 = Page Receive Occurred

0 = Page Receive Does Not Occurred

Parallel Detect

Fault Interrupt

1 = Parallel Detect Fault Occurred

0 = Parallel Detect Fault Does Not Occurred

Link Partner

Acknowledge Interrupt

1 = Link Partner Acknowledge Occurred

0 = Link Partner Acknowledge Does Not Occurred

Link Down Interrupt

Remote Fault Interrupt

Link Up Interrupt

1 = Link Down Occurred

0 = Link Down Does Not Occurred

1 = Remote Fault Occurred

0 = Remote Fault Does Not Occurred

1 = Link Up Interrupt Occurred

0 = Link Up Interrupt Does Not Occurred

Register 1fh - 100BaseTX PHY Controller

1f.15:14

1f:13

Reserved

Pairswap Disable

Energy Detect

1 = Disable MDI/MDIX; 0 = Enable MDI/MDIX

R/W

RO

0

1f.12

1 = Presence of Signal on RX+/- Analog Wire Pair

0 = No Signal Setected on RX+/-

1f.11

Force Link

1 = Force Link Pass; 0 = Normal Link Operation

This bit bypasses the control logic and allow transmitter

to send pattern even if there is no link.

R/W

0

1f.10

1f.9

1f.8

1f.7

Power Saving

Interrupt Level

Enable Jabber

1 = Enable Ppower Saving; 0 = Disable

1 = Interrupt Pin Active High; 0 = Active Low

1 = Enable Jabber Counter; 0 = Disable

RW

1

0

1

0

Auto-Negotiation Complete 1 = Auto-Negotiation Complete; 0 = Not Nomplete

Note 1. RW: Read/Write, RO: Read only, SC: Self clear, LH: Latch High, LL: Latch Low. Some of the default values are set by strap-in. See

“Srapping Options.”

KS8721B/BT

20

August 2003

KS8721B/BT

Micrel

Address Name

Description

Mode^{(Note 1)}Default

1f.6

Enable Pause

1 = flow control capable; 0 = no flow control

RO

0

(Flow-Control Result)

1f.5

PHY Isolate

1 = PHY in isolate mode; 0 = not isolated

RO

0

1f.4:2

Operation Mode Indication [000] = still in auto-negotiation

[001] = 10BaseT half duplex

[010] = 100BaseTX half duplex

[011] = default

[101] = 10BaseT full duplex

[110] = 100BaseTX full duplex

[111] = PHY/MII isolate

1f.1

1f.0

Enable SQE Test

1 = enable SQE test; 0 = disable

RW

0

Disable Data Scrambling 1 = disable scrambler; 0 = enable

Note 1. RW: Read/Write, RO: Read only, SC: Self clear, LH: Latch High, LL: Latch Low. Some of the default values are set by strap-in. See

“Srapping Options.”

August 2003

21

KS8721B/BT

Micrel

Absolute Maximum Ratings (Note 1)

Operating Ratings (Note 2)

Supply Voltage

(V

V

(V

, V

,

(V

V

(V

, V

,

DDC DD_PLL DD_TX DD_RCV

) ................................................... –0.5V to +3.0V

) .................................................... –0.5V to +4.0V

) ........................................... +2.375V to +2.625V

) ............... +2.375V to +2.625V or +3.0V to +3.6V

DD_RX

DDIO

Input Voltage ............................................... –0.5V to +4.0V

Output Voltage ............................................ –0.5V to +4.0V

Lead Temperature (soldering, 10 sec.) ..................... 270°C

Ambient Temperature (T ) ........................... –0°C to +70°C

A

Package Thermal Resistance (Note 3)

TQFP (θ ) .....................................................69.64°C/W

JA

SSOP (θ ).....................................................42.91°C/W

JA

Storage Temperature (T ) ....................... –55°C to +150°C

S

Electrical Characteristics (Note 4)

V_DD= 2.5V ±5%; T_A= 0°C to +70°C; unless noted; bold values indicate –40°C ≤ T_A≤ +85°C; unless noted.

Symbol

Parameter

Condition

Min

Typ

Max

Units

Total Supply Current (including TX output driver current)

I_DD1

Normal 100BaseTX

110

150

40

130

180

60

mA

I_DD2

Normal 10BaseT (50% utilization)

Power Saving Mode 100BaseTX

Power Down Mode

I_DD3

I_DD5

5

TTL Inputs

V_IH

Input High Voltage

V_DD(I/O)

V

–0.8

V_IL

Input Low Voltage

Input Current

0.8

10

V

I_IN

V_IN= GND ~ V_DD

–10

µA

TTL Outputs

V_OH

Output High Voltage

I_OH= –4mA

V_DD(I/O)

–0.4

V

V_OL

Output Low Voltage

I_OL= 4mA

0.4

10

V

|I_OZ

|

Output Tr-State Leakage

µA

100BaseTX Receive

R_INRX+/RX– Differential Input

8

kΩ

Resistance

Propagation Delay

from magnetics to RDTX

50

110

ns

100BaseTX Transmit (measured differentially after 1:1 transformer)

V_O

Peak Differential Output Voltage

Output Voltage Imbalance

50Ω from each output to V_DD

0.95

1.05

2

V

V_IMB

t_r, t_t

%

Rise/Fall Time

Rise/Fall Time Imbalance

3

0

5

0.5

ns

100BaseTX Transmit (measured differentially after 1:1 transformer)

Duty Cycle Distortion

Overshoot

±0.5

V

%

5

V_SET

Reference Voltage of ISET

Propagation Delay

Jitters

0.75

45

ns

from TDTX to magentics

60

ns

0.7

1.4

ns_(pk-pk

Note 1. Exceeding the absolute maximum rating may damage the device.

Note 2. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level

(Ground to V ).

DD

Note 3. No HS (heat spreader) in package.

Note 4. Specification for packaged product only.

KS8721B/BT

22

August 2003

KS8721B/BT

Micrel

Symbol

Parameter

Condition

Min

Typ

Max

Units

10BaseTX Receive

R_IN

RX+/RX– Differential

Input Resistance

8

kΩ

V_SQ

Squelch Threshold

5MHz square wave

400

mV

10BaseTX Transmit (measured differentially after 1:1 transformer)

V_P

Peak Differential Output Voltage

Jitters Added

50Ω from each output to V_DD

2.2

2.8

V

±3.5

ns

t_r, t_t

Rise/Fall Time

25

Clock Outputs

X1, X2

Crystal Oscillator

25

MHZ

RXC₁₀₀

RXC₁₀

Receive Clock, 100TX

Receive Clock, 10T

Receive Clock Jitters

Transmit Clock, 100TX

Transmit Clock, 10T

Transmit Clock Jitters

2.5

3.0

25

MHZ

ns_(pk-pk)

MHZ

TXC₁₀₀

TXC₁₀

2.5

1.8

MHZ

ns_(pk-pk)

August 2003

23

KS8721B/BT

Micrel

Timing Diagrams

TXC

t_HD2

t_SU2

TXEN

t_HD1

TXD[3:0]

CRS

t_SU1

t_CRS1

t_CRS2

Valid

Data

TXP/TXM

t_LAT

SQE Timing

TXC

TXEN

COL

t_SQE

t_SQEP

Figure 4. 10BaseT MII Transmit Timing

Symbol

t_SU1

Parameter

Min

10

0

Typ

Max

Units

ns

TXD [3:0] Set-Up to TXC High

TXEN Set-Up to TXC High

TXD [3:0] Hold After TXC High

TXEN Hold After TXC High

t_SU2

ns

t_HD1

ns

t_HD2

0

ns

t_CRS1

t_CRS2

t_LAT

TXEN High to CRS Asserted Latency

TXEN Low to CRS De-Asserted Latency

TXEN High to TXP/TXM Output (TX Latency)

COL (SQE) Delay Aftter TXEN Ae-Asserted

COL (SQE) Pulse Duration

4

8

BT

µs

4

t_SQE

2.5

1.0

t_SQEP

µs

Table 2. 10BaseT MII Transmit Timing Parameters

KS8721B/BT

24

August 2003

KS8721B/BT

Micrel

TXC

t_HD2

t_SU2

TXEN

t_HD1

t_SU1

TXD[3:0],

TXER

Data

In

t_CRS2

t_CRS1

t_LAT

CRS

Symbol

Out

TX+/TX-

Figure 5. 100BaseT MII Transmit Timing

Symbol

t_SU1

Parameter

Min

10

0

Typ

Max

Units

ns

TXD [3:0] Set-Up to TXC High

TXEN Set-Up to TXC High

t_SU2

ns

t_HD1

TXD [3:0] Hold After TXC High

TXER Hold After TXC High

ns

t_HD2

0

ns

t_HD3

TXEN Hold After TXC High

0

ns

t_CRS1

t_CRS2

t_LAT

TXEN High to CRS Asserted Latency

TXEN Low to CRS De-Asserted Latency

TXEN High to TX+/TX– Output (TX Latency)

4

7

BT

Table 3. 100BaseT MII Transmit Timing Parameters

August 2003

25

KS8721B/BT

Micrel

Start of

Stream

End of

Stream

RX+/RX-

CRS

t_CRS1

t_CRS2

RXDV

t_RLAT

t_HD

RXD[3:0]

RXER

t_SU

t_WH

RXC

t_WL

t_P

Figure 6. 100BaseT MII Receivce Timing

Symbol

t_P

Parameter

Min

Typ

Max

Units

ns

RXC Period

40

t_WL

RXC Pulse Width

20

ns

t_WH

ns

t_SU

RXD [3:0], RXER, RXDV Set-Up to Rising Edge of RXC

RXD [3:0], RXER, RXDV Hold from Rising Edge of RXC

CRS to RXD Latency, 4B or 5B Aligned

20

ns

t_HD

ns

t_RLAT

t_CRS1

t_CRS2

1

2

3

BT

ns

“Start of Stream” to CSR Asserted

140

170

“End of Stream” to CSR De-Asserted

ns

Table 4. 100BaseT MII Receive Timing Parameters

KS8721B/BT

26

August 2003

KS8721B/BT

Micrel

FLP

Burst

TX+/TX-

t_FLPW

t_B

TB

Clock

Pulse

Data

Pulse

Clock

Pulse

Data

Pulse

TX+/TX-

t_PW

t_CTD

t_C

TC

Figure 7. Auto-Negotiation/Fast Link Pulse Timing

Symbol

t_BTB

Parameter

Min

Typ

16

Max

Units

ms

ns

FLP Burst to FLP Burst

FLP Burst Width

8

24

t_FLPW

t_PW

2

Clock/Data Pulse Width

100

69

t_CTD

Clock Pulse to Data Pulse

µs

t_CTC

Clock Pulse to Clock Pulse

Number of Clock/Data Pulses per Burst

136

µs

17

33

Table 5. Auto-Negotiation/Fast Link Pulse Timing

August 2003

27

KS8721B/BT

Micrel

t_P

MDC

t_MD1

t_MD2

MDIO

Valid

Data

Valid

Data

(Into Chip)

t_MD3

MDIO

Valid

Data

(Out of Chip)

Figure 8. Serial Management Interface Timing

Symbol

t_P

Parameter

MDC Period

Min

Typ

Max

Units

ns

400

t_MD1

t_MD2

t_MD3

MDIO Set-Up to MDC (MDIO as input)

MDIO Hold after MDC (MDIO as input)

MDC to MDIO Valid (MDIO as output)

10

ns

222

ns

Table 6. Serial Management Interface Timing

KS8721B/BT

28

August 2003

KS8721B/BT

Micrel

Supply

Voltage

tsr

RST_N

tcs tch

Strap-In

Value

trc

Strap-In /

Output Pin

Figure 9. Reset Timing

Symbol

Parameter

Min

10

Typ

Max

Units

ms

ns

t_sr

t_cs

t_ch

t_rc

Stable Supply Voltages to Reset High

Configuration Set-Up Time

Configuration Hold Time

50

ns

Reset to Strap-In Pin Output

50

µs

Table 7. Reset Timing Parameters

August 2003

29

KS8721B/BT

Micrel

Selection of Isolation Transformer^{(Note 1)}

One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-mode

chokeisrecommendedforexceedingFCCrequirements. Thefollowingtablegivesrecommendedtransformercharacteristics.

Characteristics Name

Turns Ratio

Value

Test Condition

1 CT : 1 CT

350µH

0.4µH

Open-Circuit Inductance (min.)

Leakage Inductance (max.)

Inter-Winding Capacitance (max.)

D.C. Resistance (max.)

Insertion Loss (max.)

HIPOT (min.)

100mV, 100 KHz, 8 mA

1MHz (min.)

12pF

0.9Ω

1.0dB

0MHz to 65MHz

1500Vrms

Note 1. The IEEE 802.3u standard for 100BaseTX assumes a transformer loss of 0.5dB. For the transmit line transformer, insertion loss of up to

1.3dB can be compensated by increasing the line drive current by means of reducing the ISET resistor value.

Selection of Reference Crystal

An oscillator or crystal with the following typical characteristics is recommended.

Characteristics Name

Frequency

Value

25.00000

±100

20

Units

MHz

ppm

pF

Frequency Tolerance (max.)

Load Capacitance (max.)

Series Resistance (max.)

25

Ω

Single Port

Magnetic Manufacturer

Number

of Ports

Part Number

Auto MDIX

Yes

Pulse

H1102

1

Bel Fuse

YCL

S558-5999-U7

PT163020

HB726

Yes

Transpower

Delta

Yes

LF8505

Yes

LanKom

LF-H41S

Yes

Table 8. Qualified Transformer Lists

KS8721B/BT

30

August 2003

KS8721B/BT

Micrel

Package Information

48-Pin SSOP (SM)

August 2003

31

KS8721B/BT

Micrel

48-Pin TQFP (TQ)

MICREL, INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com

The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.

Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can

reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into

the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s

use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify

Micrel for any damages resulting from such use or sale.

KS8721B/BT

32

August 2003

型号:	KS8721B
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Active
IHS 制造商：	ROCHESTER ELECTRONICS LLC
零件包装代码：	SSOP
包装说明：	MO-118AA, SSOP-48
针数：	48
Reach Compliance Code：	unknown
风险等级：	5.81
Is Samacsys：	N
JESD-30 代码：	R-PDSO-G48
JESD-609代码：	e0
长度：	15.875 mm
湿度敏感等级：	1
功能数量：	1
端子数量：	48
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：	240
认证状态：	COMMERCIAL
座面最大高度：	2.794 mm
标称供电电压：	2.5 V
表面贴装：	YES
技术：	CMOS
电信集成电路类型：	ETHERNET TRANSCEIVER
温度等级：	COMMERCIAL
端子面层：	TIN LEAD
端子形式：	GULL WING
端子节距：	0.635 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
宽度：	7.493 mm
Base Number Matches：	1

电子百科

产品导航

产品型号KS8721B的概述

产品型号KS8721B的Datasheet PDF文件预览

KS8721B相关产品

KS8721B相关文章

IC37:专业IC行业平台