KTS6027-2应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

Wireless Components

2 Band TV Tuner Mixer-Oscillator-PLL

with unbalanced IF-Amplifier

KTS6027-2, KTS6029-2 Version 2.0

Specification July 2001

Revision History: Current Version: Preliminary Datasheet V 1.1, July 2000

Previous Version:Target Data Sheet

Page

Subjects (major changes since last revision)

(in previous

Version)

(in current

Version)

all

version to 1.1, status to preliminary

circuit diagram modified

4 - 2

4 - 3

5 - 2

4 - 2

4 - 3

5 - 2

circuit diagram modified

Bus input/output SDA max changed to 6V,

Bus input SCL max changed to 6V,

ADC input added

5 - 3

5 - 5

5 - 3

5 - 5

new reference for ESD protection

Current consumption for LOW/MID band and HIGH band added,

tbf’s replaced by data

Charge Pump output voltage VCP = 1.3 V min

5 - 8

5 - 9

5 - 8

5 - 9

Oscillator phsase noise -85 dBc/Hz min, -89 dBc/Hz typ

Revision History: Current Version: Datasheet, V 2.0, July 2001

Previous Version:Preliminary Datasheet V 1.1, July 2000

Page

Subjects (major changes since last revision)

(in previous

Version)

(in current

Version)

all

version to 2.0, preliminary deleted

definition of thermal properties changed

current consumtion changed

5 - 2

5 - 5

5- 2

5 - 5

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Edition 03.99

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KTS6027-2, KTS6029-2

Product Info

Package

General Description The KTS6027-2/KTS6029-2 is a 5 V

mixer/oscillator and synthesizer for

analog and digital TV and VCR tuners.

Features General

ꢀ Suitable for analog and digital ter-

restrial TV tuner

ꢀ Compatible with KTS6027-S or

KTS6029-S in normal mode

ꢀ New features in extended mode

ꢀ Full ESD protection

Mixer/Oscillator

ꢀ High impedance mixer input for

LOW/MID band

PLL

ꢀ Low impedance mixer input for

ꢀ PLL with short lock-in time

HIGH band

ꢀ High voltage VCO tuning output

ꢀ 4 pin oscillator for LOW/MID band

ꢀ 4 pin oscillator for HIGH band

IF-Amplifier

2

ꢀ Fast I C bus

ꢀ 4 NPN bandswitch buffers

ꢀ Internal LOW-MID/HIGH switch

ꢀ Lock-in flag

ꢀ single ended IF preamplifier

ꢀ 75 Ω output impedance

ꢀ Power-down reset

ꢀ 4 programmable reference divider

ratios: 24, 64, 80, 128

ꢀ 4 programmable charge pump cur-

rents

Application

ꢀ The IC is suitable for NTSC tuners in TV- and VCR-sets or CATV set-top

receivers for analog TV and Digital Video Broadcasting.

Ordering Information

Type

Ordering Code

Package

KTS6027-2

KTS6029-2

Q67037-A1162 ( tape and reel)

Q67037-A1163 ( tape and reel)

P-TSSOP-28-1

Wireless Components

Product Info

Specification, July 2001

1

Table of Contents

1

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

2

Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

3

Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

3.2 Internal Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

3.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

3.4 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

4

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19

4.1 KTS6027-2 Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20

4.2 KTS6029-2 Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21

5

Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22

5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23

5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23

5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25

5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26

5.2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31

5.3 I2C Bus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35

5.4 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36

5.4.1 Gain (GV) test Set-up in LOW/MID. . . . . . . . . . . . . . . . . . . . . . . . . . 5-36

5.4.2 Gain (GV) test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36

5.4.3 Matching circuit for optimum noise figure in LOW/MID. . . . . . . . . . . 5-37

5.4.4 Noise Figure Test Set-up in LOW/MID . . . . . . . . . . . . . . . . . . . . . . . 5-37

5.4.5 Noise Figure Test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38

5.4.6 Cross modulation Test Set-up in LOW/MID band. . . . . . . . . . . . . . . 5-38

5.4.7 Cross modulation Test Set-up in HIGH band . . . . . . . . . . . . . . . . . . 5-39

5.4.8 Measurement of fref and fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39

5.5 Electrical Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40

5.5.1 Input admittance (S11) of the LOW/MID band mixer input. . . . . . . . 5-40

5.5.2 Input impedance (S11) of the HIGH band mixer input . . . . . . . . . . . 5-40

5.5.3 Output admittance (S22) of the Mixer output . . . . . . . . . . . . . . . . . . 5-41

5.5.4 Output impedance (S22) of the IF output . . . . . . . . . . . . . . . . . . . . . 5-41

2

Product Description

Contents of this Chapter

2.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

KTS6027-2, KTS6029-2

Product Description

2.1 General Description

The KTS6027-2, KTS6029-2 device combines a digitally programmable phase

locked loop (PLL), with a mixer-oscillator block including two balanced mixers

and oscillators for use in TV and VCR tuners.

The PLL block with four selectable chip addresses forms a digitally programm-

able phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise

setting of the frequency of the tuner oscillator up to 1024 MHz in increments of

31.25, 50, 62.5 or 166.7 kHz. The tuning process is controlled by a micropro-

2

cessor via an I C bus. The device has four output ports. A flag is set when the

2

loop is locked. It can be read by the processor via the I C bus.

The mixer-oscillator block includes two balanced mixers (one mixer with high-

impedance input and one mixer with a balanced low-impedance input), two fre-

quency and amplitude-stable balanced oscillators for LOW/MID and HIGH, an

IF amplifier, a low-noise reference voltage source, and a band switch.

2.2 Features

General

ꢀ Suitable for analog and digital terrestrial TV tuner

ꢀ Compatible with KTS6027-S or KTS6029-S in normal mode

ꢀ New features in extended mode

ꢀ Full ESD protection

Mixer/Oscillator

ꢀ High impedance mixer input for LOW/MID band

ꢀ Low impedance mixer input for HIGH band

ꢀ 4 pin oscillator for LOW/MID band

ꢀ 4 pin oscillator for HIGH band

IF-Amplifier

ꢀ single ended IF preamplifier

ꢀ 75 Ω output impedance

PLL

ꢀ PLL with short lock-in time

ꢀ High voltage VCO tuning output

2

ꢀ Fast I C bus

ꢀ 4 NPN bandswitch buffers

ꢀ Internal LOW-MID/HIGH switch

Wireless Components

2 - 6

Specification, July 2001

KTS6027-2, KTS6029-2

Product Description

ꢀ Lock-in flag

ꢀ Power-down reset

ꢀ 4 programmable reference divider ratios: 24, 64, 80, 128

ꢀ 4 programmable charge pump currents

2.3 Application

ꢀ The IC is suitable for NTSC tuners in TV- and VCR-sets or CATV set-top

receivers for analog TV and Digital Video Broadcasting.

2.4 Package Outlines

P-TSSOP-28-1

Wireless Components

2 - 7

Specification, July 2001

3

Functional Description

Contents of this Chapter

3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

3.2 Internal Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

3.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

3.4 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

3.4.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

3.4.2 Mixer-Oscillator block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

3.4.3 PLL block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

3.4.4 I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

KTS6027-2, KTS6029-2

Functional Description

3.1 Pin Configuration

OSCHIGHIN

OSCHIGHOUT

OSCHIGHIN

1

2

3

4

5

6

7

8

9

28 HIGHIN

27 HIGHIN

26 LOW/MIDIN

25

VCC

OSCLOW/MIDIN

OSCLOW/MIDOUT

24 MIXOUT

23 MIXOUT

22

OSCLOW/MIDOUT

OSCLOW/MIDIN

RFGND

PLLGND

KTS6027-2

21

SDA

20 SCL

19 AS

ADC 10

IFOUT 11

PHIGH 12

VT 13

18 XTAL

17 PFM

16 PMID

15 PLOW

CP 14

KTS6027-2_Pin_config

Figure 3-1

KTS6027-2 Pin Configuration

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

HIGHIN

OSCHIGHIN

OSCHIGHOUT

OSCHIGHIN

2

3

LOW/MIDIN

VCC

4

5

MIXOUT

OSCLOW/MIDIN

6

OSCLOW/MIDOUT

7

PLLGND

SDA

OSCLOW/MIDOUT

KTS6029-2

8

OSCLOW/MIDIN

RFGND

ADC

9

SCL

10

11

12

13

14

AS

XTAL

PFM

IFOUT

PHIGH

VT

PMID

PLOW

CP

KTS6029-2_Pin_config

Figure 3-2

KTS6029-2 Pin Configuration

Wireless Components

3 - 9

Specification, July 2001

KTS6027-2, KTS6029-2

Functional Description

3.2 Internal Pin Configuration

Note: Pin designation refers to KTS6027-2. KTS6029-2 has reversed pinning

Table 3-1 Pin Definition and Function

Pin No. Symbol

Equivalent I/O-Schematic

Average DC voltage

LOW/MID

HIGH

1

2

3

4

5

6

7

8

9

OSCHIGHIN

0.0 V

1.6 V

OSC-

HIGHOUT

0.0 V

1.6 V

2.3 V

1.6 V

0.0 V

2.8 V

1.6 V

0.0 V

2

1

3

4

OSC-

HIGHOUT

OSCHIGHIN

OSCLOW/

MIDIN

OSCLOW/

MIDOUT

6

5

7

8

OSCLOW/

MIDOUT

OSCLOW/

MIDIN

RFGND

analog ground

Wireless Components

3 - 10

Specification, July 2001

KTS6027-2, KTS6029-2

Functional Description

Table 3-1 Pin Definition and Function (continued)

Pin No. Symbol Equivalent I/O-Schematic

Average DC voltage

LOW/MID

HIGH

10

ADC

V

ADC

10

11

IFOUT

2.3 V

11

12

PHIGH

5.0 V

V

CE

12

Wireless Components

3 - 11

Specification, July 2001

KTS6027-2, KTS6029-2

Functional Description

Table 3-1 Pin Definition and Function (continued)

Pin No. Symbol Equivalent I/O-Schematic

Average DC voltage

LOW/MID

HIGH

13

VT

V

T

14

13

14

CP

2.1 V

15

16

17

PLOW

PMID

PFM

5 V or V

5 V

CE

15

16

17

5 V or V

CE

18

XTAL

3.0 V

18

Wireless Components

3 - 12

Specification, July 2001

KTS6027-2, KTS6029-2

Functional Description

Table 3-1 Pin Definition and Function (continued)

Pin No. Symbol Equivalent I/O-Schematic

Average DC voltage

LOW/MID

HIGH

19

AS

V

AS

19

20

SCL

n.a.

20

21

SDA

n.a.

21

22

PLLGND

digital ground

0.0 V

Wireless Components

3 - 13

Specification, July 2001

KTS6027-2, KTS6029-2

Functional Description

Table 3-1 Pin Definition and Function (continued)

Pin No. Symbol Equivalent I/O-Schematic

Average DC voltage

LOW/MID

HIGH

23

MIXOUT

3.8 V

IF Amp.

23

24

MIXOUT

3.8 V

Oscillator

25

26

VCC

supply voltage

5.0 V

1.8 V

5.0 V

0.0 V

LOW/MIDIN

26

27

28

HIGHIN

0.0 V

0.9 V

27

28

Wireless Components

3 - 14

Specification, July 2001

KTS6027-2, KTS6029-2

Functional Description

3.3 Block Diagram

28

(1)

27

(2)

26

(3)

25

(4)

24

(5)

23

(6)

22

(7)

21

(8)

20

(9)

19

(10)

18

(11)

17

16

15

(12) (13) (14)

V_CC

I²C Bus

Ports

RF Input

HIGH

RF Input

LOW/MID

LOW

or MID

FL

Lock

Detector

HIGH

Crystal

Oscillator

Mixer

HIGH

Mixer

LOW/MID

LOW

or MID

ADC

Reference

Divider

HIGH

Prog.

Divider

f_div

f_ref

Phase/

Frequency

Comparator

Oscillator

HIGH

Oscillator

LOW/MID

SAW

Driver

LOW

or MID

CP,

CM,

OS

Charge

Pump

HIGH

(28)

1

(27)

2

(26)

3

(25)

4

(24)

5

(23)

6

(22)

7

(21)

8

(20)

9

(19) (18)

10 11

(17)

12

(16)

13

(15)

14

KTS602729_block_diag

Note: Pin designations in parenthesis refer to KTS6029-2

Figure 3-3

Block Diagram

Wireless Components

3 - 15

Specification, July 2001

KTS6027-2, KTS6029-2

Functional Description

3.4 Circuit Description

3.4.1 General

In the normal mode (see Table 5-7 Test modes on page 32) the IC is compatible with

KTS6027-S / KTS6029-S. An extended mode makes a reference divider ratio

of 24 (see Table 5-8 Reference divider ratio on page 32) and two additional charge pump

currents (see Table 5-9 Charge pump current on page 33) available.

3.4.2 Mixer-Oscillator block

The mixer oscillator section includes two balanced mixers (double balanced

mixer), two balanced oscillators for LOW and / or MID band and HIGH band, an

IF amplifier, a reference voltage source and a band switch.

Filters between tuner input and IC separate the TV frequency signals into two

bands. The band switching in the tuner front-end is done by using two or three

port outputs. In the selected band the signal passes a tuner input stage with

MOSFET amplifier, a double-tuned bandpass filter and is then fed to the bal-

anced mixer input of the IC which has in case of LOW / MID a high-impedance

input and in case of HIGH a low-impedance input. The input signal is mixed

there with the signal from the activated on chip oscillator to the IF frequency

which is filtered out at the balanced high-impedance output pair by means of a

parallel tuned circuit. The following SAW preamplifier has a low output imped-

ance to drive the SAW filter directly.

3.4.3 PLL block

The oscillator signal is internally DC-coupled as a differential signal to the pro-

grammable divider inputs. The signal subsequently passes through a program-

mable divider with ratio N = 256 through 32767 and is then compared in a digital

frequency / phase detector to a reference frequency f = 31.25, 50, 62.5 or

ref

166.7 kHz.

This frequency is derived from an unbalanced, low-impedance 4 MHz crystal

oscillator (pin XTAL) divided by R = 128, 80, 64 or 24.

The phase detector has two outputs that drive two current sources of opposite

polarity as charge pump. If the negative edge of the divided VCO signal appears

prior to the negative edge of the reference signal, the positive current source

pulses for the duration of the phase difference. In the reverse case the negative

current source pulses. If the two signals are in phase, the charge pump output

(CP) goes into the high-impedance state (PLL is locked). An active low-pass fil-

ter integrates the current pulses to generate the tuning voltage for the VCO

Wireless Components

3 - 16

Specification, July 2001

KTS6027-2, KTS6029-2

Functional Description

(internal amplifier, external pull-up resistor at TUNE and external RC circuitry).

The charge pump output is also switched into the high-impedance state if the

control bits T0 = 1 and T1 = 0. Here it should be noted, however, that the tuning

voltage can alter over a long period in the high-impedance state as a result of

self-discharge in the peripheral circuitry. TUNE may be switched off by the con-

trol bit OS to allow external adjustments.

If the VCO is not oscillating the PLL locks to a tuning voltage of 33 V .

By means of the control bits CP, CM, T0 and T1 the pump current can be

switched between four values by software. This programmability permits alter-

ation of the control response time of the PLL in the locked-in state. In this way

different VCO gains can be compensated, for example.

The software-switched ports PLOW, PMID, PHIGH and PFM are general-pur-

pose open-collector outputs. The test bits T0 = 0 and T1 = 1 switches the test

signals f

(i.e.f

/ 64) and f (divided input signal) to PLOW and PMID

ref

XTAL div

respectively.

The lock detector resets the lock flag FL if the width of the charge pump current

pulses is wider than the period of the crystal oscillator (i.e. 250 ns). Hence, if FL

= 1, the maximum deviation of the input frequency from the programmed fre-

quency is given by

∆f = ± I (K

/ f

) (C1+C2) / (C1C2)

P

VCO XTAL

where I is the charge pump current, K

the VCO gain, f

the crystal oscil-

XTAL

P

VCO

lator frequency and C1, C2 the capacitances in the loop filter (see Figure 4-1

KTS6027-2 Evaluation Board on page 20). As the charge pump pulses at i.e. 62.5 kHz (=

f ), it takes a maximum of 16 µs for FL to be reset after the loop has lost lock

ref

state.

Once FL has been reset, it is set only if the charge pump pulse width is less than

250 ns for eight consecutive f periods. Therefore it takes between 128 and

ref

144 µs for FL to be set after the loop regains lock.

3.4.4 I²C-Bus Interface

2

Data is exchanged between the processor and the PLL via the I C bus. The

clock is generated by the processor (input SCL), while pin SDA functions as an

input or output depending on the direction of the data (open collector, external

pull-up resistor). Both inputs have hysteresis and a low-pass characteristic,

2

which enhance the noise immunity of the I C bus.

2

The data from the processor pass through an I C bus controller. Depending on

their function the data are subsequently stored in registers. If the bus is free,

both lines will be in the marking state (SDA, SCL are HIGH). Each telegram

begins with the start condition and ends with the stop condition. Start condition:

SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH

Wireless Components

3 - 17

Specification, July 2001

KTS6027-2, KTS6029-2

Functional Description

while SCL remains HIGH. All further information transfer takes place during

SCL = LOW, and the data is forwarded to the control logic on the positive clock

edge.

The table ”Bit Allocation” (see Table 5-4 Bit Allocation Read / Write on page 31) should be

referred to the following description. All telegrams are transmitted byte-by-byte,

followed by a ninth clock pulse, during which the control logic returns the SDA

line to LOW (acknowledge condition). The first byte is comprised of seven

address bits. These are used by the processor to select the PLL from several

peripheral components (chip select). The LSB bit (R/W) determines whether

data are written into (R/W = 0) or read from (R/W = 1) the PLL.

In the data portion of the telegram during a WRITE operation, the MSB bit of the

first or third data byte determines whether a divider ratio or control information

is to follow. In each case the second byte of the same data type has to follow

the first byte.

If the address byte indicates a READ operation, the PLL generates an acknowl-

edge and then shifts out the status byte onto the SDA line. If the processor gen-

erates an acknowledge, a further status byte is output; otherwise the data line

is released to allow the processor to generate a stop condition. The status word

consists the lock flag and the power-on flag.

Four different chip addresses can be set by appropriate DC level at pin AS (see

Table 5-6 Address selection on page 32).

While applying the supply voltage, a power-on reset circuit prevents the PLL

from setting the SDA line to LOW, which would block the bus. The power-on

reset flag POR is set at power-on and when V falls below 3.2 V. It will be reset

CC

at the end of a READ operation.

Wireless Components

3 - 18

Specification, July 2001

4

Applications

Contents of this Chapter

4.1 KTS6027-2 Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20

4.2 KTS6029-2 Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21

KTS6027-2, KTS6029-2

Applications

4.1 KTS6027-2 Evaluation Board

SDA SCL AS

100p 100p

PFM PMID PLOW

4n7 4n7 4n7

R_Gen= 75

HIGH

Ω

R

_Gen= 75

Ω

V_CC

LOW/

MID

4n7

1:1*)

4 MHz

68p

L4

68p 47n

220 220 220

18p

1n

22p 22p

2p2

27

28

26

25

24

23

22

21

20

19

10

18

11

17

12

16

13

15

14

KTS6027-2

1

2

3

4

5

6

7

8

9

C

47n

2

4n7

1p2 1p2 1p2 1p2 2p7 2p2 2p2 2p7

120p

C

2n2

L2

L1

L3

1

ADC

PHIGH

220

1k

100n

1p

BA892

1n

18p

1k8

3k3

1k

100k

33k 560

47p

2k7

1k8

BB659C

4n7

+ 33 V

R

_Load= 75

IF

Ω

BB659C

2k7

output

10n

KTS6027-2 Application Circuit

Figure 4-1

KTS6027-2 Evaluation Board

Table 4-1 Recommended band limits in MHz

RF input Oscillator

Table 4-1 Coils

turns

1.5

wire

min

55.25

max

min

max

173

407

849

L1

L2

L3

L4

*)

2 mm

0.4 mm

0.5 mm

0.4 mm

0.3 mm

LOW

MID

127.25

101

179

413

3.5

2.5 mm

3.5 mm

133.25 361.25

367.25 803.25

9.5

HIGH

12.5

TOKO B4F Type 617DB-1023

Wireless Components

4 - 20

Specification, July 2001

KTS6027-2, KTS6029-2

Applications

4.2 KTS6029-2 Evaluation Board

10n

+ 33 V

IF

_Load= 75

2k7

47p

2k7

output

Ω

BB659C

R

4n7

BB659C

1k8

18p

1k8

1n

1k

3k3

33k 560

100k

100n

BA892

1p

220

1k

C

2n2

2

ADC

PHIGH

L1

L3

L2

120p

1p2 1p2 1p2 1p2 2p7 2p2 2p2 2p7

C

47n

1

4n7

28

27

26

25

24

23

22

21

20

19

18

11

17

16

13

15

KTS6029-2

1

2

3

4

5

6

7

8

9

10

12

14

2p2

L4

22p 22p

1:1*)

1n

18p

4 MHz

220

100p 100p

220

4n7

220

68p

68p 47n

4n7

V_CC

4n7 4n7 4n7

LOW/

MID

HIGH

R_Gen= 75

Ω

R_Gen= 75 Ω

SDA SCL AS

PFM PMID PLOW

KTS6029-2 Application Circuit

Figure 4-2

KTS6029-2 Evaluation Board

Table 4-1 Recommended band limits in MHz

RF input Oscillator

Table 4-1 Coils

turns

1.5

wire

min

55.25

max

min

max

173

407

849

L1

L2

L3

L4

*)

2 mm

0.4 mm

0.5 mm

0.4 mm

0.3 mm

LOW

MID

127.25

101

179

413

3.5

2.5 mm

3.5 mm

133.25 361.25

367.25 803.25

9.5

HIGH

12.5

TOKO B4F Type 617DB-1023

Wireless Components

4 - 21

Specification, July 2001

5

Reference

Contents of this Chapter

5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23

5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23

5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25

5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26

5.2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31

Table 5-4 Bit Allocation Read / Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31

Table 5-5 Description of symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31

Table 5-6 Address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32

Table 5-7 Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32

Table 5-8 Reference divider ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32

Table 5-9 Charge pump current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33

Table 5-10 Bandswitching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33

Table 5-11 A/D converter levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34

5.3 I2C Bus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35

5.4 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36