L4923
ELECTRICAL CHARACTERISTICS (V = 14. 4V, – 40°C ≤ TJ ≤ + 125°C unless otherwise specified)
i
Symbol
Parameter
Operating Input Voltage
Output Voltage
Test Conditions
(*) Note 1
Io = 0mA to 1A
Min.
Typ.
Max.
Unit
Vi
6
26
V
Vo
4.8
4.9
5.2
5.1
V
V
T = 25 C
°
J
Line Regulation
Vi = 6 to 26V; IO = 10mA
5
25
mV
dB
V
∆
Line
SVR
Supply Voltage Rejection
Io = 700mA
55
f = 120Hz; Co = 47µF
Vi = 12Vdc + 5Vpp
Load Regulation
Dropout Voltage
Io = 10mA to 1A
15
50
mV
V
V
∆
LOAD
Vi – Vo
0.45
0.70
0.90
T = 25 C, I = 1A
°
J
O
Over Full T, Io = 1A
V
Iq
Quiescent Current
Io = 10mA
Io = 1A
Active High Inhibit
7
25
0.30
12
70
0.65
mA
mA
mA
ISC
Short Circuit Current
Supply Volt. Rej.
1.8
60
A
SVR
Io = 350mA ; f = 120Hz
50
dB
C = 100 F ; V = 12V 5V
µ
±
o
i
pp
VR
VRT peak
IR
Rset Output Saturation Voltage 1.5V < VO < VRT (off), IR = 1.6mA
3V < VO < VRT (off), IR = 8mA
0.40
0.40
V
V
Power On-Off Reset out Peak
Voltage
0.65
20
1.0
V
1KΩ Reset Pull-up to VO
Reset Output Leakage Current
(high level)
Vo in Regul.
VR = 5V
50
µ
A
tD
Reset Pulse Delay Time
Power OFF Vo Threshold
CD = 100nF
ms
VRthOFF
Vo @ Reset out H to L
4.75 Vo –0.15
4.7
V
V
Transition; T = 25 C
– 40°C ≤ TJ ≤ + 125°C
°
J
IC6
VRthON
V6
Delay Capacitor Charging
Current (current generator)
V6 = 3V
20
µA
Power ON Vo Threshold
Vo @ Reset out L to H
Transition
VrthOFF
+ 0.03V 0.04V
Vo –
V
Delay Comparator Threshold
Reset out = ”1” H to L Transition
Reset out = ”0” L to H Transition
3.2
3.7
3.8
V
V
4
4.4
0.5
V6H
VInhL
VInhH
IInhL
Delay Comparator Hysteresis
Low Inhibit Voltage
500
mV
V
High Inhibit Voltage
2.0
V
Low Level Inhibit Current
VInh L = 0.4V
– 40
– 10
µ
A
(*) Note 1 : The device is not operating within the range : 26 V < Vi < 37 V.
EXTERNALCOMPENSATION
Where the output transistor is a lateral PNP type
there is a pole in the regulation loop at a frequency
too low to be compensatedby a capacitorwich can
be integrated. An external compensation is there-
fore necessary so a very high value capacitor must
be connectedfrom the outputto ground.
Theparassiticequivalentseriesresistanceoftheca-
pacitorusedaddsa zerotothe regulationloop.This
zero may compromise the stability of the system
since its effect tendsto cancel the effectof the pole
added.InregulatorsthisESR mustbe less than3Ω
and the minimumcapacitorvalue is 47µF.
Sincethepurposeofa voltageregulatoris tosupply
a fixed output voltage in spite of supply and load
variations,the openloop gain of theregulatormust
be very high atlow frequencies.This maycause in-
stability as a result of the various poles present in
the loop. To avoid this instability dominant pole
compensationisused toreducephaseshiftsdueto
other poles at the unity gain frequency. The lower
thefrequencyoftheseotherpoles,thegreatermust
be the capacitor used to create the dominant pole
for the same DC gain.
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