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产品型号L4923的Datasheet PDF文件预览

L4923  
5V–1A VERY LOW DROP REGULATOR  
WITH RESET AND INHIBIT  
.
VERY LOW DROP (max. 0.9V at 1A) OVER  
FULL OPERATING TEMPERATURE RANGE  
(– 40 / +125 °C)  
LOW QUIESCENT CURRENT (max 70 mA at  
1 A) OVER FULL T RANGE  
PRECISEOUTPUTVOLTAGE(5V± 4%)OVER  
FULL T RANGE  
POWER ON-OFF INFORMATION WITH SET-  
TABLEDELAY  
INHIBIT FOR REMOTE ON-OFF COMMAND  
(active high)  
LOAD STANDBY CURRENT  
LOAD DUMP AND REVERSE BATTERY PRO-  
TECTION  
.
.
.
.
Heptawatt  
ORDERING NUMBER : L4923  
The device is internally protected against load  
dumps transient of + 60 V, input overvoltage, re-  
verse polarity, overheatingand outputshortcircuit :  
thankstothesefeaturesthe L4923is very suitedfor  
the automotiveand industrial applications.  
.
.
.
.
SHORT CIRCUIT PROTECTION  
THERMAL SHUTDOWN  
The reset function is very useful for power off and  
power on information when supplying a microproc-  
essor.  
DESCRIPTION  
TheL4923is a highcurrentmonolithicvoltageregu-  
lator with very low voltagedrop (0.70 V max at 1 A,  
TJ = 25 °C).  
The inhibit function reduces drastically the con-  
sumptionwhenno loadcurrentis required: typically  
the standby currentvalue is 300 µA.  
BLOCK DIAGRAM  
June 2000  
1/6  
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.  
L4923  
ABSOLUTE MAXIMUM RATINGS  
Symbol  
Parameter  
Value  
35  
Unit  
V
Vi  
Vr  
DC Input Voltage  
DC Reverse Voltage  
– 18  
V
VD  
TJ  
Positive Load Dump Protection (t = 300ms)  
Junction Temperature range  
60  
V
– 40 to 150  
– 40 to 125  
– 55 to 150  
°C  
°C  
°C  
Top  
Tstg  
Operating Temperature Range  
Storage Temperature Range  
Note: The circuit is ESD protected according to MIL-STD-883C  
THERMAL DATA  
Symbol  
Parameter  
Thermal Resistance Junction Case  
Value  
Unit  
Rth j-case  
4
C/W  
°
PIN CONNECTION  
Figure 1 : ApplicationCircuit.  
(*) RECOMMENDED VALUE : C = 47 F, ESR < 10 , (Iout > 10 mA) OVER FULL Trange  
.
µ
0
2/6  
L4923  
ELECTRICAL CHARACTERISTICS (V = 14. 4V, – 40°C TJ + 125°C unless otherwise specified)  
i
Symbol  
Parameter  
Operating Input Voltage  
Output Voltage  
Test Conditions  
(*) Note 1  
Io = 0mA to 1A  
Min.  
Typ.  
Max.  
Unit  
Vi  
6
26  
V
Vo  
4.8  
4.9  
5.2  
5.1  
V
V
T = 25 C  
°
J
Line Regulation  
Vi = 6 to 26V; IO = 10mA  
5
25  
mV  
dB  
V
Line  
SVR  
Supply Voltage Rejection  
Io = 700mA  
55  
f = 120Hz; Co = 47µF  
Vi = 12Vdc + 5Vpp  
Load Regulation  
Dropout Voltage  
Io = 10mA to 1A  
15  
50  
mV  
V
V
LOAD  
Vi – Vo  
0.45  
0.70  
0.90  
T = 25 C, I = 1A  
°
J
O
Over Full T, Io = 1A  
V
Iq  
Quiescent Current  
Io = 10mA  
Io = 1A  
Active High Inhibit  
7
25  
0.30  
12  
70  
0.65  
mA  
mA  
mA  
ISC  
Short Circuit Current  
Supply Volt. Rej.  
1.8  
60  
A
SVR  
Io = 350mA ; f = 120Hz  
50  
dB  
C = 100 F ; V = 12V 5V  
µ
±
o
i
pp  
VR  
VRT peak  
IR  
Rset Output Saturation Voltage 1.5V < VO < VRT (off), IR = 1.6mA  
3V < VO < VRT (off), IR = 8mA  
0.40  
0.40  
V
V
Power On-Off Reset out Peak  
Voltage  
0.65  
20  
1.0  
V
1KReset Pull-up to VO  
Reset Output Leakage Current  
(high level)  
Vo in Regul.  
VR = 5V  
50  
µ
A
tD  
Reset Pulse Delay Time  
Power OFF Vo Threshold  
CD = 100nF  
ms  
VRthOFF  
Vo @ Reset out H to L  
4.75 Vo 0.15  
4.7  
V
V
Transition; T = 25 C  
– 40°C TJ + 125°C  
°
J
IC6  
VRthON  
V6  
Delay Capacitor Charging  
Current (current generator)  
V6 = 3V  
20  
µA  
Power ON Vo Threshold  
Vo @ Reset out L to H  
Transition  
VrthOFF  
+ 0.03V 0.04V  
Vo –  
V
Delay Comparator Threshold  
Reset out = ”1” H to L Transition  
Reset out = ”0” L to H Transition  
3.2  
3.7  
3.8  
V
V
4
4.4  
0.5  
V6H  
VInhL  
VInhH  
IInhL  
Delay Comparator Hysteresis  
Low Inhibit Voltage  
500  
mV  
V
High Inhibit Voltage  
2.0  
V
Low Level Inhibit Current  
VInh L = 0.4V  
– 40  
– 10  
µ
A
(*) Note 1 : The device is not operating within the range : 26 V < Vi < 37 V.  
EXTERNALCOMPENSATION  
Where the output transistor is a lateral PNP type  
there is a pole in the regulation loop at a frequency  
too low to be compensatedby a capacitorwich can  
be integrated. An external compensation is there-  
fore necessary so a very high value capacitor must  
be connectedfrom the outputto ground.  
Theparassiticequivalentseriesresistanceoftheca-  
pacitorusedaddsa zerotothe regulationloop.This  
zero may compromise the stability of the system  
since its effect tendsto cancel the effectof the pole  
added.InregulatorsthisESR mustbe less than3Ω  
and the minimumcapacitorvalue is 47µF.  
Sincethepurposeofa voltageregulatoris tosupply  
a fixed output voltage in spite of supply and load  
variations,the openloop gain of theregulatormust  
be very high atlow frequencies.This maycause in-  
stability as a result of the various poles present in  
the loop. To avoid this instability dominant pole  
compensationisused toreducephaseshiftsdueto  
other poles at the unity gain frequency. The lower  
thefrequencyoftheseotherpoles,thegreatermust  
be the capacitor used to create the dominant pole  
for the same DC gain.  
3/6  
L4923  
FUNCTIONAL DESCRIPTION  
The operating principle of the voltage regulator is  
basedonthereference,theerroramplifier,thedriver  
and the power PNP. This stage uses an Isolated  
CollectorVerticalPNPtransistorwhich allowsto ob-  
tain very low dropoutvoltage(typ.450 mV)and low  
quiescentcurrent (IQ = 20mA typically at IO = 1 A).  
The reset function is LOW active when the output  
voltage level is lower than the reset threshold volt-  
ageVRth (typ.value: VO -150mV).Whentheoutput  
voltageis higherthanVRth theresetbecomesHIGH  
afteradelaytimesettablewiththeexternalcapacitor  
Cd. Typically td = 20 ms, Cd = 0.1 µF. The reset  
threshold hysteresis improves the noise immunity  
allowing to avoid false switchings. The typical reset  
outputwaveformis shownin fig.2.  
Thanks to these features the device is particularly  
suited when the power dissipation must be limited  
as, for example, in automotiveor industrial applica-  
tions supplied by battery.  
TheinhibitcircuitacceptsstandardTTLinputlevels:  
thisblockswitchesoffthevoltageregulatorwhenthe  
input signalis HIGH and switches on it when the in-  
putsignalisLOW.Thankstoinhibitfunctionthecon-  
sumptionis drastically reduced(650 µA max)when  
no load current is required.  
The three gain stages (operational amplifier, driver  
and power PNP) require the external capacitor  
(COmin = 22 µF) to guarantee the global stability of  
the system.  
Theantisaturationcircuitallowstoreducedrastically  
the current peak which takes place during the start  
up.  
Figure 2 : Typical Reset OutputWaveform.  
4/6  
L4923  
mm  
inch  
DIM.  
MIN. TYP. MAX. MIN. TYP. MAX.  
OUTLINE AND  
A
C
D
D1  
E
E1  
F
4.8  
1.37  
2.8  
1.35 0.047  
0.55 0.014  
0.97 0.028  
0.189  
0.054  
0.110  
0.053  
0.022  
0.038  
0.031  
0.035  
MECHANICAL DATA  
2.4  
1.2  
0.35  
0.7  
0.094  
0.6  
0.8  
0.9  
0.024  
F1  
G
2.34  
4.88  
7.42  
2.54  
5.08  
7.62  
2.74 0.095 0.100 0.105  
5.28 0.193 0.200 0.205  
7.82 0.295 0.300 0.307  
10.4  
10.4 0.396  
G1  
G2  
H2  
H3  
L
L1  
L2  
L3  
L4  
L5  
L6  
L7  
L9  
M
0.409  
0.409  
10.05  
16.7  
16.9  
14.92  
17.1 0.657 0.668 0.673  
0.587  
21.24 21.54 21.84 0.386 0.848 0.860  
22.27 22.52 22.77 0.877 0.891 0.896  
1.29  
3
0.051  
0.102 0.110 0.118  
2.6  
15.1  
6
2.8  
15.5  
6.35  
0.2  
2.8  
5.08  
15.8 0.594 0.610 0.622  
6.6  
0.236 0.250 0.260  
0.008  
2.55  
4.83  
3.05 0.100 0.110 0.120  
5.33 0.190 0.200 0.210  
40° (typ.)  
M1  
V4  
Dia  
Heptawatt V  
3.65  
3.85 0.144  
0.152  
V
V
L
E
L1  
M1  
A
M
D
C
D1  
H2  
L2  
L3  
F
L5  
E1  
E
V4  
L9  
H3  
H1  
G
G1 G2  
Dia.  
F
L7  
L4  
H2  
F1  
L6  
HEPTAMEC  
5/6  
L4923  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the conse-  
quences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No  
license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this  
publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMi-  
croelectronics products are not authorized for use as critical components in life support devices or systems without express written  
approval of STMicroelectronics.  
The ST logo is a registered trademark of STMicroelectronics  
2000 STMicroelectronics – Printed in Italy – All Rights Reserved  
STMicroelectronics GROUP OF COMPANIES  
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -  
Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.  
http://www.st.com  
6/6  
配单直通车
L4923产品参数
型号:L4923
是否Rohs认证: 不符合
生命周期:Obsolete
IHS 制造商:STMICROELECTRONICS
零件包装代码:ZFM
包装说明:HEPTAWATT-7
针数:7
Reach Compliance Code:not_compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
风险等级:5.88
Is Samacsys:N
可调性:FIXED
最大回动电压 1:0.9 V
标称回动电压 1:0.9 V
最大绝对输入电压:35 V
最大输入电压:26 V
最小输入电压:6 V
JESD-30 代码:R-PZFM-T7
JESD-609代码:e0
最大电网调整率:0.025%
最大负载调整率:0.05%
功能数量:1
输出次数:1
端子数量:7
工作温度TJ-Max:125 °C
工作温度TJ-Min:-40 °C
最高工作温度:125 °C
最低工作温度:-40 °C
最大输出电流 1:1 A
最大输出电压 1:5.2 V
最小输出电压 1:4.8 V
标称输出电压 1:5 V
封装主体材料:PLASTIC/EPOXY
封装代码:ZIP
封装等效代码:ZIP7,.15,.2TB
封装形状:RECTANGULAR
封装形式:FLANGE MOUNT
峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified
调节器类型:FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR
子类别:Other Regulators
表面贴装:NO
技术:BIPOLAR
端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE
端子节距:1.27 mm
端子位置:ZIG-ZAG
处于峰值回流温度下的最长时间:NOT SPECIFIED
最大电压容差:4%
Base Number Matches:1
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