L6599D芯片引脚定义引脚图及功能IC贸易商引脚图技术参数-中国IC网-芯三七

L6599

High-voltage resonant controller

Features

■ 50% duty cycle, variable frequency control of

resonant half-bridge

■ High-accuracy oscillator

■ Up to 500kHz operating frequency

DIP-16

SO-16N

■ Two-level OCP: frequency-shift and latched

shutdown

Order code

■ Interface with PFC controller

■ Latched disable input

Part number

Package

Packaging

■ Burst-mode operation at light load

L6599D

L6599TR

L6599N

SO-16N

DIP-16

Tube

Tape and reel

Tube

■ Input for power-ON/OFF sequencing or

brownout protection

■ Non-linear soft-start for monotonic output

voltage rise

Applications

■ 600V-rail compatible high-side gate driver with

integrated bootstrap diode and high dV/dt

immunity

■ LCD & PDP TV

■ Desktop PC, entry-level server

■ Telecom SMPS

■ -300/800mA high-side and low-side gate

drivers with UVLO pull-down

■ AC-DC adapter, open frame SMPS

■ DIP-16, SO-16N packages

Block diagram

Vcc

H.V.

12

16 V_BOOT

DISABLE

DIS

8

+

-

DIS

15 HVG

14

S

R

Q

UV

DETECTION

HVG

DRIVER

1.85V

5

C_BOOT

17V

SYNCHRONOUS

BOOTSTRAP DIODE

UVLO

STBY

UVLO

OUT

-

LC TANK

CIRCUIT

STANDBY

LEVEL

SHIFTER

+

1.25V

Vs

DRIVING

LOGIC

Ifmin

11 LVG

DEAD

TIME

LVG DRIVER

+

-

2V

10

RFmin

Css

4

1

+

ISEN_DIS

GND

Q

S

-

1.5V

R

UVLO

6

ISEN

+

-

0.8V

CONTROL

LOGIC

9

PFC_STOP

-

LINE_OK

1.25V

6.3V

+

ISEN_DIS

DIS

STANDBY

CF

3

15

µA

VCO

2

7

DELAY

LINE

May 2006

Rev 1

1/36

www.st.com

36

Contents

L6599

Contents

1

2

Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1

2.2

Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3

4

Typical system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.1

4.2

Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5

6

7

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Operation at no load or very light load . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Current sense, OCP and OLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Latched shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Line sensing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Bootstrap section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8

9

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2/36

L6599

Device description

1

Device description

The L6599 is a double-ended controller specific for the resonant half-bridge topology. It

provides 50% complementary duty cycle: the high-side switch and the low-side switch are

driven ON 180° out-of-phase for exactly the same time.

Output voltage regulation is obtained by modulating the operating frequency. A fixed dead-

time inserted between the turn-OFF of one switch and the turn-ON of the other one

guarantees soft-switching and enables high-frequency operation.

To drive the high-side switch with the bootstrap approach, the IC incorporates a high-voltage

floating structure able to withstand more than 600V with a synchronous-driven high-voltage

DMOS that replaces the external fast-recovery bootstrap diode.

The IC enables the designer to set the operating frequency range of the converter by means

of an externally programmable oscillator.

At start-up, to prevent uncontrolled inrush current, the switching frequency starts from a

programmable maximum value and progressively decays until it reaches the steady-state

value determined by the control loop. This frequency shift is non linear to minimize output

voltage overshoots; its duration is programmable as well.

The IC can be forced to enter a controlled burst-mode operation at light load, so as to keep

converter's input consumption to a minimum.

IC's functions include a not-latched active-low disable input with current hysteresis useful for

power sequencing or for brownout protection, a current sense input for OCP with frequency

shift and delayed shutdown with automatic restart.

A higher level OCP latches off the IC if the first-level protection is not sufficient to control the

primary current. Their combination offers complete protection against overload and short

circuits. An additional latched disable input (DIS) allows easy implementation of OTP and/or

OVP.

An interface with the PFC controller is provided that enables to switch off the pre-regulator

during fault conditions, such as OCP shutdown and DIS high, or during burst-mode

operation.

3/36

Pin Settings

L6599

2

Pin Settings

2.1

Connection

Figure 1. Pin Connection (Top view)

VBOOT

HVG

Css

DELAY

CF

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

OUT

RFmin

STBY

ISEN

LINE

N.C.

Vcc

LVG

GND

DIS

PFC_STOP

2.2

Functions

Table 1.

N.

Pin functions

Name

Function

Soft start. This pin connects an external capacitor to GND and a resistor to RFmin (pin 4)

that set both the maximum oscillator frequency and the time constant for the frequency shift

that occurs as the chip starts up (soft-start). An internal switch discharges this capacitor

every time the chip turns OFF (V_CC< UVLO, LINE < 1.25V or > 6V, DIS > 1.85V, ISEN >

1.5V, DELAY > 3.5V) to make sure it will be soft-started next, and when the voltage on the

current sense pin (ISEN) exceeds 0.8V, as long as it stays above 0.75V.

1

C_SS

Delayed shutdown upon overcurrent. A capacitor and a resistor are connected from this pin

to GND to set both the maximum duration of an overcurrent condition before the IC stops

switching and the delay after which the IC restarts switching. Every time the voltage on the

ISEN pin exceeds 0.8V the capacitor is charged by an internal 150µA current generator and

is slowly discharged by the external resistor. If the voltage on the pin reaches 2V, the soft

start capacitor is completely discharged so that the switching frequency is pushed to its

maximum value and the 150µA is kept always on. As the voltage on the pin exceeds 3.5V

the IC stops switching and the internal generator is turned OFF, so that the voltage on the

pin will decay because of the external resistor. The IC will be soft-restarted as the voltage

drops below 0.3V. In this way, under short circuit conditions, the converter will work

intermittently with very low input average power.

2

DELAY

Timing capacitor. A capacitor connected from this pin to GND is charged and discharged by

internal current generators programmed by the external network connected to pin 4 (RFmin)

and determines the switching frequency of the converter.

3

CF

4/36

L6599

Pin Settings

Table 1.

Pin functions

Minimum oscillator frequency setting. This pin provides a precise 2V reference and a resistor

connected from this pin to GND defines a current that is used to set the minimum oscillator

frequency. To close the feedback loop that regulates the converter output voltage by

modulating the oscillator frequency, the phototransistor of an optocoupler will be connected

to this pin through a resistor. The value of this resistor will set the maximum operating

frequency. An R-C series connected from this pin to GND sets frequency shift at start-up to

prevent excessive energy inrush (soft-start).

4

5

RFmin

Burst-mode operation threshold. The pin senses some voltage related to the feedback

control, which is compared to an internal reference (1.25V). If the voltage on the pin is lower

than the reference, the IC enters an idle state and its quiescent current is reduced. The chip

restarts switching as the voltage exceeds the reference by 50mV. Soft-start is not invoked.

This function realizes burst-mode operation when the load falls below a level that can be

programmed by properly choosing the resistor connecting the optocoupler to pin RFmin (see

block diagram). Tie the pin to RFmin if burst-mode is not used.

STBY

Current sense input. The pin senses the primary current though a sense resistor or a

capacitive divider for lossless sensing. This input is not intended for a cycle-by-cycle control;

hence the voltage signal must be filtered to get average current information. As the voltage

exceeds a 0.8V threshold (with 50mV hysteresis), the soft-start capacitor connected to pin 1

is internally discharged: the frequency increases hence limiting the power throughput. Under

output short circuit, this normally results in a nearly constant peak primary current. This

condition is allowed for a maximum time set at pin 2. If the current keeps on building up

despite this frequency increase, a second comparator referenced at 1.5V latches the device

off and brings its consumption almost to a “before start-up” level. The information is latched

and it is necessary to recycle the supply voltage of the IC to enable it to restart: the latch is

removed as the voltage on the Vcc pin goes below the UVLO threshold. Tie the pin to GND if

the function is not used.

6

ISEN

Line sensing input. The pin is to be connected to the high-voltage input bus with a resistor

divider to perform either AC or DC (in systems with PFC) brownout protection. A voltage

below 1.25V shuts down (not latched) the IC, lowers its consumption and discharges the

soft-start capacitor. IC’s operation is re-enabled (soft-started) as the voltage exceeds 1.25V.

The comparator is provided with current hysteresis: an internal 15µA current generator is ON

as long as the voltage applied at the pin is below 1.25V and is OFF if this value is exceeded.

Bypass the pin with a capacitor to GND to reduce noise pick-up. The voltage on the pin is

top-limited by an internal zener. Activating the zener causes the IC to shut down (not

latched). Bias the pin between 1.25 and 6V if the function is not used.

7

8

LINE

Latched device shutdown. Internally the pin connects a comparator that, when the voltage

on the pin exceeds 1.85V, shuts the IC down and brings its consumption almost to a “before

start-up” level. The information is latched and it is necessary to recycle the supply voltage of

the IC to enable it to restart: the latch is removed as the voltage on the V_CCpin goes below

the UVLO threshold. Tie the pin to GND if the function is not used.

DIS

Open-drain ON/OFF control of PFC controller. This pin, normally open, is intended for

stopping the PFC controller, for protection purpose or during burst-mode operation. It goes

low when the IC is shut down by DIS > 1.85V, ISEN > 1.5V, LINE > 6V and STBY < 1.25V.

The pin is pulled low also when the voltage on pin DELAY exceeds 2V and goes back open

as the voltage falls below 0.3V. During UVLO, it is open. Leave the pin unconnected if not

used.

9

PFC_STOP

GND

Chip ground. Current return for both the low-side gate-drive current and the bias current of

the IC. All of the ground connections of the bias components should be tied to a track going

to this pin and kept separate from any pulsed current return.

10

5/36

Typical system block diagram

L6599

Table 1.

Pin functions

Low-side gate-drive output. The driver is capable of 0.3A min. source and 0.8A min. sink

peak current to drive the lower MOSFET of the half-bridge leg. The pin is actively pulled to

11

LVG

GND during UVLO.

Supply Voltage of both the signal part of the IC and the low-side gate driver. Sometimes a

small bypass capacitor (0.1µF typ.) to GND might be useful to get a clean bias voltage for

the signal part of the IC.

12

V_CC

High-voltage spacer. The pin is not internally connected to isolate the high-voltage pin and

ease compliance with safety regulations (creepage distance) on the PCB.

13

14

N.C.

OUT

High-side gate-drive floating ground. Current return for the high-side gate-drive current.

Layout carefully the connection of this pin to avoid too large spikes below ground.

High-side floating gate-drive output. The driver is capable of 0.3A min. source and 0.8A min.

sink peak current to drive the upper MOSFET of the half-bridge leg. A resistor internally

connected to pin 14 (OUT) ensures that the pin is not floating during UVLO.

15

16

HVG

High-side gate-drive floating supply Voltage. The bootstrap capacitor connected between

this pin and pin 14 (OUT) is fed by an internal synchronous bootstrap diode driven in-phase

with the low-side gate-drive. This patented structure replaces the normally used external

diode.

VBOOT

3

Typical system block diagram

Figure 2. Typical system block diagram

6/36

L6599

Electrical data

4

Electrical data

4.1

Maximum ratings

Table 2.

Symbol

Absolute maximum ratings

16

14

12

9

Parameter

Floating supply voltage

Value

Unit

V_BOOT

V_OUT

-1 to 618

V

-3 to V_BOOT-18

Floating ground voltage

Floating ground max. slew rate

IC Supply voltage (I_CC≤25 mA)

Maximum voltage (pin open)

Maximum sink current (pin low)

Maximum pin voltage (Ipin ≤1mA)

Maximum source current

50

V/ns

dV_OUT/dt

V_CC

Self-limited

-0.3 to V_CC

V

V_{PFC_STOP}

I_{PFC_STOP}

V_LINEmax

I_RFmin

9

Self-limited

2

A

7

V

4

mA

V

1 to 6, 8 Analog inputs & outputs

-0.3 to 5

Note:

ESD immunity for pins 14, 15 and 16 is guaranteed up to 900V

4.2

Thermal data

Table 3.

Symbol

Thermal data

Description

Value

Unit

Max. thermal resistance junction to ambient (DIP16)

Max. thermal resistance junction to ambient (SO16)

Storage temperature range

80

120

R_thJA

°C/W

T_STG

T_J

-55 to 150

°C

Junction operating temperature range

-40 to 150

Recommended max. power dissipation @T_A= 70°C (DIP16)

Recommended max. power dissipation @T_A= 50°C (SO16)

1

P_TOT

W

0.83

7/36

Electrical characteristics

L6599

5

Electrical characteristics

T = 0 to 105°C, V = 15V, V

= 15V, C

= C

= 1nF; C = 470pF;

LVG F

J

CC

BOOT

HVG

R

= 12kΩ; unless otherwise specified.

RFmin

Table 4.

Symbol

Electrical characteristics

Parameter

Test condition

Min

Typ

Max

Unit

IC supply voltage

V_CC

Operating range

After device turn-on

Voltage rising

8.85

10

16

V

V_CC(ON)

V_CC(OFF)

Turn-ON threshold

10.7

8.15

2.55

17

11.4

8.85

Turn-OFF threshold

Hysteresis

Voltage falling

7.45

Hys

V_Z

V_CCclamp voltage

Iclamp = 10mA

16

17.9

Supply current

I_start-up

I_q

Before device turn-ON

V_CC= V_CC(ON)- 0.2V

Start-up current

Quiescent current

Operating current

200

1.5

3.5

250

2

µA

mA

Device ON, V_STBY= 1V

Device ON,

V_STBY= V_RFmin

I_op

5

V_DIS> 1.85V or V_DELAY

I_q

Residual consumption

300

400

µA

> 3.5V or V_LINE< 1.25 V

or V_LINE= V_clamp

High-side floating gate-drive supply

V_BOOTpin leakage

I_LKBOOT

5

µA

Ω

V_BOOT= 580V

V_OUT= 562V

current

I_LKOUT

r_DS(on)

OUT pin leakage current

Synchronous bootstrap

diode ON-resistance

150

V_LVG= High

Overcurrent comparator

I_ISEN

t_LEB

V_ISEN= 0 to V_ISENdis

Input bias current

-1

µA

ns

After V_HVGand V_LVG

low-to-high transition

Leading edge blanking

250

0.8

Frequency shift

threshold

Voltage rising ⁽¹⁾

V_ISENx

0.76

1.44

0.84

V

Hysteresis

Voltage falling

50

1.5

300

mV

V

Voltage rising ⁽¹⁾

V_ISENdis

td_(H-L)

Latch OFF threshold

Delay to output

1.56

400

ns

8/36

L6599

Electrical characteristics

Table 4.

Symbol

Electrical characteristics

Parameter

Test condition

Min

Typ

Max

Unit

Line sensing

Voltage rising or falling

V_th

Threshold voltage

1.2

1.25

15

1.3

V

(1)

I_Hyst

Current hysteresis

Clamp level

12

6

18

8

µA

V

V_CC> 5V, V_LINE= 0.3V

I_LINE= 1mA

V_clamp

DIS function

I_DIS

V_th

V_DIS= 0 to V_th

Input bias current

Disable threshold

-1

µA

V

Voltage rising ⁽¹⁾

1.77

1.85

1.93

Oscillator

D

Output duty cycle

Both HVG and LVG

48

50

60

52

%

58.2

240

61.8

260

kHz

R_RFmin= 2.7 kΩ

250

f_osc

Oscillation frequency

Maximum

recommended

500

0.4

kHz

T_D

Dead-time

Peak value

Valley value

Between HVG and LVG

0.2

0.3

3.9

0.9

µs

V

V_CFp

V_CFv

V

Voltage reference at

pin 4

V_REF

(1)

1.92

1

2

1

2.08

100

V

K_M

Current mirroring ratio

Timing resistor range

A/A

RF_MIN

kΩ

PFC_STOP function

V_{PFC_STOP}= V_CC

V_DIS= 0V

,

High level leakage

current

I_leak

1

µA

V

I_{PFC_STOP}=1mA,

V_DIS= 2V

V_L

Low saturation level

0.2

Soft-start function

I_leak

R

Open-state current

V(Css) = 2V

0.5

µA

V_ISEN> V_ISENx

Discharge resistance

120

Ω

Standby function

I_DIS

V_th

V_DIS= 0 to V_th

Input Bias Current

Disable threshold

Hysteresis

-1

µA

V

Voltage falling ⁽¹⁾

Voltage rising

1.2

1.25

50

1.3

Hys

mV

9/36

Electrical characteristics

L6599

Unit

Table 4.

Symbol

Electrical characteristics

Parameter

Test condition

Min

Typ

Max

Delayed shutdown function

I_leak

I_CHARGE

Vth₁

Open-state current

Charge current

V(DELAY) = 0

0.5

200

2.08

µA

V

V_DELAY= 1V,

V_ISEN= 0.85V

100

150

2

Voltage rising ⁽¹⁾

Threshold for forced

operation at max.

frequency

1.92

Voltage rising ⁽¹⁾

Voltage falling ⁽¹⁾

Vth₂

Vth₃

Shutdown threshold

Restart threshold

3.3

3.5

0.3

3.7

V

0.25

0.35

Low - side gate driver (voltages referred to GND)

V_LVGL

V_LVGH

I_sourcepk

I_sinkpk

t_f

I_sink= 200mA

_source= 5mA

Output low voltage

Output high voltage

Peak source current

Peak sink current

Fall time

1.5

V

12.8

-0.3

0.8

13.3

I

A

30

60

ns

t_r

Rise time

V

_CC= 0 to V_CC(ON)

,

UVLO saturation

1.1

1.5

V

I_sink= 2mA

High-side gate driver (voltages referred to OUT)

V_HVGL

V_HVGH

I_sourcepk

I_sinkpk

t_f

I_sink= 200 mA

I_source= 5 mA

Output low voltage

Output high voltage

V

12.8

-0.3

0.8

13.3

Peak source current

Peak sink current

Fall time

A

30

60

25

ns

kΩ

t_r

Rise time

HVG-OUT pull-down

1. Values traking each other

10/36

L6599

Typical electrical performance

6

Typical electrical performance

Figure 3. Device consumption vs

supply voltage

Figure 4. IC consumption vs

junction temperature

Figure 5.

V

clamp voltage vs

Figure 6. UVLO thresholds vs

junction temperature

CC

junction temperature

11/36

Typical electrical performance

L6599

Figure 7. Oscillator frequency vs

Figure 8. Dead-time vs

junction temperature

Figure 9. Oscillator frequency vs

timing components

Figure 10. Oscillator ramp vs

junction temperature

12/36

L6599

Typical electrical performance

Figure 11. Reference voltage vs

junction temperature

Figure 12. Current mirroring ratio vs

junction temperature

Figure 13. OCP delay source current vs Figure 14. OCP delay thresholds vs

junction temperature junction temperature

13/36

Typical electrical performance

L6599

Figure 15. Standby thresholds vs

Figure 16. Current sense thresholds vs

junction temperature

Figure 17. Line thresholds vs

junction temperature

Figure 18. Line source current vs

junction temperature

Figure 19. Latched disable threshold vs

junction temperature

14/36

L6599

Application information

7

Application information

The L6599 is an advanced double-ended controller specific for resonant half-bridge

topology. In these converters the switches (MOSFETs) of the half-bridge leg are alternately

switched on and OFF (180° out-of-phase) for exactly the same time. This is commonly

referred to as operation at "50% duty cycle", although the real duty cycle, that is the ratio of

the ON-time of either switch to the switching period, is actually less than 50%. The reason is

that there is an internally fixed dead-time T , inserted between the turn-OFF of either

D

MOSFET and the turn-ON of the other one, where both MOSFETs are OFF. This dead- time

is essential in order for the converter to work correctly: it will ensure soft-switching and

enable high-frequency operation with high efficiency and low EMI emissions.

To perform converter's output voltage regulation the device is able to operate in different

modes (Figure 20), depending on the load conditions:

1. Variable frequency at heavy and medium/light load. A relaxation oscillator (see

"Oscillator" section for more details) generates a symmetrical triangular waveform,

which MOSFETs' switching is locked to. The frequency of this waveform is related to a

current that will be modulated by the feedback circuitry. As a result, the tank circuit

driven by the half-bridge will be stimulated at a frequency dictated by the feedback loop

to keep the output voltage regulated, thus exploiting its frequency-dependent transfer

characteristics.

2. Burst-mode control with no or very light load. When the load falls below a value, the

converter will enter a controlled intermittent operation, where a series of a few

switching cycles at a nearly fixed frequency are spaced out by long idle periods where

both MOSFETs are in OFF-state. A further load decrease will be translated into longer

idle periods and then in a reduction of the average switching frequency. When the

converter is completely unloaded, the average switching frequency can go down even

to few hundred Hz, thus minimizing magnetizing current losses as well as all frequency-

related losses and making it easier to comply with energy saving recommendations.

Figure 20. Multi-mode operation

15/36

Application information

L6599

7.1

Oscillator

The oscillator is programmed externally by means of a capacitor (CF), connected from pin 3

(CF) to ground, that will be alternately charged and discharged by the current defined with

the network connected to pin 4 (RF ). The pin provides an accurate 2V reference with

min

about 2mA source capability and the higher the current sourced by the pin is, the higher the

oscillator frequency will be. The block diagram of Figure 21 shows a simplified internal

circuit that explains the operation.

The network that loads the RFmin pin generally comprises three branches:

1. A resistor RF

connected between the pin and ground that determines the minimum

min

operating frequency;

2. A resistor RF

connected between the pin and the collector of the (emitter-grounded)

max

phototransistor that transfers the feedback signal from the secondary side back to the

primary side; while in operation, the phototransistor will modulate the current through

this branch - hence modulating the oscillator frequency - to perform output voltage

regulation; the value of RF

determines the maximum frequency the half-bridge will

max

be operated at when the phototransistor is fully saturated;

3. An R-C series circuit (C + R ) connected between the pin and ground that enables

SS

to set up a frequency shift at start-up (see Chapter 7.3: Soft-start). Note that the

contribution of this branch is zero during steady-state operation.

Figure 21. Oscillator's internal block diagram.

L6599

2 V

K_M·I_R

+

-

3

CF

2·K_M·I_R

RFmin

4

I_R

CF

0.9V

1 V

+

-

S

R

R_Fmin

R_SS

R_Fmax

Q

+

-

C_SS

3.9V

4 V

The following approximate relationships hold for the minimum and the maximum oscillator

frequency respectively:

1

f

_min= ------------------------------------------

3 ⋅ CF ⋅ RF_min

1

f

_max= --------------------------------------------------------------------------

| |

3 ⋅ CF ⋅ (RF_minRF_max

)

16/36

L6599

Application information

After fixing CF in the hundred pF or in the nF (consistently with the maximum source

capability of the RF pin and trading this off against the total consumption of the device),

min

the value of RF

and RF

will be selected so that the oscillator frequency is able to

min

max

cover the entire range needed for regulation, from the minimum value f

(at minimum input

min

voltage and maximum load) to the maximum value f

minimum load):

(at maximum input voltage and

max

1

RF_min= -----------------------------------

3 ⋅ CF ⋅ f_min

RF_min

RF_max= --------------------

f

--^m-----^a--^x- – 1

f_min

A different selection criterion will be given for RF

in case burst-mode operation at no-load

max

will be used (see "Operation at no load or very light load" section).

Figure 22. Oscillator waveforms and their relationship with gate-driving signals

CF

T^D

t

HVG

LVG

HB

t

In Figure 22 the timing relationship between the oscillator waveform and the gate-drive

signals, as well as the swinging node of the half-bridge leg (HB) is shown. Note that the low-

side gate-drive is turned on while the oscillator's triangle is ramping up and the high-side

gate-drive is turned on while the triangle is ramping down. In this way, at start-up, or as the

IC resumes switching during burst-mode operation, the low-side MOSFET will be switched

on first to charge the bootstrap capacitor. As a result, the bootstrap capacitor will always be

charged and ready to supply the high-side floating driver.

17/36

Application information

L6599

7.2

Operation at no load or very light load

When the resonant half-bridge is lightly loaded or unloaded at all, its switching frequency will

be at its maximum value. To keep the output voltage under control in these conditions and to

avoid losing soft-switching, there must be some significant residual current flowing through

the transformer's magnetizing inductance. This current, however, produces some

associated losses that prevent converter's no-load consumption from achieving very low

values.

To overcome this issue, the L6599 enables the designer to make the converter operate

intermittently (burst-mode operation), with a series of a few switching cycles spaced out by

long idle periods where both MOSFETs are in OFF-state, so that the average switching

frequency can be substantially reduced. As a result, the average value of the residual

magnetizing current and the associated losses will be considerably cut down, thus

facilitating the converter to comply with energy saving recommendations.

The device can be operated in burst-mode by using pin 5 (STBY): if the voltage applied to

this pin falls below 1.25V the IC will enter an idle state where both gate-drive outputs are

low, the oscillator is stopped, the soft-start capacitor C keeps its charge and only the 2V

SS

reference at RF

pin stays alive to minimize IC's consumption and V capacitor's

min

CC

discharge. The IC will resume normal operation as the voltage on the pin exceeds 1.25V by

50mV.

To implement burst-mode operation the voltage applied to the STBY pin needs to be related

to the feedback loop. Figure 23 shows the simplest implementation, suitable with a narrow

input voltage range (e.g. when there is a PFC front-end).

Figure 23. Burst-mode implementation: narrow input voltage range.

RFmin

4

Fmin

R

Fmax

R

Fmin

R

Fmax

R

L6599

STBY

5

Figure 24. Burst-mode implementation: wide input voltage range.

B+

RFmin

STBY

4

5

D

RRC

Fmin

R

Fmax

R

L6599

LINE

L6599

7

A

R

C

R

RD

B

R

A

R

B

C

+ R >> R

18/36

L6599

Application information

Essentially, RF

will define the switching frequency f

above which the L6599 will enter

max

burst-mode operation. Once fixed f

, RF

will be found from the relationship:

max

RF_min

3

8

-- --------------------

RF_max

=

⋅

f

--^m-----^a--^x- – 1

f_min

Note that, unlike the f

considered in the previous section ("Chapter 7.1: Oscillator"), here

max

f

is associated to some load Pout greater than the minimum one. Pout will be such that

max

B B

the transformer's peak currents are low enough not to cause audible noise.

Resonant converter's switching frequency, however, depends also on the input voltage;

hence, in case there is quite a large input voltage range with the circuit of Figure 23 the

value of Pout would change considerably. In this case it is recommended to use the

B

arrangement shown in Figure 24 where the information on the converter's input voltage is

added to the voltage applied to the STBY pin. Due to the strongly non-linear relationship

between switching frequency and input voltage, it is more practical to find empirically the

right amount of correction R / (R + R ) needed to minimize the change of Pout . Just be

A

B

careful in choosing the total value R + R much greater than R to minimize the effect on

A

B

C

the LINE pin voltage (see Chapter 7.6: Line sensing function).

Whichever circuit is in use, its operation can be described as follows. As the load falls below

the value Pout the frequency will try to exceed the maximum programmed value f and

B

max

the voltage on the STBY pin (V

) will go below 1.25V. The IC will then stop with both

STBY

gate-drive outputs low, so that both MOSFETs of the half-bridge leg are in OFF-state. The

voltage V will now increase as a result of the feedback reaction to the energy delivery

STBY

stop and, as it exceeds 1.3V, the IC will restart switching. After a while, V

will go down

STBY

again in response to the energy burst and stop the IC. In this way the converter will work in a

burst-mode fashion with a nearly constant switching frequency. A further load decrease will

then cause a frequency reduction, which can go down even to few hundred hertz. The timing

diagram of Figure 25 illustrates this kind of operation, showing the most significant signals.

A small capacitor (typically in the hundred pF) from the STBY pin to ground, placed as close

to the IC as possible to reduce switching noise pick-up, will help get clean operation.

To help the designer meet energy saving requirements even in power-factor-corrected

systems, where a PFC pre-regulator precedes the DC-DC converter, the device allows that

the PFC pre-regulator can be turned off during burst-mode operation, hence eliminating the

^{no-load consumption of this stage (0.5}÷ 1W). There is no compliance issue in that because

EMC regulations on low-frequency harmonic emissions refer to nominal load, no limit is

envisaged when the converter operates with light or no load.

To do so, the device provides pin 9 (PFC_STOP): it is an open collector output, normally

open, that is asserted low when the IC is idle during burst-mode operation. This signal will

be externally used for switching off the PFC controller and the pre-regulator as shown in

Figure 26 When the L6599 is in UVLO the pin is kept open, to let the PFC controller start

first.

19/36

Application information

Figure 25. Load-dependent operating modes: timing diagram

L6599

STBY

50 mV

hyster.

1.25V

t

osc

f

t

LVG

HVG

PFC_STOP

PFC

GATE-DRIVE

Resonant Mode

Burst-mode

Resonant Mode

Figure 26. How the L6599 can switch OFF a PFC controller at light load

ZCD

L6599

Vcc

9

PFC_STOP

22 k

Ω

L6561/2

12

100 k

Ω

BC547

L6599

BC547

PFC_OK

(AC_OK)

9

PFC_STOP

L6563

20/36

L6599

Application information

7.3

Soft-start

Generally speaking, purpose of soft-start is to progressively increase converter's power

capability when it is started up, so as to avoid excessive inrush current. In resonant

converters the deliverable power depends inversely on frequency, then soft- start is done by

sweeping the operating frequency from an initial high value until the control loop takes over.

With the L6599 converter's soft start-up is simply realized with the addition of an R-C series

circuit from pin 4 (RF ) to ground (see Figure 27).

min

Initially, the capacitor C is totally discharged, so that the series resistor R is effectively

SS

in parallel to RF

and the resulting initial frequency is determined by R and RF

only,

min

SS

min

since the optocoupler's phototransistor is cut off (as long as the output voltage is not too far

away from the regulated value):

1

f

_start= ------------------------------------------------------------------------

| |

3 ⋅ CF ⋅ (R(F_minR_SS))

The C capacitor is progressively charged until its voltage reaches the reference voltage

SS

(2V) and, consequently, the current through R goes to zero. This conventionally takes 5

SS

time constants R ·C but, before that time, the output voltage will have got close to the

SS SS

regulated value and the feedback loop taken over, so that it will be the optocoupler's

phototransistor to determine the operating frequency from that moment onwards.

During this frequency sweep phase the operating frequency will decay following the

exponential charge of C , that is, initially it will change relatively quickly but the rate of

SS

change will get slower and slower. This counteracts the non-linear frequency dependence

of the tank circuit that makes converter's power capability change little as frequency is away

from resonance and change very quickly as frequency approaches resonance frequency

(see Figure 28).

Figure 27. Soft-start circuit

RFmin

4

Fmin

R

SS

R

L6599

Css

1

C

21/36

Application information

Figure 28. Power vs frequency curve in an resonant half-bridge

L6599

RESONANCE

FREQUENCY

| Z ( f ) | ^{- 1}

f

Initial

frequency

Steady-state

frequency

As a result, the average input current will smoothly increase, without the peaking that occurs

with linear frequency sweep, and the output voltage will reach the regulated value with

almost no overshoot.

Typically, R and C will be selected based on the following relationships:

SS

RF_min

_SS= ---------------------

f_start

R

----------- – 1

f_min

3 ⋅ 10^–3

C_ss= ----------------------

R_SS

where f

is recommended to be at least 4 times f . The proposed criterion for C is

min SS

start

quite empirical and is a compromise between an effective soft-start action and an effective

OCP (see next section). Please refer to the timing diagram of Figure 31 to see some

significant signals during the soft-start phase.

22/36

L6599

Application information

7.4

Current sense, OCP and OLP

The resonant half-bridge is essentially voltage-mode controlled; hence a current sense input

will only serve as an overcurrent protection (OCP).

Unlike PWM-controlled converters, where energy flow is controlled by the duty cycle of the

primary switch (or switches), in a resonant half-bridge the duty cycle is fixed and energy flow

is controlled by its switching frequency. This impacts on the way current limitation can be

realized. While in PWM-controlled converters energy flow can be limited simply by

terminating switch conduction beforehand when the sensed current exceeds a preset

threshold (this is commonly now as cycle-by-cycle limitation), in a resonant half-bridge the

switching frequency, that is, its oscillator's frequency must be increased and this cannot be

done as quickly as turning off a switch: it takes at least the next oscillator cycle to see the

frequency change. This implies that to have an effective increase, able to change the energy

flow significantly, the rate of change of the frequency must be slower than the frequency

itself. This, in turn, implies that cycle-by-cycle limitation is not feasible and that, therefore,

the information on the primary current fed to the current sensing input must be somehow

averaged. Of course, the averaging time must not be too long to prevent the primary current

from reaching too high values.

In Figure 29 and Figure 30 a couple of current sensing methods are illustrated that will be

described in the following. The circuit of Figure 29 is simpler but the dissipation on the sense

resistor Rs might not be negligible, hurting efficiency; the circuit of Figure 30 is more

complex but virtually lossless and recommended when the efficiency target is very high.

Figure 29. Current sensing technique with sense resistor

Cr

6

ISEN

6

ICr

L6599

10

fmin

Vspk

0

Rs

τ ≈

23/36

Application information

Figure 30. Lossless current sensing technique, with capacitive shunt

L6599

10

fmin

V_Crpk

≈

τ

1N4148

C_AR_A

1N4148

6

ISEN

L6599

I^Cr

pk

Cr

RB

C_B

The device is equipped with a current sensing input (pin 6, ISEN) and a sophisticated

overcurrent management system. The ISEN pin is internally connected to the input of a first

comparator, referenced to 0.8V, and to that of a second comparator referenced to 1.5V. If the

voltage externally applied to the pin by either circuit in Figure 29 or Figure 30 exceeds 0.8V

the first comparator is tripped and this causes an internal switch to be turned on and

discharge the soft-start capacitor C (see Chapter 7.3: Soft-start). This will quickly

SS

increase the oscillator frequency and thereby limit energy transfer. The discharge will go on

until the voltage on the ISEN pin has dropped by 50mV; this, with an averaging time in the

range of 10/f , ensures an effective frequency rise. Under output short circuit, this

min

operation results in a nearly constant peak primary current.

It is normal that the voltage on the ISEN pin may overshoot above 0.8V; however, if the

voltage on the ISEN pin reaches 1.5V, the second comparator will be triggered, the L6599

will shutdown and latch off with both the gate-drive outputs and the PFC_STOP pin low,

hence turning off the entire unit. The supply voltage of the IC must be pulled below the

UVLO threshold and then again above the start-up level in order to restart. Such an event

may occur if the soft-start capacitor C is too large, so that its discharge is not fast enough

SS

or in case of transformer's magnetizing inductance saturation or a shorted secondary

rectifier.

In the circuit shown in Figure 29 where a sense resistor R in series to the source of the

S

low-side MOSFET is used, note the particular connection of the resonant capacitor. In this

way the voltage across R is related to the current flowing through the high-side MOSFET

S

and is positive most of the switching period, except for the time needed for the resonant

current to reverse after the low-side MOSFET has been switched OFF. Assuming that the

time constant of the RC filter is at least ten times the minimum switching frequency f , the

min

approximate value of R can be found using the empirical equation:

S

Vs_pkx

5 ⋅ 0.8

4

--------------

------------------

--------------

R_S

=

≈

I_Crpkx

where I

is the maximum desired peak current flowing through the resonant capacitor

Crpkx

and the primary winding of the transformer, which is related to the maximum load and the

minimum input voltage.

24/36

L6599

Application information

The circuit shown in Figure 30 can be operated in two different ways. If the resistor R in

A

series to C is small (not above some hundred Ω, just to limit current spiking) the circuit

A

operates like a capacitive current divider; C will be typically selected equal to C /100 or

A

R

less and will be a low-loss type, the sense resistor R will be selected as:

B

C_r

1 + -------

C_A

0.8π

⎛

⎝

⎞

⎠

--------------

=

R_B

I_Crpkx

and C will be such that R ·C is in the range of 10 /f

.

B

min

If the resistor R in series to C is not small (in this case it will be typically selected in the ten

A

kΩ), the circuit operates like a divider of the ripple voltage across the resonant capacitor Cr,

which, in turn, is related to its current through the reactance of Cr. Again, C will be typically

A

selected equal to C /100 or less, this time not necessarily a low-loss type, while R

R

B

(provided it is << R ) according to:

A

R_A²+ X_C²

0.8π

-------------- ---------------------------

A

R_B

=

⋅

I_Crpkx

X

C_r

where the reactance of C (X ) and C (X ) should be calculated at the frequency where

A

CA

R

Cr

I

= I

. Again, C will be such that R ·C is in the range of 10 /f

.

Crpk

Crpkx

B

min

Whichever circuit one is going to use, the calculated values of R or R should be

S

B

considered just a first cut value that needs to be adjusted after experimental verification.

OCP is effective in limiting primary-to-secondary energy flow in case of an overload or an

output short circuit, but the output current through the secondary winding and rectifiers

under these conditions might be so high to endanger converter's safety if continuously

flowing. To prevent any damage during these conditions it is customary to force converter's

intermittent operation, in order to bring the average output current to values such that the

thermal stress for the transformer and the rectifiers can be easily handled.

With the L6599 the designer can program externally the maximum time T that the

SH

converter is allowed to run overloaded or under short circuit conditions. Overloads or short

circuits lasting less than T will not cause any other action, hence providing the system

SH

with immunity to short duration phenomena. If, instead, T is exceeded an overload

SH

protection (OLP) procedure is activated that shuts down the device and, in case of

continuous overload/short circuit, results in continuous intermittent operation with a user-

defined duty cycle.

25/36

Application information

Figure 31. Soft-start and delayed shutdown upon overcurrent timing diagram

L6599

Vcc

TMP

T^SH

T^STOP

t

Css

T^ss

2V

Primary

Current

0A

0.8V

ISEN

t

3.5V

2V

DELAY

0.3V

t

Vout

t

PFC_STOP

NORMAL

OPERATION LOAD

OVER

NORMAL

OPERATION

START-UPSOFT-START

OVERLOAD

SHUTDOWN

SOFT-START

MIN. POWER

This function is realized with pin 2 (DELAY), by means of a capacitor C

and a parallel

Delay

resistor R

connected to ground. As the voltage on the ISEN pin exceeds 0.8V the first

Delay

OCP comparator, in addition to discharging C , turns on an internal current generator that

SS

sources 150µA from the DELAY pin and charges C

. During an overload/short-circuit the

Delay

OCP comparator and the internal current source will be repeatedly activated and C

will

Delay

be charged with an average current that depends essentially on the time constant of the

current sense filtering circuit, on C and the characteristics of the resonant circuit; the

SS

discharge due to R

can be neglected, considering that the associated time constant is

Delay

typically much longer.

This operation will go on until the voltage on C

reaches 2V, which defines the time T

.

SH

Delay

There is not a simple relationship that links T to C

, thus it is more practical to

SH

Delay

determine C

experimentally. As a rough indication, with C

= 1µF T will be in the

Delay

Delay SH

order of 100ms.

Once C is charged at 2V the internal switch that discharges C is forced low

Delay

SS

continuously regardless of the OCP comparator's output, and the 150µA current source is

continuously on, until the voltage on C reaches 3.5V. This phase lasts:

Delay

T

_MP= 10 ⋅ C_Delay

with T is expressed in ms and C

in µF. During this time the L6599 runs at a frequency

MP

Delay

close to f

(see Chapter 7.3: Soft-start) to minimize the energy inside the resonant circuit.

start

As the voltage on C

is 3.5V, the device stops switching and the PFC_STOP pin is pulled

Delay

low. Also the internal generator is turned off, so that C

will now be slowly discharged by

Delay

R

. The IC will restart when the voltage on C

will be less than 0.3V, which will take:

Delay

3.5

0.3

T_STOP= R_Delay⋅ C

-------

_Delayln

≈ 2.5R_Delay⋅ C_Delay

26/36

L6599

Application information

The timing diagram of Figure 31 shows this operation.

Note that if during T the supply voltage of the L6599 (Vcc) falls below the UVLO

STOP

threshold the IC keeps memory of the event and will not restart immediately after V

CC

exceeds the start-up threshold if V(DELAY) is still higher than 0.3V. Also the PFC_STOP pin

will stay low as long as V(DELAY) is greater than 0.3V. Note also that in case there is an

overload lasting less than T , the value of T for the next overload will be lower if they are

SH

close to one another.

7.5

Latched shutdown

The device is equipped with a comparator having the non-inverting input externally available

at pin 8 (DIS) and with the inverting input internally referenced to 1.85V. As the voltage on

the pin exceeds the internal threshold, the IC is immediately shut down and its consumption

reduced at a low value. The information is latched and it is necessary to let the voltage on

the Vcc pin go below the UVLO threshold to reset the latch and restart the IC.

This function is useful to implement a latched overtemperature protection very easily by

biasing the pin with a divider from an external reference voltage, where the upper resistor is

an NTC physically located close to a heating element like the MOSFET, or the secondary

diode or the transformer.

An OVP can be implemented as well, e.g. by sensing the output voltage and transferring an

overvoltage condition via an optocoupler.

7.6

Line sensing function

This function basically stops the IC as the input voltage to the converter falls below the

specified range and lets it restart as the voltage goes back within the range. The sensed

voltage can be either the rectified and filtered mains voltage, in which case the function will

act as a brownout protection, or, in systems with a PFC pre-regulator front-end, the output

voltage of the PFC stage, in which case the function will serve as power-on and power-off

sequencing.

L6599 shutdown upon input undervoltage is accomplished by means of an internal

comparator, as shown in the block diagram of Figure 32, whose non-inverting input is

available at pin 7 (LINE). The comparator is internally referenced to 1.25V and disables the

IC if the voltage applied on the LINE pin is below the internal reference. Under these

conditions the soft-start is discharged, the PFC_STOP pin is open and the consumption of

the IC is reduced. PWM operation is re-enabled as the voltage on the pin is above the

reference. The comparator is provided with current hysteresis instead of a more usual

voltage hysteresis: an internal 1 µA current sink is ON as long as the voltage on the LINE pin

is below the reference and is OFF if the voltage is above the reference.

This approach provides an additional degree of freedom: it is possible to set the ON

threshold and the OFF threshold separately by properly choosing the resistors of the

external divider (see below). With voltage hysteresis, instead, fixing one threshold

automatically fixes the other one depending on the built-in hysteresis of the comparator.

27/36

Application information

Figure 32. Line sensing function: internal block diagram and timing diagram

L6599

With reference to Figure 32 the following relationships can be established for the ON

(Vin ) and OFF (Vin

) thresholds of the input voltage:

ON

OFF

Vin_ON– 1.25

–6

1.25

R_H

----------------------------------

= 15 ⋅ 10 + -----------

R_H

Vin_OFF– 1.25

------------------------------------

1.25

R_H

= -----------

R_H

which, solved for R and R , yield:

H

L

Vin_ON– Vin_OFF

R_H= ------------------------------------------

15 ⋅ 10^–6

1.25

Vin_OFF– 1.25

------------------------------------

⋅

R_L= R_H

While the line undervoltage is active there is no PWM activity, thus the V voltage (if not

CC

supplied by another source) continuously oscillates between the start-up and the UVLO

thresholds, as shown in the timing diagram of Figure 32.

As an additional measure of safety (e.g. in case the low-side resistor is open or missing, or

in non-power factor corrected systems in case of abnormally high input voltage) if the

28/36

L6599

Application information

voltage on the pin exceeds 7V the device is shutdown. If its supply voltage is always above

the UVLO threshold, the IC will restart as the voltage falls below 7V.

The LINE pin, while the device is operating, is a high impedance input connected to high

value resistors, thus it is prone to pick up noise, which might alter the OFF threshold or give

origin to undesired switch-off of the IC during ESD tests. It is possible to bypass the pin to

ground with a small film capacitor (e.g. 1-10 nF) to prevent any malfunctioning of this kind. If

the function is not used the pin has to be connected to a voltage greater than 1.25V but

lower than 6V (worst-case value of the 7V threshold).

7.7

Bootstrap section

The supply of the floating high-side section is obtained by means of a bootstrap circuitry.

This solution normally requires a high voltage fast recovery diode to charge the bootstrap

capacitor C

. In the L6599 a patented integrated structure, replaces this external diode.

BOOT

It is realized by means of a high voltage DMOS, working in the third quadrant and driven

synchronously with the low side driver (LVG), with a diode in series to the source, as shown

in Figure 33.

Figure 33. Bootstrap supply: internal bootstrap synchronous diode

L6599

Vcc

12

16

VBOOT

CBOOT

LVG

14

OUT

The diode prevents any current can flow from the VBOOT pin back to V in case that the

CC

supply is quickly turned off when the internal capacitor of the pump is not fully discharged.

To drive the synchronous DMOS it is necessary a voltage higher than the supply voltage

V

. This voltage is obtained by means of an internal charge pump (Figure 33).

CC

The bootstrap structure introduces a voltage drop while recharging C

(i.e. when the low

BOOT

side driver is on), which increases with the operating frequency and with the size of the

external power MOSFET. It is the sum of the drop across the r and the forward drop

(DS)ON

across the series diode. At low frequency this drop is very small and can be neglected but,

as the operating frequency increases, it must be taken into account. In fact, the drop

reduces the amplitude of the driving signal and can significantly increase the R

external high-side MOSFET and then its conductive loss.

of the

(DS)ON

29/36

Application information

L6599

This concern applies to converters designed with a high resonance frequency (indicatively,

> 150 kHz), so that they run at high frequency also at full load. Otherwise, the converter will

run at high frequency only at light load, where the current flowing in the MOSFETs of the

half-bridge leg is lower, so that, generally, an r

rise is not an issue. However, it is wise

(DS)ON

to check this point anyway and the following equation is useful to compute the drop on the

bootstrap driver:

Q_g

--------------------

R_(DS)ON+ V_F

V

_Drop= I

r

_{Charge (DS)ON}+ V_F=

T_Charge

where Q is the gate charge of the external power MOS, r

is the on-resistance of the

g

(DS)ON

bootstrap DMOS (150 , typ.) and T

is the ON-time of the bootstrap driver, which

charge

equals about half the switching period minus the dead time T . For example, using a

D

MOSFET with a total gate charge of 30nC, the drop on the bootstrap driver is about 3V at a

switching frequency of 200kHz:

30 ⋅ 10^–9

------------------------------------------------------------

150 + 0.6= 2.7V

V_Drop

=

2.5 ⋅ 10^–6– 0.3 ⋅ 10^–6

If a significant drop on the bootstrap driver is an issue, an external ultra-fast diode can be

used, thus saving the drop on the r of the internal DMOS.

(DS)ON

30/36

L6599

Application information

7.8

Application example

Figure 34. EVAL6599-90W demo board, 90W adapter with L6563 & L6599: electrical schematic

31/36

Application information

Table 5.

L6599

EVAL6599-90W demo board, 90W adapter with L6563 & L6599: evaluation

data

Vin = 115Vac

Pout

Vin = 230Vac

Vout

[V]

Iout

[W]

Eff.

%

Vout

[V]

Iout

[A]

Pout

[W]

Eff.

%

[A]

[W]

18.95

18.97

18.98

18.99

19.00

19.01

4.71

3.72

2.7

89.25

70.49

51.22

32.46

18.99

9.50

4.75

1.52

1.01

0.51

0.25

0

99.13

78.00

56.55

36.00

21.70

11.30

5.86

3

90.04

90.38

90.57

90.16

87.51

84.03

81.06

50.70

50.38

47.53

37.44

---

18.95

18.96

18.97

18.98

18.99

19.00

19.01

4.71

3.72

2.7

89.25

70.53

51.22

32.46

18.99

9.50

4.75

1.52

1.01

0.51

0.25

0

97.23

76.74

55.85

35.57

21.30

10.87

5.77

2.4

91.80

91.91

91.71

91.24

89.15

87.40

82.32

63.37

59.97

51.33

36.89

---

1.71

1.0

1.71

1.0

0.5

0.25

0.080

0.053

0.027

0.013

0

0.25

0.080

0.053

0.027

0.013

0

2

1.68

1

1.08

0.66

0.28

0.67

0.34

32/36

L6599

Package mechanical data

8

Package mechanical data

®

In order to meet environmental requirements, ST offers these devices in ECOPACK

packages. These packages have a Lead-free second level interconnect. The category of

second Level Interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97. The maximum ratings related to soldering

conditions are also marked on the inner box label. ECOPACK is an ST trademark.

ECOPACK specifications are available at: www.st.com.

Table 6.

Dim.

Plastic DIP-16 mechanical data

mm.

inch

Typ

Min

Typ

Max

Min

Max

a1

0.51

0.020

B

b

0.77

1.65

0.030

0.065

0.5

0.020

0.010

b1

0.25

D

E

e

20

0.787

8.5

2.54

17.78

0.335

0.100

0.700

e3

F

I

7.1

5.1

0.280

0.201

L

3.3

0.130

Z

1.27

0.050

Figure 35. Plastic DIP-16 package dimensions

33/36

Package mechanical data

L6599

Table 7.

Dim.

SO16N mechanical data

mm.

inch

Typ

Min

Typ

Max

Min

Max

A

1.75

0.25

0.069

0.009

a1

0.1

0.004

a2

b

1.6

0.063

0.018

0.010

0.35

0.19

0.46

0.25

0.014

0.007

b1

C

0.5

0.020

c1

D(1)

E

45°

10

(typ.)

0.386

0.228

9.8

5.8

0.394

0.244

6.2

e

1.27

8.89

0.050

0.350

e3

F(1)

G

3.8

4.60

0.4

4.0

0.150

0.181

0.150

0.157

0.208

0.050

5.30

1.27

L

M

S

0.62

0.024

8°(max.)

Figure 36. Package dimensions

34/36

L6599

Revision history

9

Revision history

Table 8.

Date

Revision history

Revision

Changes

15-May-2006

1

Initial release

35/36

L6599

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the

right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any

time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no

liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this

document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products

or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such

third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS

OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZE REPRESENTATIVE OF ST, ST PRODUCTS ARE NOT DESIGNED,

AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS,

NOR IN PRODUCTS OR SYSTEMS, WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR

SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void

any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any

liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

36/36

型号:	L6599D
Brand Name：	STMicroelectronics
是否Rohs认证：	符合
生命周期：	Not Recommended
IHS 制造商：	STMICROELECTRONICS
零件包装代码：	SOIC
包装说明：	SOP, SOP16,.25
针数：	16
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	12 weeks
风险等级：	7.07
Samacsys Confidence：	3
Samacsys Status：	Released
Samacsys PartID：	4392
Samacsys Pin Count：	16
Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	Small Outline Packages
Samacsys Footprint Name：	ST SO-16N
Samacsys Released Date：	2015-04-16 09:48:08
Is Samacsys：	N
模拟集成电路 - 其他类型：	SWITCHING CONTROLLER
控制模式：	VOLTAGE-MODE
控制技术：	RESONANT CONTROL
最大输入电压：	16 V
最小输入电压：	8.85 V
标称输入电压：	15 V
JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e4
长度：	9.9 mm
湿度敏感等级：	3
功能数量：	1
端子数量：	16
最大输出电流：	0.8 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP16,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
电源：	15 V
认证状态：	Not Qualified
座面最大高度：	1.75 mm
子类别：	Power Management Circuits
最大供电电流 (Isup)：	2 mA
标称供电电压 (Vsup)：	15 V
表面贴装：	YES
切换器配置：	PUSH-PULL
最大切换频率：	500 kHz
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
宽度：	3.9 mm
Base Number Matches：	1

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