designed to conduct through it’s intrinsic body diode during
transient intervals before it turns on, eliminating the need for
an external diode.
Frequency Synchronization
(SYNC/MODE Pin) (Continued)
Synchronous rectification is disabled and the NFET con-
ducts through it’s body diode during the second part of each
cycle while in PFM mode to reduce quiescent current asso-
ciated with the synchronous rectifier’s control circuitry. The
synchronous rectifier may also remain off in PWM mode
when duty cycles are short due to high input-output voltage
differentials or light loads, when there is insufficient time for
the synchronous rectifier to activate. The body diode of the
NFET is also used under these conditions. To increase effi-
ciency in PFM or short duty-cycle PWM conditions, place an
external Schottky diode from PGND to SW. Contact the
Portable Power applications group at National Semiconduc-
tor, if interested in a device with synchronous rectification in
PFM mode.
over/undershoot. Note that sharp edged signals from a pulse
or function generator can develop under/overshoot as high
as 10V at the end of an improperly terminated cable.
Drive the SYNC/MODE pin using a signal with a slew rate
faster than 5V/100µs. Use a comparator Schmitt trigger or
logic gate to drive the SYNC/MODE pin. Do not leave the pin
floating of allow it to linger between logic levels. These
measures will prevent output voltage errors that could oth-
erwise occur in response to an indeterminate logic state.
Overvoltage Protection
The LM2612 has an over-voltage comparator that prevents
the output voltage from rising too high when the device is left
in PWM mode under low-load conditions. Otherwise, the
output voltage could rise out of regulation from the minimum
energy transferred per cycle due to the 200ns minimum
on-time of the PFET switch while in PWM mode. When the
output voltage rises by 30mV over its regulation threshold,
the OVP comparator inhibits PWM operation to skip pulses
until the output voltage returns to the regulation threshold. In
over voltage protection, output voltage and ripple increase
slightly.
Current Limiting
A current limit feature allows the LM2612 to protect itself and
external components during overload conditions. Current
limiting is implemented using an independent internal com-
parator that trips at 850mA max, (980mA for B grade de-
vices). In PWM mode, cycle-by-cycle current limiting is nor-
mally used. If an excessive load pulls the output voltage
down to approximately 0.7V, then the device switches to a
timed current limit mode. In timed current limit mode the
internal P-FET switch is turned off after the current compara-
tor trips and the beginning of the next cycle is inhibited for
2.5µs to force the instantaneous inductor current to ramp
down to a safe value. PFM mode also uses timed current
limit operation. The synchronous rectifier is off in timed cur-
rent limit mode. Timed current limit prevents the loss of
current control seen in some products when the output volt-
age is pulled low in serious overload conditions.
Shutdown Mode
Setting the EN digital input pin low to SGND places the
LM2612 in a 0.1uA (typ) shutdown mode. During shutdown,
the PFET switch, NFET synchronous rectifier, reference,
control and bias of the LM2612 are turned off. Setting EN
high to VDD enables normal operation. While turning on, soft
start is activated. EN is a CMOS Schmitt trigger digital input
with thresholds that scale with the input voltage at VDD. The
nominal logic thresholds are approximately 0.71VDD and
0.55VDD for the high and low thresholds respectively. Drive
EN using CMOS logic referenced to the supply voltage at the
VDD pin of the LM2612.
Current Limiting and PWM Mode
Transient Response
Considerations
EN must be set low to turn off the LM2612 during power-up
and undervoltage conditions when the supply is less than the
2.8V minimum operating voltage. The LM2612 is designed
for mobile phones and similar applications where power
sequencing is determined by the system controller and in-
ternal UVLO (Under Voltage LockOut) circuitry is unneces-
sary. The LM2612 has no UVLO circuitry. Although the
LM2612 exhibited safe behavior during pre-production
evaluation while enabled at low input voltages, this is not
guaranteed.
The LM2612 was designed for fast response to moderate
load steps. Harsh transient conditions during loads above
300mA can cause the inductor current to swing up to the
850mA current limit, resulting in PWM mode jitter or instabil-
ity from activation of the current limit comparator. To avoid
this jitter or instability, do not power-up or start the LM2612
into a full load (loads near or above 400mA). Do not change
operating modes or output voltages when operating at a full
load. Avoid extremely sharp and wide-ranging load steps to
<
>
full load, such as from 30mA to 350mA.
Internal Synchronous Rectification
Pin Selectable Output Voltage
While in PWM mode, the LM2612 uses an internal NFET as
a synchronous rectifier to improve efficiency by reducing
rectifier forward voltage drop and associated power loss. In
general, synchronous rectification provides a significant im-
provement in efficiency whenever the output voltage is rela-
tively low compared to the voltage drop across an ordinary
rectifier diode.
The LM2612 features pin-selectable output voltage to elimi-
nate the need for external feedback resistors. The output
can be set to 1.05V, 1.3V, 1.5V or 1.8V by configuring the
VID0 and VID1 pins. See Setting the Output Voltage in the
Application Information section for further details.
Under moderate and heavy loads, the internal NFET syn-
chronous rectifier is turned on during the inductor current
down-slope in the second part of each cycle. The synchro-
nous rectifier is turned off prior to the next cycle, or when the
inductor current ramps near zero at light loads. The NFET is
Soft-Start
The LM2612 has soft start to reduce current inrush during
power-up and startup. This reduces stress on the LM2612
and external components. It also reduces startup transients
on the power source.
15
www.national.com
QQ：528164397 复制
