LM5025A
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SNVS293F –DECEMBER 2004–REVISED AUGUST 2016
Feature Description (continued)
7.3.6 Volt Second Clamp
The Volt × Second Clamp comparator compares the ramp signal (RAMP) to a fixed 2.5-V reference. By proper
selection of RFF and CFF, the maximum ON-time of the main switch can be set to the desired duration. The ON-
time set by Volt × Second Clamp varies inversely with the line voltage because the RAMP capacitor is charged
by a resistor connected to VIN while the threshold of the clamp is a fixed voltage (2.5 V). An example illustrates
the use of the Volt × Second Clamp comparator to achieve a 50% duty cycle limit, at 200 KHz, at a 48-V line
input: A 50% duty cycle at a 200 KHz requires a 2.5 µs of ON-time. At 48-V input the Volt × Second product is
120 V × µs (48 V × 2.5 µs). To achieve this clamp level, use Equation 3 and Equation 4:
RFF × CFF = VIN × TON / 2.5 V
48 × 2.5 µ / 2.5 = 48 µ
(3)
(4)
Select CFF = 470 pF
RFF = 102 kΩ
The recommended capacitor value range for CFF is 100 pF to 1000 pF.
The CFF ramp capacitor is discharged at the conclusion of every cycle by an internal discharge switch controlled
by either the internal clock or by the V × S Clamp comparator, whichever event occurs first.
7.3.7 Current Limit
The LM5025A contains two modes of overcurrent protection. If the sense voltage at the CS1 input exceeds 0.5 V
the present power cycle is terminated (cycle-by-cycle current limit). If the sense voltage at the CS2 input exceeds
0.5 V, the controller terminates the present cycle, discharge the soft-start capacitor and reduce the soft-start
current source to 1 µA. The soft-start (SS) capacitor is released after being fully discharged and slowly charges
with a 1-µA current source. When the voltage at the SS pin reaches approximately 1 V, the PWM comparator
produces the first output pulse at OUT_A. After the first pulse occurs, the soft-start current source reverts to the
normal 20-µA level. Fully discharging and then slowly charging the SS capacitor protects a continuously
overloaded converter with a low duty cycle hiccup mode.
These two modes of overcurrent protection allow the user great flexibility to configure the system behavior in
over-load conditions. If it is desired for the system to act as a current source during an overload, then the CS1
cycle-by-cycle current limiting must be used. In this case the current sense signal must be applied to the CS1
input and the CS2 input must be grounded. If during an overload condition it is desired for the system to briefly
shutdown, followed by soft-start retry, then the CS2 hiccup current limiting mode must be used. In this case the
current sense signal must be applied to the CS2 input and the CS1 input must be grounded. This shutdown and
soft-start retry repeats indefinitely while the overload condition remains. The hiccup mode greatly reduces the
thermal stresses to the system during heavy overloads. The cycle-by-cycle mode has higher system thermal
dissipations during heavy overloads, but provides the advantage of continuous operation for short duration
overload conditions.
It is possible to use both overcurrent modes concurrently, whereby slight overload conditions activate the CS1
cycle-by-cycle mode while more severe overloading activates the CS2 hiccup mode. Generally the CS1 input is
always configured to monitor the main switch FET current each cycle. The CS2 input can be configured in
several different ways depending upon the system requirements.
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The CS2 input can also be set to monitor the main switch FET current except scaled to a higher threshold
than CS1
An external overcurrent timer can be configured which trips after a predetermined overcurrent time, driving
the CS2 input high, initiating a hiccup event.
In a closed-loop voltage regulaton system, the COMP input rises to saturation when the cycle-by-cycle
current limit is active. An external filter and delay timer and voltage divider can be configured between the
COMP pin and the CS2 pin to scale and delay the COMP voltage. If the CS2 pin voltage reaches 0.5 V a
hiccup event will initiate.
TI recommends a small RC filter placed near the controller for each of the CS pins. The CS1 input has an
internal FET which discharges the current sense filter capacitor at the conclusion of every cycle, to improve
dynamic performance. This same FET remains on an additional 50 ns at the start of each main switch cycle to
attenuate the leading edge spike in the current sense signal. The CS2 discharge FET only operates following a
CS2 event, UVLO, and thermal shutdown.
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