LNK616PG各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

LNK603-606/613-616

®

LinkSwitch-II Family

Energy-Efﬁcient, Accurate CV/CC Switcher

for Adapters and Chargers

Product Highlights

Dramatically Simpliﬁes CV/CC Converters

• Eliminates optocoupler and all secondary CV/CC control circuitry

• Eliminates all control loop compensation circuitry

Advanced Performance Features

• Compensates for transformer inductance tolerances

• Compensates for input line voltage variations

• Compensates for cable voltage drop (LNK61X series)

• Compensates for external component temperature variations

• Very tight IC parameter tolerances using proprietary trimming

technology

Wide Range

High Voltage

DC Input

D

S

FB

LinkSwitch-II

BP/M

• Frequency jittering greatly reduces EMI ﬁlter cost

• Even tighter output tolerances achievable with external resistor

selection/trimming

PI-4960-011510

(a) Typical Application Schematic

• Programmable switching frequency up to 85 kHz to reduce

transformer size

V_O

±±5

Advanced Protection/Safety Features

• Auto-restart protection reduces power delivered by >95% for

output short circuit and control loop faults (open and shorted

components)

±ꢀ15

• Hysteretic thermal shutdown – automatic recovery reduces

power supply returns from the ﬁeld

• Meets high voltage creepage requirements between DRAIN and

all other pins both on the PCB and at the package

PI-4916-14ꢀ118

(b) Output Characteristic

I_O

EcoSmart^®– Energy Efﬁcient

Figure 1. Typical Application/Performance – Not a Simpliﬁed Circuit (a) and

Output Characteristic Envelope (b). (see Application Section for

more information).

• Easily meets all global energy efﬁciency regulations

• No-load consumption below 30 mW at 230 VAC with optional

external bias winding

• ON/OFF control provides constant efﬁciency down to very light

loads – ideal for CEC and ENERGY STAR 2.0 regulations

• No current sense resistors – maximizes efﬁciency

Output Power Table

85-265 VAC

Product³

Adapter¹

2.5 W

Open Frame²

Green Package

• Halogen free and RoHS compliant package

LNK603/613PG/DG

LNK604/614PG/DG

LNK605/615PG/DG

LNK606/616PG/GG/DG

3.3 W

3.5 W

4.1 W

Applications

4.5 W

5.1 W

• Chargers for cell/cordless phones, PDAs, MP3/portable audio

devices, adapters, LED drivers, etc.

5.5 W

6.1 W

Table 1. Output Power Table.

Description

Notes:

The LinkSwitch-II dramatically simpliﬁes low power CV/CC

charger designs by eliminating an optocoupler and secondary

control circuitry. The device introduces a revolutionary control

technique to provide very tight output voltage and current

regulation, compensating for transformer and internal parameter

tolerances along with input voltage variations.

1. Minimum continuous power in a typical non-ventilated enclosed adapter

measured at +50 °C ambient, device, T_J<100 °C.

2. Maximum practical continuous power in an open frame design with adequate

heatsinking, measured at 50 °C ambient (see Key Applications Considerations

section for more information).

3. Packages: P: DIP-8C, G: SMD-8C, D: SO-8C.

The device incorporates a 700 V power MOSFET, a novel ON/OFF

control state machine, a high voltage switched current source for

self biasing, frequency jittering, cycle-by-cycle current limit and

hysteretic thermal shutdown circuitry onto a monolithic IC.

www.powerint.com

January 2010

LNK603-606/613-616

DRAIN

(D)

REGULATOR

6 V

BYPASS

(BP/M)

+

-

6 V

5 V

FB

OUT

+

Reset

V_ILIMIT

D

Q

STATE

MACHINE

FEEDBACK

V_TH

-

(FB)

t_SAMPLE-OUT

I_LIM

DC_MAX

Drive

V_ILIMIT

CABLE DROP

COMPENSATION

FAULT

Auto-Restart

Open-Loop

FB

6.5 V

THERMAL

SHUTDOWN

INDUCTANCE

CORRECTION

DC_MAX

t_SAMPLE-INPUT

SAMPLE

t_SAMPLE-OUT

DELAY

t_SAMPLE-INPUT

OSCILLATOR

SOURCE

(S)

+

-

I_LIM

SOURCE

(S)

V_ILIMIT

CONSTANT

CURRENT

Current Limit

Comparator

LEADING

EDGE

BLANKING

PI-4908-041508

Figure 2

Functional Block Diagram.

Pin Functional Description

DRAIN (D) Pin:

P Package (DIP-8C)

G Package (SMD-8C)

This pin is the power MOSFET drain connection. It provides

internal operating current for both start-up and steady-state

operation.

D Package (SO-8C)

FB

S

1

2

8

7

1

2

8

7

FB

S

BYPASS/MULTI-FUNCTIONAL PROGRAMMABLE

(BP/M) Pin:

This pin has multiple functions:

1. It is the connection point for an external bypass capacitor for

the internally generated 6 V supply.

BP/M

6

5

6

5

S

4

D

4

2. It is a mode selection for the cable drop compensation for

LNK61X series.

3a

3b

FEEDBACK (FB) Pin:

PI-3491-012808

During normal operation, switching of the power MOSFET is

controlled by this pin. This pin senses the AC voltage on the bias

winding. This control input regulates both the output voltage in

CV mode and output current in CC mode based on the ﬂyback

voltage of the bias winding. The internal inductance correction

circuit uses the forward voltage on the bias winding to sense the

bulk capacitor voltage.

Figure 3. Pin Conﬁguration.

SOURCE (S) Pin:

This pin is internally connected to the output MOSFET source for

high voltage power and control circuit common returns.

2

Rev. F 01/10

www.powerint.com

LNK603-606/613-616

Auto-Restart and Open-Loop Protection

LinkSwitch-II Functional Description

In the event of a fault condition such as an output short or an

open loop condition the LinkSwitch-II enters into an appropriate

protection mode as described below.

The LinkSwitch-II combines a high voltage power MOSFET

switch with a power supply controller in one device. Similar to

the LinkSwitch-LP and TinySwitch-III it uses ON/OFF control to

regulate the output voltage. In addition, the switching frequency

is modulated to regulate the output current to provide a

constant current characteristic. The LinkSwitch-II controller

consists of an oscillator, feedback (sense and logic) circuit, 6 V

regulator, over-temperature protection, frequency jittering,

current limit circuit, leading-edge blanking, inductance

correction circuitry, frequency control for constant current

regulation and ON/OFF state machine for CV control.

In the event the FEEDBACK pin voltage during the ﬂyback

period falls below 0.7 V before the FEEDBACK pin sampling

delay (~2.5 ms) for a duration in excess of ~450 ms (auto-restart

on-time (t_AR-ON) the converter enters into auto-restart, wherein

the power MOSFET is disabled for 2 seconds (~18% auto-

restart duty cycle). The auto-restart alternately enables and

disables the switching of the power MOSFET until the fault

condition is removed.

Inductance Correction Circuitry

In addition to the conditions for auto-restart described above, if

the sensed FEEDBACK pin current during the forward period of

the conduction cycle (switch “on” time) falls below 120 mA, the

converter annunciates this as an open-loop condition (top

resistor in potential divider is open or missing) and reduces the

auto-restart time from 450 msec to approximately 6 clock cycles

(90 ms), whilst keeping the disable period of 2 seconds.

If the primary magnetizing inductance is either too high or low

the converter will automatically compensate for this by adjusting

the oscillator frequency. Since this controller is designed to

operate in discontinuous-conduction mode the output power is

directly proportional to the set primary inductance and its

tolerance can be completely compensated with adjustments to

the switching frequency.

Over-Temperature Protection

Constant Current (CC) Operation

The thermal shutdown circuitry senses the die temperature. The

threshold is set at 142 °C typical with a 60 °C hysteresis. When

the die temperature rises above this threshold (142 °C) the

power MOSFET is disabled and remains disabled until the die

temperature falls by 60 °C, at which point the MOSFET is

re-enabled.

As the output voltage and therefore the ﬂyback voltage across

the bias winding increases, the FEEDBACK pin voltage increases.

The switching frequency is adjusted as the FEEDBACK pin

voltage increases to provide a constant output current regulation.

The constant current circuit and the inductance correction

circuit are designed to operate concurrently in the CC region.

Current Limit

Constant Voltage (CV) Operation

The current limit circuit senses the current in the power

MOSFET. When this current exceeds the internal threshold

(I_LIMIT), the power MOSFET is turned off for the remainder of that

cycle. The leading edge blanking circuit inhibits the current limit

comparator for a short time (t_LEB) after the power MOSFET is

turned on. This leading edge blanking time has been set so that

current spikes caused by capacitance and rectiﬁer reverse

recovery time will not cause premature termination of the MOSFET

conduction. The LinkSwitch-II also contains a “di/dt” correction

feature to minimize CC variation across the input line range.

As the FEEDBACK pin approaches V_FBthfrom the constant

current regulation mode, the power supply transitions into CV

operation. The switching frequency at this point is at its

maximum value, corresponding to the peak power point of the

CCCV characteristic. The controller regulates the feedback pin

voltage to remain at V_FBthusing an ON/OFF state-machine. The

FEEDBACK pin voltage is sampled 2.5 ms after the turn-off of

the high voltage switch. At light loads the current limit is also

reduced to decrease the transformer ﬂux density.

Output Cable Compensation

6.0 V Regulator

This compensation provides a constant output voltage at the

end of the cable over the entire load range in CV mode. As the

converter load increases from no-load to the peak power point

(transition point between CV and CC) the voltage drop introduced

across the output cable is compensated by increasing the

FEEDBACK pin reference voltage. The controller determines the

output load and therefore the correct degree of compensation

based on the output of the state machine. Cable drop

compensation for a 24 AWG (0.3 W) cable is selected with

C_BP= 1 mF and for a 26 AWG (0.49 W) cable with C_PB= 10 mF.

The 6 V regulator charges the bypass capacitor connected to

the BYPASS pin to 6 V by drawing a current from the voltage on

the DRAIN, whenever the MOSFET is off. The BYPASS pin is

the internal supply voltage node. When the MOSFET is on, the

device runs off of the energy stored in the bypass capacitor.

Extremely low power consumption of the internal circuitry

allows the LinkSwitch-II to operate continuously from the

current drawn from the DRAIN pin. A bypass capacitor value of

either 1 mF or 10 mF is sufﬁcient for both high frequency

decoupling and energy storage.

3

www.powerint.com

Rev. F 01/10

LNK603-606/613-616

Applications Example

C6

1 nF

R7

100 V 200 Ω

L1

T1

EE16

1.5 mH

5 V, 555 mA

5

3

10

D7

C3

820 pF

1 kV

R2

SS14

R8

470 kΩ

8

1

200 Ω

D1

D2

C7

1N4007 1N4007

DC

Output

680 µF

10 V

R3

RF1

8.2 Ω

2 W

300 Ω

2

4

VR1

2MM5230B-7

4.7 V

C1

4.7 µF

400 V

C2

4.7 µF

400 V

D5

1N4007

AC

Input

NC

D6

LL4148

LinkSwitch-II

R5

U1

13 kΩ

LNK613DG

1%

D

D3

D4

FB

1N4007 1N4007

BP

R4

S

R6

8.87 kΩ

1%

C4

1 µF

25 V

6.2 kΩ C5

10 µF

16 V

PI-5111-050808

Figure 4.

Energy Efﬁcient USB Charger Power Supply (74% Average Efﬁciency, <30 mW No-load Input Power).

compensation. A 1 mF value selects the standard compensation.

A 10 mF value selects the enhanced compensation. Table 2

shows the amount of compensation for each device and

bypass capacitor value. The LNK60x devices do not provide

cable drop compensation.

Circuit Description

This circuit shown in Figure 4 is conﬁgured as a primary-side

regulated ﬂyback power supply utilizing the LNK613DG. With

an average efﬁciency of 74% and <30 mW no-load input power

this design easily exceeds the most stringent current energy

efﬁciency requirements.

The optional bias supply formed by D6 and C5 provides the

operating current for U1 via resistor R4. This reduces the

no-load consumption from ~200 mW to <30 mW and also

increases light load efﬁciency.

Input Filter

AC input power is rectiﬁed by diodes D1 through D4. The

rectiﬁed DC is ﬁltered by the bulk storage capacitors C1 and

C2. Inductor L1, C1 and C2 form a pi (π) ﬁlter, which attenuates

conducted differential-mode EMI noise. This conﬁguration

along with Power Integrations transformer E-shield^™technology

allow this design to meet EMI standard EN55022 class B with

good margin without requiring a Y capacitor, even with the

output connected to safety earth ground. Fusible resistor RF1

provides protection against catastrophic failure. This should be

suitably rated (typically a wire wound type) to withstand the

instantaneous dissipation while the input capacitors charge

when ﬁrst connected to the AC line.

The rectiﬁed and ﬁltered input voltage is applied to one side of

the primary winding of T1. The other side of the transformer’s

primary winding is driven by the integrated MOSFET in U1. The

leakage inductance drain voltage spike is limited by an RCD-R

clamp consisting of D5, R2, R3, and C3.

Output Rectiﬁcation

The secondary of the transformer is rectiﬁed by D7, a 1 A, 40 V

Schottky barrier type for higher efﬁciency, and ﬁltered by C7. If

lower efﬁciency is acceptable then this can be replaced with a

1 A PN junction diode for lower cost. In this application C7 was

sized to meet the required output voltage ripple speciﬁcation

without requiring a post LC ﬁlter. To meet battery self discharge

requirement the pre-load resistor has been replaced with a

series resistor and Zener network (R8 and VR1). However in

designs where this is not a requirement a standard 1 kW

resistor can be used.

LNK 613 Primary

The LNK613DG device (U1) incorporates the power switching

device, oscillator, CC/CV control engine, startup, and protection

functions. The integrated 700 V MOSFET provides a large drain

voltage margin in universal input AC applications, increasing

reliability and also reducing the output diode voltage stress by

allowing a greater transformer turns ratio. The device is

completely self-powered from the BYPASS pin and decoupling

capacitor C4. For the LNK61X devices, the bypass capacitor

value also selects the amount of output cable voltage drop

Output Regulation

The LNK613 regulates the output using ON/OFF control in the

constant voltage (CV) regulation region of the output character-

4

Rev. F 01/10

www.powerint.com

LNK603-606/613-616

istic and frequency control for constant current (CC) regulation.

The feedback resistors (R5 and R6) were selected using

standard 1% resistor values to center both the nominal output

voltage and constant current regulation thresholds.

LinkSwitch-II Output Cable Voltage Drop Compensation

BYPASS Pin

Output Voltage

Change Factor

Device

LNK613

Capacitor Value

1.035

1.055

1.045

1.065

1.050

1.070

1.060

1.090

1 mF

10 mF

1 mF

Key Application Considerations

LNK614

LNK615

LNK616

Output Power Table

10 mF

1 mF

The data sheet maximum output power table (Table 1) repre-

sents the maximum practical continuous output power level

that can be obtained under the following assumed conditions:

10 mF

1 mF

10 mF

1. The minimum DC input voltage is 90 V or higher at 85 VAC

input. The value of the input capacitance should be large

enough to meet these criteria for AC input designs.

2. Secondary output of 5 V with a Schottky rectiﬁer diode.

3. Assumed efﬁciency of 70%.

4. Discontinuous mode operation (K_P>1.3).

5. The part is board mounted with SOURCE pins soldered to a

sufﬁcient area of copper to keep the SOURCE pin tempera-

ture at or below 90 °C.

Table 2. Cable Compensation Change Factor vs Device and BYPASS Pin

Capacitor Value.

The output voltage that is entered into PIXls design spreadsheet

is the voltage at the end of the output cable when the power

supply is delivering maximum power. The output voltage at the

terminals of the supply is the value measured at the end of the

cable multiplied by the output voltage change factor.

LinkSwitch-II Layout Considerations

6. Ambient temperature of 50 °C for open frame designs and

an internal enclosure temperature of 60 °C for adapter

designs.

Circuit Board Layout

LinkSwitch-II is a highly integrated power supply solution that

integrates on a single die, both, the controller and the high

voltage MOSFET. The presence of high switching currents and

voltages together with analog signals makes it especially

important to follow good PCB design practice to ensure stable

and trouble free operation of the power supply. See Figure 5 for

a recommended circuit board layout for LinkSwitch-II.

Note: Higher output power are achievable if an output CC

tolerance > 10% is acceptable, allowing the device to be

operated at a higher SOURCE pin temperature.

Output Tolerance

LinkSwitch-II provides an overall output tolerance (including line,

component variation and temperature) of 5% for the output

voltage in CV operation and 10% for the output current during

CC operation over a junction temperature range of 0 °C to 100 °C

for the P/G package. For the D package (SO8) additional CC

variance may occur due to stress caused by the manufacturing

ﬂow (i.e. solder-wave immersion or IR reﬂow). A sample power

supply build is recommended to verify production tolerances for

each design.

When designing a printed circuit board for the LinkSwitch-II

based power supply, it is important to follow the following

guidelines:

Single Point Grounding

Use a single point (Kelvin) connection at the negative terminal of

the input ﬁlter capacitor for the LinkSwitch-II SOURCE pin and

bias winding return. This improves surge capabilities by

returning surge currents from the bias winding directly to the

input ﬁlter capacitor.

BYPASS Pin Capacitor Selection

For LinkSwitch-II 60x Family of Devices (without output

cable voltage drop compensation)

Bypass Capacitor

The BYPASS pin capacitor should be located as close as

possible to the SOURCE and BYPASS pins.

A 1 mF BYPASS pin capacitor is recommended. The capacitor

voltage rating should be greater than 7 V. The capacitor’s

dielectric material is not important but tolerance of capacitor

should be ≤ 50%. The capacitor must be physically located

close to the LinkSwitch-II BYPASS pin.

Feedback Resistors

Place the feedback resistors directly at the FEEDBACK pin of

the LinkSwitch-II device. This minimizes noise coupling.

Thermal Considerations

For LinkSwitch-II 61x Family of Devices (with output cable

voltage drop compensation)

The copper area connected to the SOURCE pins provides the

LinkSwitch-II heat sink. A good estimate is that the LinkSwitch-II

will dissipate 10% of the output power. Provide enough copper

area to keep the SOURCE pin temperature below 90 °C. Higher

temperatures are allowable only if an output current (CC)

tolerance above 10% is acceptable. In this case a maximum

SOURCE pin temperature below 110 °C is recommended to

provide margin for part to part R_DS(ON)variation.

The amount of output cable compensation can be selected with

the value of the BYPASS pin capacitor. A value of 1 mF selects

the standard cable compensation. A 10 mF capacitor selects

the enhanced cable compensation. Table 2 shows the amount

of compensation for each LinkSwitch-II device and capacitor

value. The capacitor can be either ceramic or electrolytic but

tolerance and temperature variation should be ≤ 50%.

5

www.powerint.com

Rev. F 01/10

LNK603-606/613-616

Output Filter

Capacitors

Output

Diode Snubber

Input Stage

Primary Clamp

R1

C1

R8

C6

T1

C2

R3

R4

D5

C3

D7

S

R1

U1

LinkSwitch-II

R5

L2

Feedback

Resistors

R2

FB

BP

D

D1

R6

C7

D2

D3

C4

C5

D4

Bypass

Capacitor

C8

D3

R9

Bypass Supply

Components

RF1

Preload

Resistor

Spark

Gap

AC

Input

DC

Output

PI-5110-050508

Figure 5.

PCB Layout Example Showing 5.1 W Design Using P Package.

Secondary Loop Area

Addition of a Bias Circuit for Higher Light Load Efﬁciency

and Lower No-load Input Power Consumption.

To minimize leakage inductance and EMI the area of the loop

connecting the secondary winding, the output diode and the

output ﬁlter capacitor should be minimized. In addition,

sufﬁcient copper area should be provided at the anode and

cathode terminal of the diode for heatsinking. A larger area is

preferred at the quiet cathode terminal. A large anode area can

increase high frequency radiated EMI.

The addition of a bias circuit can decrease the no-load input

power from ~200 mW down to less than 30 mW at 230 VAC

input. Light load efﬁciency also increases which may avoid the

need to use a Schottky barrier vs PN junction output diode

while still meeting average efﬁciency requirements.

Electrostatic Discharge Spark Gap

An trace is placed along the isolation barrier to form one

electrode of a spark gap. The other electrode on the secondary

is formed by the output return node. The spark gap directs

ESD energy from the secondary back to the AC input. The

trace from the AC input to the spark gap electrode should be

spaced away from other traces to prevent unwanted arcing

occurring and possible circuit damage.

The power supply schematic shown in Figure 4 has the bias

circuit incorporated. Diode D6, C5 and R4 form the bias circuit.

As the output voltage is less than 8 V, an additional transformer

winding is needed, AC stacked on top of the feedback winding.

This provides a high enough voltage to supply the BYPASS pin

even during low switching frequency operation at no-load.

In Figure 4 the additional bias winding (from pin 2 to pin 1) is

stacked on top of the feedback winding (pin 4 to pin 2). Diode

D6 rectiﬁes the output and C5 is the ﬁlter capacitor. A 10 uF

capacitor is recommended to hold up the bias voltage at low

switching frequencies. The capacitor type is not critical but the

Drain Clamp Optimization

LinkSwitch-II senses the feedback winding on the primary side

to regulate the output. The voltage that appears on the feed-

back winding is a reﬂection of the secondary winding voltage

while the internal MOSFET is off. Therefore any leakage

inductance induced ringing can affect output regulation. Optimizing

the drain clamp to minimize the high frequency ringing will give

the best regulation. Figure 6 shows the desired drain voltage

waveform compared to Figure 7 with a large undershoot due to

the leakage inductance induced ring. This will reduce the

output voltage regulation performance. To reduce this adjust

the value of the resistor in series with the clamp diode.

voltage rating should be above the maximum value of V_BIAS

.

The recommended current into the BYPASS pin is equal to IC

supply current (~0.5 mA) at the minimum bias winding voltage.

The BYPASS pin current should not exceed 3 mA at the maximum

bias winding voltage. The value of R4 is calculated according to

(V_BIAS– V_BP)/I_S2, where V_BIAS(10 V typ.) is the voltage across C5, I_S2

(0.5 mA typ.) is the IC supply current and V_BP(6.2 V typ.) is the

6

Rev. F 01/10

www.powerint.com

LNK603-606/613-616

An overshoot

is acceptable

Negative ring may

increase output

ripple and/or

degrade output

regulation

Figure 6. Desired Drain Voltage Waveform with Minimal Leakage

Ringing Undershoot.

Figure 7.

Undesirable Drain Voltage Waveform with Large Leakage

Ring Undershoot.

L1

1 mH

TI

EE13

5

10

8

D7

SL13

C3

R2

470 kΩ

820 pF

3

1 kV

D1

D2

C7

470 µF

10 V

1N4007 1N4007

DC

Output

1 kΩ

R3

300 Ω

RF1

8.2 Ω

2 W

2

4

C1

4.7 µF

400 V

C2

4.7 µF

400 V

AC

Input

D5

1N4007

NC

LinkSwitch-II

R5

U1

13 kΩ

LNK613DG

1%

D

D3

D4

FB

1N4007 1N4007

BP

S

R6

9.31 kΩ

1%

C4

1 µF

50 V

PI-5116-050808

Figure 8. LinkSwitch-II Flyback Power Supply Without Bias Supply.

former saturation and excessive leading edge current spikes.

LinkSwitch-II has a leading edge blanking time of 170 ns to

prevent premature termination of the ON-cycle.

BYPASS pin voltage. The parameters I_S2and V_BPare provided in

the parameter table of the LinkSwitch-II data sheet. Diode D6 can

be any low cost diode such as FR102, 1N4148 or BAV19/20/21.

3. Thermal check – At maximum output power, both minimum

and maximum input voltage and maximum ambient tempera-

ture; verify that temperature speciﬁcations are not exceeded

for LinkSwitch-II, transformer, output diodes and output

capacitors. Enough thermal margin should be allowed for

part-to-part variation of the R_DS(ON)of LinkSwitch-II, as speciﬁed

in the data sheet. To assure 10% CC tolerance a maximum

SOURCE pin temperature of 90 ºC is recommended.

Quick Design Checklist

As with any power supply design, all LinkSwitch-II designs

should be veriﬁed on the bench to make sure that component

speciﬁcations are not exceeded under worst-case conditions.

The following minimum set of tests is strongly recommended:

1. Maximum drain voltage – Verify that peak V_DSdoes not exceed

680 V at the highest input voltage and maximum output power.

2. Maximum drain current – At maximum ambient temperature,

maximum input voltage and maximum output load, verify

drain current waveforms at start-up for any signs of trans-

Design Tools

Up-to-date information on design tools can be found at the

Power Integrations web site: www.powerint.com

7

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Rev. F 01/10

LNK603-606/613-616

Absolute Maximum Ratings^(1,4)

Lead Temperature⁽³⁾.................................................................260 °C

Notes:

1. All voltages referenced to SOURCE, T_A= 25 °C.

2. Duration not to exceed 2 msec.

DRAIN Voltage .........................................................-0.3 V to 700 V

DRAIN Peak Current: LNK603/613...................320 (480) mA⁽⁴⁾

LNK604/614.................. 400 (600) mA⁽⁴⁾

LNK605/615.................. 504 (750) mA⁽⁴⁾

LNK606/616.................. 654 (980) mA⁽⁴⁾

3. 1/16 in. from case for 5 seconds.

Peak Negative Pulsed Drain Current ............................ -100 mA⁽²⁾

FEEDBACK Pin Voltage .................................................-0.3 V to 9 V

FEEDBACK Pin Current ................................................. ..... 100 mA

BYPASS Pin Voltage ..................................... .............-0.3 V to 9 V

Storage Temperature ........................................... -65 °C to 150 °C

Operating Junction Temperature.........................-40 °C to 150 °C

4. The higher peak DRAIN current is allowed while the DRAIN

voltage is simultaneously less than 400 V.

5. Maximum ratings speciﬁed may be applied, one at a time

without causing permanent damage to the product.

Exposure to Absolute Maximum ratings for extended

periods of time may affect product reliability.

Thermal Impedance

Thermal Impedance: P or G Package:

Notes:

(q_JA) ....................................70 °C/W⁽²⁾; 60 °C/W⁽³⁾1. Measured on pin 8 (SOURCE) close to plastic interface.

(q_JC)⁽¹⁾............................................... .........11 °C/W 2. Soldered to 0.36 sq. in. (232 mm²), 2 oz. (610 g/m²) copper clad.

D Package:

3. Soldered to 1 sq. in. (645 mm²), 2 oz. (610 g/m²) copper clad.

(q_JA.....................................100 °C/W⁽²⁾; 80 °C/W⁽³⁾

(q_JC)⁽¹⁾.......................... ...........................30 °C/W

Conditions

(Unless Otherwi^Jse Speciﬁed)

SOURCE = 0 V; T = 0 to 100 °C

Parameter

Symbol

Min

Typ

Max

Units

Control Functions

Output Frequency

T_J= 25 °C, V_FB= V_FBth

t_ON× I_FB= 2 mA-ms

(See Note 1,7)

LNK603/6

LNK613/6

59

58

66

65

73

72

f_OSC

kHz

Frequency Ratio

(Constant Current)

T_J= 25 °C

Between V_FB= 1.0 V and V_FB= 1.6 V

f_RATIO(CC)

f_RATIO(IC)

1.59

1.635

1.215

7

1.68

Frequency Ratio

(Inductance Correction)

Between t_ON× I_FB= 1.6 mA × ms

and t_ON× I_FB= 2 mA × ms

1.160

1.265

Peak-Peak Jitter Compared to

Average Frequency, T_J= 25 °C

Frequency Jitter

%

Ratio of Output Fre-

quency at Auto-Restart

T_J= 25 °C

Relative to f_OSC

f_OSC(AR)

DC_MAX

12

16.5

55

21

%

Maximum Duty Cycle

(Note 4,5)

LNK603/604P

LNK603/604D

1.815

1.855

1.835

1.775

1.935

1.975

1.935

1.840

1.880

1.860

1.800

1.960

2.000

1.960

1.865

1.905

1.885

1.825

1.985

2.025

1.985

LNK605P, LNK605D

T_J= 25 °C

See Figure 19,

C_BP= 10 mF

LNK606P/G/D

FEEDBACK Pin

Voltage

V_FBth

V

LNK613/614P

LNK613/614/615D

LNK615P

LNK616P/G/D

FEEDBACK Pin

Voltage Temperature

Coefﬁcient

TC_VFB

-0.01

0.72

%/°C

V

FEEDBACK Pin

Voltage at Turn-OFF

Threshold

V_FB(AR)

0.65

0.79

1.035

1.055

1.045

1.065

C_BP= 1 mF

C_BP= 10 mF

C_BP= 1 mF

C_BP= 10 mF

LNK613

See Figure 19

Cable Compensation

Factor

υ_FB

LNK614

See Figure 19

8

Rev. F 01/10

www.powerint.com

LNK603-606/613-616

Conditions

(Unless Otherwi^Jse Speciﬁed)

SOURCE = 0 V; T = 0 to 100 °C

Parameter

Symbol

Min

Typ

Max

Units

Control Functions (cont.)

1.05

1.07

1.06

1.09

4

C_BP= 1 mF

LNK615

See Figure 19

C_BP= 10 mF

Cable Compensation

Factor

υ_FB

C_BP= 1 mF

LNK616

See Figure 19

C_BP= 10 mF

I_FB= -500 mA

f_OSC= 66 kHz

2

I_FB= -1 mA

Switch ON-Time

t_ON

ms

V_FB= V_FBth

(Note 5)

1.33

1

I_FB= -1.5 mA

I_FB= -2 mA

Minimum Switch

ON-Time

t_ON(min)

(Note 5)

700

ns

FEEDBACK Pin

Sampling Delay

t_FB

I_S1

See Figure 19

2.35

2.55

280

2.75

330

ms

FB Voltage > V_FBth

DRAIN Supply

Current

LNK6X3/4

440

480

520

-3.4

-4.8

-2.3

-3.2

520

560

600

-1.8

-2.5

-1.0

-1.4

FB Voltage = V_FBth-0.1,

Switch ON-Time = t_ON

(MOSFET Switching at f_OSC

mA

I_S2

LNK6X5

LNK6X6

)

LNK6X3/4

LNK6X5/6

LNK6X3/4

LNK6X5/6

-5.0

-7.0

-4.0

-5.6

I_CH1

V_BP= 0 V

V_BP= 4 V

BYPASS Pin

Charge Current

mA

I_CH2

BYPASS Pin Voltage

V_BP

V_BPH

5.65

0.70

6.2

6.00

1.00

6.5

6.25

1.20

6.8

V

BYPASS Pin

Voltage Hysteresis

BYPASS Pin

Shunt Voltage

V_SHUNT

Circuit Protection

LNK6X3

di/dt = 50 mA/ms , T_J= 25 °C

186

233

293

382

200

250

315

410

214

267

337

LNK6X4

di/dt = 60 mA/ms , T_J= 25 °C

Current Limit

I_LIMIT

mA

LNK6X5

di/dt = 70 mA/ms , T_J= 25 °C

LNK6X6

di/dt = 100 mA/ms , T_J= 25 °C

438

T_J= 25 °C

See Figure 21, (See Note 6)

T_J= 25 °C

Normalized Output

Current

Leading Edge

Blanking Time

Thermal Shutdown

Temperature

Thermal Shutdown

Hysteresis

I_O

0.975

170

1.000

215

142

60

1.025

t_LEB

T_SD

T_SDH

ns

°C

(See Note 5)

135

150

9

www.powerint.com

Rev. F 01/10

LNK603-606/613-616

Conditions

(Unless Otherwi^Jse Speciﬁed)

SOURCE = 0 V; T = 0 to 100 °C

Parameter

Symbol

Min

Typ

Max

Units

Output

24

36

24

36

16

24

9.6

14

28

42

28

42

19

28

11

17

T_J= 25 °C

LNK6X3

I_D= 50 mA

T_J= 100 °C

T_J= 25 °C

LNK6X4

I_D= 50 mA

T_J= 100 °C

ON-State

Resistance

R_DS(ON)

W

T_J= 25 °C

LNK6X5

I_D= 62 mA

T_J= 100 °C

T_J= 25 °C

LNK6X6

I_D= 82 mA

T_J= 100 °C

V_DS= 560 V See Figure 20

I_DSS1

50

T_J= 125 °C See Note 3

OFF-State

Leakage

mA

V_DS= 375 V See Figure 20

I_DSS2

15

T_J= 50 °C

Breakdown

Voltage

T_J= 25 °C

See Figure 20

BV_DSS

700

50

V

DRAIN Supply

Voltage

t_ON× I_FB= 2 mA-ms, f_OSC= 12 kHz

V_FB= 0

Auto-Restart

ON-Time

t_AR-ON

t_AR-OFF

I_OL

450

1.2

ms

s

See Notes 1, 5

Auto-Restart

OFF-Time

2

Open-Loop

FEEDBACK Pin

Current Threshold

See Note 5

-120

90

mA

ms

Open-Loop

ON-Time

NOTES:

1. Auto-restart ON-time is a function of switching frequency programmed by t_onx I_FBand minimum frequency in CC mode.

2. The current limit threshold is compensated to cancel the effect of current limit delay. As a result the output current stays constant

across the input line range.

3. I_DSS1is the worst case OFF state leakage speciﬁcation at 80% of BV_DSSand maximum operating junction temperature. I_DSS2is a

typical speciﬁcation under worst case application conditions (rectiﬁed 265 VAC) for no-load consumption calculations.

4. When the duty-cycle exceeds DC_MAXthe LinkSwitch-II operates in on-time extension mode.

5. This parameter is derived from characterization.

6. Mechanical stress induced during the assembly may cause shift in this parameter. This shift has no impact on the ability of

LinkSwitch-II to meet 10% in mass production given the design follows recommendation in AN-44 and good manufacturing practice

7. The switching frequency is programmable between 60 kHz and 85 kHz.

10

Rev. F 01/10

www.powerint.com

LNK603-606/613-616

Typical Performance Characteristics

1.200

1.000

0.800

1.000

0.800

0.600

0.400

0.600

0.400

0.200

0.000

0.200

0.000

-40 -15 10 35 60

85 110 135

-40 -15 10 35 60

85 110 135

Temperature (°C)

Figure 9. Current Limit vs. Temperature.

Figure 10. Output Frequency vs. Temperature.

1.200

1.000

0.800

1.000

0.800

0.600

0.400

0.200

0.600

0.400

0.200

0.000

-40 -15 10 35 60

85 110 135

-40 -15 10 35 60

85 110 135

Temperature (°C)

Figure 11. Frequency Ratio vs. Temperature (Constant Current).

Figure 12. Frequency Ratio vs. Temperature (Inductor Current).

1.200

1.000

0.800

1.000

0.800

0.600

0.400

0.600

0.400

0.200

0.000

0.200

0.000

-40 -15 10 35 60

85 110 135

-40 -15 10 35 60

85 110 135

Temperature (°C)

Figure 13. Feedback Voltage vs. Temperature.

Figure 14. Normalized Output Current vs. Temperature.

11

www.powerint.com

Rev. F 01/10

LNK603-606/613-616

Typical Performance Characteristics (cont.)

1.1

300

250

200

150

100

50

T_CASE=25 °C

T_CASE=100 °C

1.0

0.9

Scaling Factors:

LNK6X3 1.0

LNK6X4 1.0

LNK6X5 1.5

LNK6X6 2.5

0

-50 -25

0

25 50 75 100 125 150

0

2

4

6

8

10

Junction Temperature (°C)

DRAIN Voltage (V)

Figure 15. Breakdown vs. Temperature.

Figure 16. Output Characteristic.

50

1000

100

10

40

Scaling Factors:

LNK6X3 1.0

LNK6X4 1.0

LNK6X5 1.5

LNK6X6 2.5

Scaling Factors:

LNK6X3 1.0

LNK6X4 1.0

LNK6X5 1.5

LNK6X6 2.5

30

20

10

0

1

0

200

400

600

0

100 200 300 400 500 600

Drain Voltage (V)

DRAIN Voltage (V)

Figure 18. Drain Capacitance Power.

Figure 17. C_OSSvs. Drain Voltage.

12

Rev. F 01/10

www.powerint.com

LNK603-606/613-616

LinkSwitch-II

FB

BP

S

V_OUT

10 µF

S

+

V_IN

D

6.2 V

500 Ω

+

2 V

PI-4961-022708

1) Raise V_BPvoltage from 0 V to 6.2 V, down to 4.5 V, up to 6.2 V

2) Raise V_INuntil cycle skipping occurs at V_OUTto measure V_FBth

3) Reduce V_INuntil cycle skipping stops at V_OUTto measure V_FBth-. Cable drop compensaion factor is υ_FB= V_FBth/ V_FBth-

4) Apply 1.5 V at V_INand measure t_FBdelay from start of cycle falling edge to the next falling edge

Figure 19. Test Set-up for Feedback Pin Measurements.

LinkSwitch-II

FB

BP

S

1 µF

5 µF

50 kΩ

10 kΩ

4 kΩ

.1 µF

S

D

S1

S2

V_IN

+

16 V

Curve

Tracer

To measure BV_DSS, I_DSS1, and I_DSS2follow these steps:

1) Close S1, open S2

2) Power-up V_INsource (16 V)

3) Open S1, close S2

4) Measure I/V characteristics of Drain pin using the curve tracer

PI-4962-040308

Figure 20. Test Set-up for Leakage and Breakdown Tests.

13

www.powerint.com

Rev. F 01/10

LNK603-606/613-616

470 pF

3.3 V

R_O

680 µF

200 V

+

V_O

200 Ω

11.5 kΩ

+

50 V

LinkSwitch-II

FB

BP

S

7.15 kΩ

S

10 µF

D

1)The transformer inductance is chosen to set the value of t_ON× I_FBto 2 mA × µS

2) R_Ois chosen to operate test circuit in the CC region

3) V_Ois measured

4) Output current is V_O/ R_O

PI-4963-022708

Figure 21. Test Set-up for Output Current Measurements.

14

Rev. F 01/10

www.powerint.com

LNK603-606/613-616

DIP-8C (P Package)

⊕^{D S}^{.004 (.10)}

Notes:

-E-

1. Package dimensions conform to JEDEC specification

MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP)

package with .300 inch row spacing.

2. Controlling dimensions are inches. Millimeter sizes are

shown in parentheses.

.240 (6.10)

.260 (6.60)

3. Dimensions shown do not include mold flash or other

protrusions. Mold flash or protrusions shall not exceed

.006 (.15) on any side.

4. Pin locations start with Pin 1, and continue counter-clock-

wise to Pin 8 when viewed from the top. The notch and/or

dimple are aids in locating Pin 1. Pin 3 is omitted.

5. Minimum metal to metal spacing at the package body for

the omitted lead location is .137 inch (3.48 mm).

6. Lead width measured at package body.

Pin 1

-D-

.367 (9.32)

.387 (9.83)

7. Lead spacing measured with the leads constrained to be

perpendicular to plane T.

.057 (1.45)

.068 (1.73)

(NOTE 6)

.125 (3.18)

.145 (3.68)

.015 (.38)

MINIMUM

-T-

SEATING

PLANE

.008 (.20)

.015 (.38)

.120 (3.05)

.140 (3.56)

.300 (7.62) BSC

(NOTE 7)

.100 (2.54) BSC

.048 (1.22)

.053 (1.35)

.137 (3.48)

MINIMUM

P08C

.300 (7.62)

.390 (9.91)

.014 (.36)

.022 (.56)

⊕^{T E D}^{S .010 (.25) M}

PI-3933-101507

SMD-8C (G Package)

Notes:

⊕ ^{D S .004 (.10)}

.046 .060 .060 .046

1. Controlling dimensions are

inches. Millimeter sizes are

shown in parentheses.

2. Dimensions shown do not

include mold flash or other

protrusions. Mold flash or

protrusions shall not exceed

.006 (.15) on any side.

3. Pin locations start with Pin 1,

and continue counter-clock-

wise to Pin 8 when viewed

from the top. Pin 3 is omitted.

4. Minimum metal to metal

spacing at the package body

for the omitted lead location

is .137 inch (3.48 mm).

-E-

.080

.086

.186

.286

.372 (9.45)

.388 (9.86)

.240 (6.10)

.260 (6.60)

.420

.010 (.25)

⊕ ^{E S}

Pin 1

.137 (3.48)

MINIMUM

5. Lead width measured at

package body.

Solder Pad Dimensions

.100 (2.54) (BSC)

6. D and E are referenced

datums on the package

body.

.367 (9.32)

.387 (9.83)

-D-

.057 (1.45)

.068 (1.73)

(NOTE 5)

.125 (3.18)

.145 (3.68)

.004 (.10)

.032 (.81)

.037 (.94)

.048 (1.22)

.053 (1.35)

°

.009 (.23)

0 - 8

.036 (0.91)

.044 (1.12)

.004 (.10)

.012 (.30)

G08C

PI-4015-101507

15

www.powerint.com

Rev. F 01/10

LNK603-606/613-616

SO-8C

0.10 (0.004)

A-B

2X

C

2

DETAIL A

B

4

4.90 (0.193) BSC

A

4

D

8

5

GAUGE

PLANE

SEATING

PLANE

3.90 (0.154) BSC

6.00 (0.236) BSC

2

0 - 8^o

C

0.25 (0.010)

BSC

1.04 (0.041) REF

0.10 (0.004)

C D

0.40 (0.016)

1.27 (0.050)

2X

1

4

Pin 1 ID

0.20 (0.008) C

2X

7X 0.31 - 0.51 (0.012 - 0.020)

1.27 (0.050) BSC

0.25 (0.010)

M

C A-B D

1.25 - 1.65

1.35 (0.053)

1.75 (0.069)

DETAIL A

(0.049 - 0.065)

H

0.10 (0.004)

0.25 (0.010)

0.10 (0.004)

C

7X

SEATING PLANE

0.17 (0.007)

0.25 (0.010)

C

Reference

Solder Pad

Dimensions

+

Notes:

1. JEDEC reference: MS-012.

2. Package outline exclusive of mold flash and metal burr.

3. Package outline inclusive of plating thickness.

4. Datums A and B to be determined at datum plane H.

2.00 (0.079)

4.90 (0.193)

5. Controlling dimensions are in millimeters. Inch dimensions

are shown in parenthesis. Angles in degrees.

+

1.27 (0.050)

0.60 (0.024)

D07C

PI-4526-040207

Part Ordering Information

• LinkSwitch Product Family

• II Series Number

• Package Identiﬁer

G

P

Plastic Surface Mount DIP

Plastic DIP

D

Plastic SO-8

• Package Material

GREEN: Halogen Free and RoHS Compliant

• Tape & Reel and Other Options

G

Blank

Standard Conﬁgurations

Tape & Reel, 1 k pcs minimum for G Package. 2.5 k pcs for D Package. Not available

for P Package.

LNK 615

D

G - TL

TL

16

Rev. F 01/10

www.powerint.com

LNK603-606/613-616

17

www.powerint.com

Rev. F 01/10

Revision

Notes

Date

06/08

03/09

07/09

01/10

C

D

E

F

Final data sheet

Auto-restart time modiﬁed PCN-09131

Introduced Max current limit when V DRAIN is below 400 V

Added LNK616DG and LNK606DG.

For the latest updates, visit our website: www.powerint.com

Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power

Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES

NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.

Patent Information

The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by

one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A

complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under

certain patent rights as set forth at http://www.powerint.com/ip.htm.

Life Support Policy

POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:

1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii)

whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signiﬁcant

injury or death to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause

the failure of the life support device or system, or to affect its safety or effectiveness.

The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, EcoSmart, Clampless, E-Shield, Filterfuse, StakFET, PI Expert

and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies.

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World Headquarters

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型号:	LNK616PG
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	POWER INTEGRATIONS INC
零件包装代码：	DIP
包装说明：	DIP,
针数：	8
Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01
Factory Lead Time：	14 weeks
风险等级：	2.35
模拟集成电路 - 其他类型：	ANALOG CIRCUIT
JESD-30 代码：	R-PDIP-T8
长度：	9.56 mm
功能数量：	1
端子数量：	8
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装形状：	RECTANGULAR
封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified
表面贴装：	NO
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm

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