LP3470M5X-4.63全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

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产品型号LP3470M5X-4.63的概述

芯片LP3470M5X-4.63概述 LP3470M5X-4.63是一款高精度、低功耗的线性稳压器，广泛应用于便携式设备和各类电子产品中。由于其优异的电源管理能力，LP3470M5X-4.63成为了市场上备受青睐的选择。该芯片能够为多个电源轨提供稳定的电压输出，从而确保电子设备的可靠运行。 LP3470系列芯片以其小巧的体积和高效的功能著称，特别适合于对空间要求严格的应用场合。此系列产品的设计理念强调高性能和经济性，确保在实现高效率和低发热的同时，保证整体系统的可靠性。LP3470M5X-4.63特别适合用于消费电子、工业控制和通信设备等领域。芯片LP3470M5X-4.63的详细参数 LP3470M5X-4.63的主要技术参数包括： - 输入电压范围：2.7V至5.5V - 输出电压：固定为4.63V - 输出电流：最大可达200mA - 静态电流：典型值为20μA - 熄灭电流：...

产品型号LP3470M5X-4.63的Datasheet PDF文件预览

June 1999

LP3470

Tiny Power On Reset Circuit

n Custom Reset Threshold Voltages: For other voltages

between 2.4V and 5.0V contact your National

Semiconductor representative

n Very Low Quiescent Current (16 µA typical)

n Guaranteed Reset valid down to V_CC=0.5V

General Description

The LP3470 is a micropower CMOS voltage supervisory cir-

cuit designed to monitor power supplies in microprocessor

(µP) and other digital systems. It provides maximum adjust-

ability for power-on-reset (POR) and supervisory functions. It

is available in the following six standard reset threshold volt-

age (V_RTH) options: 2.63V, 2.93V, 3.08V, 4.00V, 4.38V, and

4.63V. If other voltage options between 2.4V and 5.0V are

desired please contact your National Semiconductor repre-

sentative.

Features

n Tiny SOT23-5 Package

n Open Drain Reset Output

n Programmable Reset Timeout Period Using an External

Capacitor

The LP3470 asserts a reset signal whenever the V_CCsupply

voltage falls below a reset threshold. The reset time-out pe-

riod is adjustable using an external capacitor. Reset remains

asserted for an interval (programmed by an external capaci-

tor) after V_CChas risen above the threshold voltage.

n Immune to Short V_CCTransients

Applications

n Critical µP and µC Power Monitoring

n Intelligent Instruments

The device is available in the tiny SOT23-5 package.

n Computers

n Portable/Battery-Powered Equipments

Key Specifications

1% Reset Threshold Accuracy Over Temperature

n Standard Reset Threshold Voltages: 2.63V, 2.93V,

3.08V, 4.00V, 4.38V, and 4.63V

Pin Configuration and Basic Operating Circuit

Pin Configuration

Basic Operating Circuit

DS100016-2

Top View

See NS Package Number

MA05B

DS100016-1

DS100016

www.national.com

Ordering Information

Operating

Order

Nominal

V_RTH(V)

Package

Marking

Package

Type

Temperature

Number

Supplied As

Range

LP3470M5-2.63

LP3470M5X-2.63

LP3470M5-2.93

LP3470M5X-2.93

LP3470M5-3.08

2.63

2.93

3.08

4.00

4.38

4.63

2.63

2.93

3.08

4.00

4.38

4.63

D25B

D26B

D28B

D29B

D30B

D31B

D25C

D26C

D28C

D29C

D30C

D31C

SOT23-5

250 Units on Tape and Reel

3k Units on Tape and Reel

250 Units on Tape and Reel

3k Units on Tape and Reel

250 Units on Tape and Reel

3k Units on Tape and Reel

250 Units on Tape and Reel

3k Units on Tape and Reel

250 Units on Tape and Reel

3k Units on Tape and Reel

250 Units on Tape and Reel

3k Units on Tape and Reel

250 Units on Tape and Reel

3k Units on Tape and Reel

250 Units on Tape and Reel

3k Units on Tape and Reel

250 Units on Tape and Reel

3k Units on Tape and Reel

250 Units on Tape and Reel

3k Units on Tape and Reel

250 Units on Tape and Reel

3k Units on Tape and Reel

250 Units on Tape and Reel

3k Units on Tape and Reel

LP3470M5X-3.08

LP3470M5-4.00

LP3470M5X-4.00

LP3470M5-4.38

LP3470M5X-4.38

LP3470M5-4.63

LP3470M5X-4.63

LP3470IM5-2.63

LP3470IM5X-2.63

LP3470IM5-2.93

LP3470IM5X-2.93

LP3470IM5-3.08

LP3470IM5X-3.08

LP3470IM5-4.00

LP3470IM5X-4.00

LP3470IM5-4.38

LP3470IM5X-4.38

LP3470IM5-4.63

LP3470IM5X-4.63

−20˚C to

+85˚C

−40˚C to

+85˚C

www.national.com

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Operating Temperature Range

LP3470

LP3470I

−20˚C to +85˚C

−40˚C to +85˚C

125˚C

Junction Temperature (T_Jmax

)

Power Dissipation (T_A= 25˚C) (Note

300 mW

V_CCVoltage

−0.3V to +6V

10 mA

Reset Voltage

θ_JA(Note 2)

280˚C/W

−65˚C to +150˚C

260˚C

Output Current (Reset)

Storage Temp. Range

Lead Temp. (Soldering, 5 sec)

ESD Rating (Note 3)

2 kV

Electrical Characteristics

Limits in standard typeface are for T_J= 25˚C, and limits in boldface type apply over the full operating temperature range, unless

otherwise specified. V_CC= +2.4V to +5.0V unless otherwise noted.

Symbol

V_CC

Parameter

Operating Voltage Range

V_CCSupply Current

Conditions

Typ (Note 4) Min (Note 5) Max (Note 5) Units

0.5

5.5

I_CC

V_CC= 4.5V

µA

V_RTH

Reset Threshold Voltage

(Note 6)

LP3470

V_RTH

0.99 V_RTH

1.01 V_RTH

LP3470I

V_RTH

0.99 V_RTH

1.01 V_RTH

0.985 V_RTH

1.015 V_RTH

V_HYST

t_PD

Hysteresis Voltage (Note 7)

V_CCto Reset Delay

100

300

3.5

µs

V_CCfalling at 1 mV/µs

C₁= 1 nF

t_RP

Reset Timeout Period (Note

1.0

V_OL

Reset Output Voltage Low

V_CC= 0.5V; I_OL= 30 µA

V_CC= 1.0V; I_OL= 100 µA

0.1

0.4

V_CC=V_RTH−100 mV; I_OL= 4

R₁

External Pull-up Resistor

0.68

kΩ

I_LEAK

Reset Output Leakage

Current

0.15

µA

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Electrical specifications do not apply when operating the device

beyond its operating conditions.

Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by T

(Maximum Junction Temperature), θ (Junction to Am-

Jmax

bient Thermal Resistance), and T (Ambient Temperature). The maximum allowable power dissipation at any temperature is P

= (T

Jmax

− T )/ θ or the number

Dmax

given in the Absolute Maximum Ratings, whichever is lower.

Note 3: The Human Body Model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.

Note 4: Typical numbers are at 25˚C and represent the most likely parametric norm.

Note 5: Min. and Max. limits in standard typeface are 100% production tested at 25˚C. Min. and Max. limits in boldface are guaranteed through correlation using Sta-

tistical Quality Control (SQC) methods. The limits are used to calculate National’s Average Outgoing Quality Level (AOQL).

Note 6: Factory-trimmed reset thresholds are available in 50 mV increments from 2.4V to 5.0V. Contact your National Semiconductor representative.

Note 7:

Note 8:

affects the relation between V and Reset as shown in the timing diagram.

HYST

is programmable by varying the value of the external capacitor (C ) connected to pin SRT. The equation is: t = 2000 x C (C in µF and t in ms).

1 RP 1 1 RP

www.national.com

Typical Operating Characteristics T_A= +25˚C, unless otherwise specified.

I_CCvs Temperture

I_CCvs V_CC

V_CCto Reset Delay vs Temp

DS100016-10

DS100016-13

DS100016-11

Normalized t_RPvs Temp.

Normalized V_RTHvs Temp.

Transient Rejection

DS100016-12

DS100016-8

DS100016-6

V_HYSTvs V_RTH

V_HYSTvs Temperature

DS100016-9

DS100016-14

Pin Description

Name

Function

SRT

Set Reset Time-out Input. Connect a capacitor between this input and ground to select the Reset

Time-out period (t_RP). t_RP= 2000 x C₁(C₁in µF and t_RPin ms). If no capacitor is connected,

leave this pin floating.

GND

V_CC1

V_CC

Ground pin.

Always connect to pin V_CC(Pin 4).

Supply voltage, and reset threshold monitor input.

Reset

Open-Drain, Active-Low reset output. Connect to an external pull-up resistor. Reset changes

from high to low whenever the monitored voltage (V_CC) drops below the reset threshold voltage

(V_RTH). Once V_CCexceeds V_RTH, Reset remains low for the reset timeout period (t_RP) and then

goes high.

www.national.com

Functional Block Diagram

DS100016-3

Pull-up Resistor Selection

Application Information

The LP3470’s Reset output structure is a simple open-drain

N-channel MOSFET switch. A pull-up resistor (R₁) should be

Reset Timeout Period

connected to V_CC

The Reset Timeout Period (t_RP) is programmable using an

external capacitor (C₁) connected to pin SRT of LP3470. A

Ceramic chip capacitor rated at or above 10V is sufficient.

The Reset Timeout Period (t_RP) can be calculated using the

following formula:

R₁should be large enough to limit the current through the

output MOSFET (Q₁) below 10 mA. A resistor value of more

than 680Ω guarantees this. R₁should also be small enough

to ensure a logic high while supplying all the leakage current

through the Reset pin. A resistor value of less than 68kΩ sat-

isfies this condition. A typical pull-up resistor value of 20 kΩ

is sufficient in most applications.

t_RP(ms) = 2000 x C₁(µF).

For example a C₁of 100 nF will achieve a t_RPof 200 ms. If

no delay due to t_RPis needed in a certain application, the pin

SRT should be left floating.

Negative-Going V_CCTransients

The LP3470 is relatively immune to short duration

negative-going V_CCtransients (glitches). The Typical Oper-

ating Characteristics show the Maximum Transient Duration

vs. Negative Transient Amplitude (graph titled Transient Re-

jection), for which reset pulses are not generated. This graph

shows the maximum pulse width a negative-going V_CCtran-

sient may typically have without causing a reset pulse to be

issued. As the transient amplitude increases (i.e. goes far-

ther below the reset threshold), the maximum allowable

pulse width decreases. A 0.1 µF bypass capacitor mounted

close to V_CCprovides additional transient immunity.

Reset Output

In applications like microprocessor (µP) systems, errors

might occur in system operation during power-up,

power-down, or brownout conditions. It is imperative to

monitor the power supply voltage in order to prevent these

errors from occurring.

The LP3470 asserts a reset signal whenever the V_CCsupply

voltage is below a threshold (V_RTH) voltage. Reset is guaran-

teed to be a logic low for V_CC0.5V. Once V_CCexceeds the

reset threshold, the reset is kept asserted for a time period

(t_RP) programmed by an external capacitor (C₁); after this in-

terval Reset goes to logic high. If a brownout condition oc-

curs (monitored voltage falls below the reset threshold minus

a small hysteresis), Reset goes low. When V_CCreturns

above the reset threshold, Reset remains low for a time pe-

riod t_RPbefore going to logic high.

www.national.com

Timing Diagram

DS100016-4

Typical Application Circuit

DS100016-5

www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted

5-Lead Small Outline Package (M5)

For Ordering Information See Ordering Information Table In This Data Sheet

NSPackage Number MA05B

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and

whose failure to perform when properly used in

accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a

significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform

can be reasonably expected to cause the failure of

the life support device or system, or to affect its

safety or effectiveness.

National Semiconductor

Corporation

Americas

Tel: 1-800-272-9959

Fax: 1-800-737-7018

Email: support@nsc.com

National Semiconductor

Europe

National Semiconductor

Asia Pacific Customer

Response Group

Tel: 65-2544466

Fax: 65-2504466

National Semiconductor

Japan Ltd.

Tel: 81-3-5639-7560

Fax: 81-3-5639-7507

Fax: +49 (0) 1 80-530 85 86

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 1 80-530 85 85

English Tel: +49 (0) 1 80-532 78 32

Français Tel: +49 (0) 1 80-532 93 58

Italiano Tel: +49 (0) 1 80-534 16 80

Email: sea.support@nsc.com

www.national.com

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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LP3470M5X-4.63产品参数

型号:	LP3470M5X-4.63
是否Rohs认证：	不符合
生命周期：	Transferred
包装说明：	SOT-23, 5 PIN
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	7.06
其他特性：	RESET THRESHOLD VOLTAGE IS 4.63V
可调阈值：	NO
模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：	R-PDSO-G5
JESD-609代码：	e0
长度：	2.92 mm
湿度敏感等级：	1
信道数量：	1
功能数量：	1
端子数量：	5
最高工作温度：	85 °C
最低工作温度：	-20 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSOP5/6,.11,37
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
电源：	2.4/5 V
认证状态：	Not Qualified
座面最大高度：	1.2 mm
子类别：	Power Management Circuits
最大供电电流 (Isup)：	0.03 mA
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	0.5 V
标称供电电压 (Vsup)：	1 V
表面贴装：	YES
技术：	CMOS
温度等级：	OTHER
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.95 mm
端子位置：	DUAL
阈值电压标称：	+4.63V
处于峰值回流温度下的最长时间：	40
宽度：	1.6 mm
Base Number Matches：	1

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